@ -26,15 +26,22 @@
# define CONFIG_MPC5200
# define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
# define CONFIG_A3M071 /* ... on A3M071 board */
# define CONFIG_MPC5200_DDR /* ... use DDR RAM */
# define CONFIG_SYS_TEXT_BASE 0x01000000 /* boot low for 32 MiB boards */
# define CONFIG_SPL_TARGET "u-boot-img.bin"
# define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33MHz */
# define CONFIG_MISC_INIT_R
# define CONFIG_SYS_LOWBOOT /* Enable lowboot */
# ifdef CONFIG_A4M2K
# define CONFIG_HOSTNAME a4m2k
# else
# define CONFIG_HOSTNAME a3m071
# endif
/*
* Serial console configuration
*/
@ -50,9 +57,6 @@
# define CONFIG_CMD_BSP
# define CONFIG_CMD_CACHE
# define CONFIG_CMD_DATE
# define CONFIG_CMD_EEPROM
# define CONFIG_CMD_I2C
# define CONFIG_CMD_MII
# define CONFIG_CMD_REGINFO
@ -61,7 +65,11 @@
*/
# define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
/* define for 66MHz speed - undef for 33MHz PCI clock speed */
# ifdef CONFIG_A4M2K
# define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
# else
# undef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
# endif
/* pass open firmware flat tree */
# define CONFIG_OF_LIBFDT
@ -76,33 +84,10 @@
# define OF_STDOUT_PATH " / soc5200@f0000000 / serial@2000"
/*
* I2C configuration
*/
# define CONFIG_HARD_I2C /* I2C with hardware support */
# define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
# define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
# define CONFIG_SYS_I2C_SLAVE 0x7F
/*
* EEPROM configuration
*/
# define CONFIG_SYS_I2C_EEPROM_ADDR 0x53
# define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
# define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6
# define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
/*
* RTC configuration
*/
# define CONFIG_RTC_PCF8563
# define CONFIG_SYS_I2C_RTC_ADDR 0x51
/*
* NOR flash configuration
*/
# define CONFIG_SYS_FLASH_BASE 0xfc000000
# define CONFIG_SYS_FLASH_SIZE 0x01 000000
# define CONFIG_SYS_FLASH_SIZE 0x02000000
# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000)
# define CONFIG_SYS_MAX_FLASH_BANKS 1
@ -153,7 +138,11 @@
*/
# define CONFIG_MPC5xxx_FEC
# define CONFIG_MPC5xxx_FEC_MII100
# ifdef CONFIG_A4M2K
# define CONFIG_PHY_ADDR 0x01
# else
# define CONFIG_PHY_ADDR 0x00
# endif
/*
* GPIO configuration
@ -166,19 +155,23 @@
* 2 means fpga ok
*/
# ifdef CONFIG_A4M2K
# define CONFIG_SYS_GPS_PORT_CONFIG 0x0005C805
# else
/* for failsave-level 0 - full failsave */
# define CONFIG_SYS_GPS_PORT_CONFIG 0x1005C005
/* for failsave-level 1 - only digiboard ok */
# define CONFIG_SYS_GPS_PORT_CONFIG_1 0x1005C005
/* for failsave-level 2 - all ok */
# define CONFIG_SYS_GPS_PORT_CONFIG_2 0x1005C005
# endif
/*
* Configuration matrix
* MSB LSB
* failsave 0 0x1005C005 000100000000010111000000011 00101 ( full failsave )
* failsave 1 0x1005C005 000100000000010111000000011 00101 ( digib . - ver ok )
* failsave 2 0x1005C005 000100000000010111000000011 00101 ( all ok )
* failsave 0 0x1005C005 000100000000010111000000000 00101 ( full failsave )
* failsave 1 0x1005C005 000100000000010111000000000 00101 ( digib . - ver ok )
* failsave 2 0x1005C005 000100000000010111000000000 00101 ( all ok )
* | | | | | | | | | | | | | | |
* | | | | | | | | | | | | | | | bit rev name
* + + - + + + - + + - - + - - - + + + - + - - - + - - - + - - - + - 0 31 CS1
@ -254,30 +247,47 @@
# define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
# define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
# define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
# ifdef CONFIG_A4M2K
/* external MRAM */
# define CONFIG_SYS_CS1_START 0xf1000000
# define CONFIG_SYS_CS1_SIZE (512 << 10) /* 512KiB MRAM */
# endif
# define CONFIG_SYS_CS2_START 0xe0000000
# define CONFIG_SYS_CS2_SIZE 0x00100000
/* FPGA slave io (512kiB) - see ticket #66 */
/* FPGA slave io (512kiB / 1MiB ) - see ticket #66 */
# define CONFIG_SYS_CS3_START 0xE9000000
# ifdef CONFIG_A4M2K
# define CONFIG_SYS_CS3_SIZE 0x00100000
# else
# define CONFIG_SYS_CS3_SIZE 0x00080000
# endif
/* 00000000 00110010 1 0 1 1 10 01 00 00 0 0 0 0 = 0x0032B900 */
# define CONFIG_SYS_CS3_CFG 0x0032B900
# ifndef CONFIG_A4M2K
/* Diagnosis Interface - see ticket #63 */
# define CONFIG_SYS_CS4_START 0xEA000000
# define CONFIG_SYS_CS4_SIZE 0x00000001
/* 00000000 00000010 1 0 1 1 10 01 00 00 0 0 0 0 = 0x0002B900 */
# define CONFIG_SYS_CS4_CFG 0x0002B900
# endif
/* FPGA master io (64kiB) - see ticket #66 */
/* FPGA master io (64kiB / 1MiB ) - see ticket #66 */
# define CONFIG_SYS_CS5_START 0xE8000000
# ifdef CONFIG_A4M2K
# define CONFIG_SYS_CS5_SIZE 0x00100000
# else
# define CONFIG_SYS_CS5_SIZE 0x00010000
# endif
/* 00000000 00110010 1 0 1 1 10 01 00 00 0 0 0 0 = 0x0032B900 */
# define CONFIG_SYS_CS5_CFG 0x0032B900
# ifdef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* for pci_clk = 66 MHz */
# define CONFIG_SYS_BOOTCS_CFG 0x0006F900
# define CONFIG_SYS_CS1_CFG 0x0004FB 00
# define CONFIG_SYS_CS1_CFG 0x0008FD 00
# define CONFIG_SYS_CS2_CFG 0x0006F90C
# else /* for pci_clk = 33 MHz */
# define CONFIG_SYS_BOOTCS_CFG 0x0002F900
@ -311,17 +321,25 @@
# define CONFIG_SYS_OS_BASE 0xfc080000
# define CONFIG_SYS_FDT_BASE 0xfc060000
# define xstr(s) str(s)
# define str(s) #s
# define CONFIG_EXTRA_ENV_SETTINGS \
" hostname= " __stringify ( CONFIG_HOSTNAME ) " \0 " \
" netdev=eth0 \0 " \
" verify=no \0 " \
" loadaddr=200000 \0 " \
" kernel_addr= " __stringify ( CONFIG_SYS_OS_BASE ) " \0 " \
" kernel_addr_r=1000000 \0 " \
" fdt_addr= " __stringify ( CONFIG_SYS_FDT_BASE ) " \0 " \
" fdt_addr_r=1800000 \0 " \
" bootfile= " __stringify ( CONFIG_HOSTNAME ) " /uImage \0 " \
" fdtfile= " __stringify ( CONFIG_HOSTNAME ) " / " \
__stringify ( CONFIG_HOSTNAME ) " .dtb \0 " \
" rootpath=/opt/eldk-5.2.1/powerpc/ " \
" core-image-minimal-mtdutils-dropbear-generic \0 " \
" consoledev=ttyPSC0 \0 " \
" nfsargs=setenv bootargs root=/dev/nfs rw " \
" nfsroot=${serverip}:${rootpath} \0 " \
" ramargs=setenv bootargs root=/dev/ram rw \0 " \
" mtdargs=setenv bootargs root=/dev/mtdblock4 rw rootfstype=jffs2 \0 " \
" mtdargs=setenv bootargs root=/dev/mtdblock4 rw rootfstype=jffs2 \0 " \
" addip=setenv bootargs ${bootargs} " \
" ip=${ipaddr}:${serverip}:${gatewayip}:${netmask} " \
" :${hostname}:${netdev}:off panic=1 \0 " \
@ -332,18 +350,18 @@
" flash_mtd=run mtdargs addip addtty; " \
" bootm ${kernel_addr} - ${fdtaddr} \0 " \
" flash_self=run ramargs addip addtty; " \
" bootm ${kernel_addr} ${ramdisk_addr} ${fdtaddr} \0 " \
" net_nfs=sleep 2; tftp ${loadadd r} ${bootfile}; " \
" tftp c00000 ${fdtfile}; " \
" bootm ${kernel_addr} ${ramdisk_addr} ${fdt_ addr} \0 " \
" net_nfs=tftp ${kernel_addr_ r} ${bootfile}; " \
" tftp ${fdt_addr_r} ${fdtfile}; " \
" run nfsargs addip addtty; " \
" bootm ${loadaddr} - c00000 \0 " \
" load=tftp ${loadaddr} u-boot.bin \0 " \
" bootm ${kernel_addr_r} - ${fdt_addr_r} \0 " \
" load=tftp ${loadaddr} " __stringify ( CONFIG_HOSTNAME ) \
" /u-boot-img.bin \0 " \
" update=protect off fc000000 fc03ffff; " \
" era fc000000 fc03ffff; cp.b ${loadaddr} fc000000 40000 \0 " \
" era fc000000 fc03ffff; cp.b ${loadaddr} fc000000 40000 \0 " \
" upd=run load;run update \0 " \
" fdtaddr= " xstr ( CONFIG_SYS_FDT_BASE ) " \0 " \
" fdtfile=dtbFile \0 " \
" kernel_addr= " xstr ( CONFIG_SYS_OS_BASE ) " \0 " \
" bootdelay=3 \0 " \
" bootcmd=run net_nfs \0 " \
" "
# define CONFIG_BOOTCOMMAND "run flash_mtd"
@ -353,6 +371,7 @@
*/
# define CONFIG_SPL
# define CONFIG_SPL_FRAMEWORK
# define CONFIG_SPL_BOARD_INIT
# define CONFIG_SPL_NOR_SUPPORT
# define CONFIG_SPL_TEXT_BASE 0xfc000000
# define CONFIG_SPL_START_S_PATH "arch / powerpc / cpu / mpc5xxx"