ppc4xx: remove PMC405 board

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
master
Matthias Fuchs 10 years ago committed by Tom Rini
parent dbe7bb0d21
commit d526330479
  1. 4
      arch/powerpc/cpu/ppc4xx/Kconfig
  2. 12
      board/esd/pmc405/Kconfig
  3. 6
      board/esd/pmc405/MAINTAINERS
  4. 13
      board/esd/pmc405/Makefile
  5. 142
      board/esd/pmc405/pmc405.c
  6. 3
      configs/PMC405_defconfig
  7. 1
      doc/README.scrapyard
  8. 318
      include/configs/PMC405.h

@ -128,9 +128,6 @@ config TARGET_CPCI405DT
config TARGET_PLU405
bool "Support PLU405"
config TARGET_PMC405
bool "Support PMC405"
config TARGET_PMC405DE
bool "Support PMC405DE"
@ -224,7 +221,6 @@ source "board/dave/PPChameleonEVB/Kconfig"
source "board/esd/cpci2dp/Kconfig"
source "board/esd/cpci405/Kconfig"
source "board/esd/plu405/Kconfig"
source "board/esd/pmc405/Kconfig"
source "board/esd/pmc405de/Kconfig"
source "board/esd/pmc440/Kconfig"
source "board/esd/voh405/Kconfig"

@ -1,12 +0,0 @@
if TARGET_PMC405
config SYS_BOARD
default "pmc405"
config SYS_VENDOR
default "esd"
config SYS_CONFIG_NAME
default "PMC405"
endif

@ -1,6 +0,0 @@
PMC405 BOARD
M: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
S: Maintained
F: board/esd/pmc405/
F: include/configs/PMC405.h
F: configs/PMC405_defconfig

@ -1,13 +0,0 @@
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# SPDX-License-Identifier: GPL-2.0+
#
# Objects for Xilinx JTAG programming (CPLD)
CPLD = ../common/xilinx_jtag/lenval.o \
../common/xilinx_jtag/micro.o \
../common/xilinx_jtag/ports.o
obj-y = pmc405.o ../common/misc.o ../common/cmd_loadpci.o $(CPLD)

@ -1,142 +0,0 @@
/*
* (C) Copyright 2001-2003
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* (C) Copyright 2005-2009
* Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <command.h>
#include <malloc.h>
DECLARE_GLOBAL_DATA_PTR;
extern void lxt971_no_sleep(void);
int board_early_init_f (void)
{
/*
* IRQ 0-15 405GP internally generated; active high; level sensitive
* IRQ 16 405GP internally generated; active low; level sensitive
* IRQ 17-24 RESERVED
* IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
* IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
* IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
* IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
* IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
* IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
* IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
*/
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
mtdcr(UIC0ER, 0x00000000); /* disable all ints */
mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
mtdcr(UIC0PR, 0xFFFFFF81); /* set int polarities */
mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
mtdcr(UIC0VCR, 0x00000001); /* set vect base=0, INT0 highest priority */
mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
/*
* EBC Configuration Register:
* set ready timeout to 512 ebc-clks -> ca. 15 us
*/
mtebc (EBC0_CFG, 0xa8400000);
/*
* Setup GPIO pins
*/
mtdcr(CPC0_CR0, mfdcr(CPC0_CR0) | ((CONFIG_SYS_FPGA_INIT |
CONFIG_SYS_FPGA_DONE |
CONFIG_SYS_XEREADY |
CONFIG_SYS_NONMONARCH |
CONFIG_SYS_REV1_2) << 5));
if (!(in_be32((void *)GPIO0_IR) & CONFIG_SYS_REV1_2)) {
/* rev 1.2 boards */
mtdcr(CPC0_CR0, mfdcr(CPC0_CR0) | ((CONFIG_SYS_INTA_FAKE |
CONFIG_SYS_SELF_RST) << 5));
}
out_be32((void *)GPIO0_OR, CONFIG_SYS_VPEN);
/* setup for output */
out_be32((void *)GPIO0_TCR, CONFIG_SYS_FPGA_PRG | CONFIG_SYS_FPGA_CLK |
CONFIG_SYS_FPGA_DATA | CONFIG_SYS_XEREADY | CONFIG_SYS_VPEN);
/*
* - check if rev1_2 is low, then:
* - set/reset CONFIG_SYS_INTA_FAKE/CONFIG_SYS_SELF_RST
* in TCR to assert INTA# or SELFRST#
*/
return 0;
}
int misc_init_r (void)
{
/* adjust flash start and offset */
gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
gd->bd->bi_flashoffset = 0;
/* deassert EREADY# */
out_be32((void *)GPIO0_OR,
in_be32((void *)GPIO0_OR) | CONFIG_SYS_XEREADY);
return (0);
}
ushort pmc405_pci_subsys_deviceid(void)
{
ulong val;
val = in_be32((void *)GPIO0_IR);
if (!(val & CONFIG_SYS_REV1_2)) { /* low=rev1.2 */
/* check monarch# signal */
if (val & CONFIG_SYS_NONMONARCH)
return CONFIG_SYS_PCI_SUBSYS_DEVICEID_NONMONARCH;
return CONFIG_SYS_PCI_SUBSYS_DEVICEID_MONARCH;
}
return CONFIG_SYS_PCI_SUBSYS_DEVICEID_NONMONARCH;
}
/*
* Check Board Identity
*/
int checkboard (void)
{
ulong val;
char str[64];
int i = getenv_f("serial#", str, sizeof(str));
puts ("Board: ");
if (i == -1)
puts ("### No HW ID - assuming PMC405");
else
puts(str);
val = in_be32((void *)GPIO0_IR);
if (!(val & CONFIG_SYS_REV1_2)) { /* low=rev1.2 */
puts(" rev1.2 (");
if (val & CONFIG_SYS_NONMONARCH) /* monarch# signal */
puts("non-");
puts("monarch)");
} else
puts(" <=rev1.1");
putc ('\n');
return 0;
}
void reset_phy(void)
{
#ifdef CONFIG_LXT971_NO_SLEEP
/*
* Disable sleep mode in LXT971
*/
lxt971_no_sleep();
#endif
}

@ -1,3 +0,0 @@
CONFIG_PPC=y
CONFIG_4xx=y
CONFIG_TARGET_PMC405=y

@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order.
Board Arch CPU Commit Removed Last known maintainer/contact
=================================================================================================
PMC405 ppc4xx 405gp - - Matthias Fuchs <matthias.fuchs@esd.eu>
PCI405 ppc4xx 405gp - - Matthias Fuchs <matthias.fuchs@esd.eu>
OCRTC ppc4xx 405gpr - - Matthias Fuchs <matthias.fuchs@esd.eu>
HUB405 ppc4xx 405ep - - Matthias Fuchs <matthias.fuchs@esd.eu>

@ -1,318 +0,0 @@
/*
* (C) Copyright 2001-2004
* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*
* High Level Configuration Options
*/
#define CONFIG_405GP 1 /* This is a PPC405 CPU */
#define CONFIG_PMC405 1 /* ...on a PMC405 board */
#define CONFIG_SYS_TEXT_BASE 0xFFF80000
#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
#define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */
#define CONFIG_BAUDRATE 9600
#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
/* Only interrupt boot if space is pressed. */
#define CONFIG_AUTOBOOT_KEYED 1
#define CONFIG_AUTOBOOT_PROMPT \
"Press SPACE to abort autoboot in %d seconds\n", bootdelay
#undef CONFIG_AUTOBOOT_DELAY_STR
#define CONFIG_AUTOBOOT_STOP_STR " "
#undef CONFIG_BOOTARGS
#undef CONFIG_BOOTCOMMAND
#define CONFIG_PREBOOT /* enable preboot variable */
#define CFG_BOOTM_LEN 0x1000000 /* support booting of huge images */
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#undef CONFIG_HAS_ETH1
#define CONFIG_PPC4xx_EMAC
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 0 /* PHY address */
#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
#define CONFIG_RESET_PHY_R 1 /* use reset_phy() */
/*
* BOOTP options
*/
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_BSP
#define CONFIG_CMD_PCI
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_ELF
#define CONFIG_CMD_DATE
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_MII
#define CONFIG_CMD_I2C
#define CONFIG_CMD_PING
#define CONFIG_CMD_UNIVERSE
#define CONFIG_CMD_EEPROM
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible */
#define CONFIG_SYS_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */
#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Sz */
#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console info */
#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
#define CONFIG_CONS_INDEX 1 /* Use UART0 */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock */
#define CONFIG_SYS_BASE_BAUD 806400
/* The following table includes the supported baudrates */
#define CONFIG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
#define CONFIG_LOOPW 1 /* enable loopw command */
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
#define CONFIG_SYS_RX_ETH_BUFFER 16
/*
* PCI stuff
*/
#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
#define PCI_HOST_FORCE 1 /* configure as pci host */
#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
#define CONFIG_PCI /* include pci support */
#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */
#define CONFIG_PCI_PNP /* do pci plug-and-play */
/* resource configuration */
#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config */
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
#define CONFIG_SYS_PCI_SUBSYS_DEVICEID_NONMONARCH 0x0408 /* PCI Device ID */
#define CONFIG_SYS_PCI_SUBSYS_DEVICEID_MONARCH 0x0409 /* PCI Device ID */
#define CONFIG_SYS_PCI_SUBSYS_DEVICEID pmc405_pci_subsys_deviceid()
#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* Processor/PPC */
#define CONFIG_SYS_PCI_PTM1LA (bd->bi_memstart) /* point to sdram */
#define CONFIG_SYS_PCI_PTM1MS (~(bd->bi_memsize - 1) | 1) /* memsize, enable */
#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
#define CONFIG_SYS_PCI_PTM2LA 0xef000000 /* point to internal regs */
#define CONFIG_SYS_PCI_PTM2MS 0xff000001 /* 16MB, enable */
#define CONFIG_SYS_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */
#define CONFIG_PCI_4xx_PTM_OVERWRITE 1 /* overwrite PTMx settings by env */
/*
* Start addresses for the final memory configuration
* (Set up by the startup code)
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
*/
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN (~(CONFIG_SYS_TEXT_BASE) + 1)
#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* 128 kB for malloc() */
#define CONFIG_PRAM 0 /* use pram variable to overwrite */
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*
* FLASH organization
*/
#define CONFIG_SYS_FLASH_BASE 0xFE000000
#define CONFIG_SYS_FLASH_INCREMENT 0x01000000
#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
#define CONFIG_SYS_FLASH_PROTECTION 1 /* don't use hardware protection */
#define CONFIG_SYS_FLASH_AUTOPROTECT_LIST {{0xfff80000, 0x80000}}
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (faster) */
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of flash banks */
#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, \
CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_INCREMENT}
#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */
#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on fli */
/*
* Environment Variable setup
*/
#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
/* environment starts at the beginning of the EEPROM */
#define CONFIG_ENV_OFFSET 0x000
#define CONFIG_ENV_SIZE 0x800 /* 2048 bytes may be used for env vars */
#define CONFIG_SYS_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */
#define CONFIG_SYS_NVRAM_SIZE 242 /* NVRAM size */
/*
* I2C EEPROM (CAT24WC16) for environment
*/
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_PPC4XX
#define CONFIG_SYS_I2C_PPC4XX_CH0
#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000
#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT24W16 */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
/* mask of address bits that overflow into the "EEPROM chip address" */
#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24W16 has */
/* 16 byte page write mode using*/
/* last 4 bits of the address */
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
/*
* External Bus Controller (EBC) Setup
*/
#define FLASH0_BA 0xFF000000 /* FLASH 0 Base Address */
#define FLASH1_BA 0xFE000000 /* FLASH 1 Base Address */
#define CAN_BA 0xF0000000 /* CAN Base Addres */
#define RTC_BA 0xF0000500 /* RTC Base Address */
#define NVRAM_BA 0xF0200000 /* NVRAM Base Address */
/* Memory Bank 0 (Flash Bank 0) initialization */
#define CONFIG_SYS_EBC_PB0AP 0x92015480
/* BAS=0xFF0,BS=16MB,BU=R/W,BW=16bit */
#define CONFIG_SYS_EBC_PB0CR (FLASH0_BA | 0x9A000)
/* Memory Bank 1 (Flash Bank 1) initialization */
#define CONFIG_SYS_EBC_PB1AP 0x92015480
/* BAS=0xFE0,BS=16MB,BU=R/W,BW=16bit*/
#define CONFIG_SYS_EBC_PB1CR (FLASH1_BA | 0x9A000)
/* Memory Bank 2 (CAN0, 1, RTC) initialization */
/* TWT=5,TH=2,CSN=0,OEN=0,WBN=0,WBF=0 */
#define CONFIG_SYS_EBC_PB2AP 0x03000440
/* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
#define CONFIG_SYS_EBC_PB2CR (CAN_BA | 0x18000)
/* Memory Bank 3 -> unused */
/* Memory Bank 4 (NVRAM) initialization */
/* TWT=5,TH=2,CSN=0,OEN=0,WBN=0,WBF=0 */
#define CONFIG_SYS_EBC_PB4AP 0x03000440
/* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
#define CONFIG_SYS_EBC_PB4CR (NVRAM_BA | 0x18000)
/*
* FPGA stuff
*/
/* FPGA program pin configuration */
#define CONFIG_SYS_FPGA_PRG 0x04000000 /* JTAG TMS pin (output) */
#define CONFIG_SYS_FPGA_CLK 0x02000000 /* JTAG TCK pin (output) */
#define CONFIG_SYS_FPGA_DATA 0x01000000 /* JTAG TDO pin (output) */
#define CONFIG_SYS_FPGA_INIT 0x00010000 /* unused (ppc input) */
#define CONFIG_SYS_FPGA_DONE 0x00008000 /* JTAG TDI pin (input) */
/* pass Ethernet MAC to VxWorks */
#define CONFIG_SYS_VXWORKS_MAC_PTR 0x00000000
/*
* GPIOs
*/
#define CONFIG_SYS_VPEN (0x80000000 >> 3) /* GPIO3 */
#define CONFIG_SYS_NONMONARCH (0x80000000 >> 14) /* GPIO14 */
#define CONFIG_SYS_XEREADY (0x80000000 >> 15) /* GPIO15 */
#define CONFIG_SYS_INTA_FAKE (0x80000000 >> 19) /* GPIO19 */
#define CONFIG_SYS_SELF_RST (0x80000000 >> 21) /* GPIO21 */
#define CONFIG_SYS_REV1_2 (0x80000000 >> 23) /* GPIO23 */
/*
* Definitions for initial stack pointer and data area (in data cache)
*/
/* use on chip memory (OCM) for temperary stack until sdram is tested */
#define CONFIG_SYS_TEMP_STACK_OCM 1
/* On Chip Memory location */
#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
/* inside of SDRAM */
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR
/* End of used area in RAM */
#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_OF_LIBFDT
#define CONFIG_OF_BOARD_SETUP
#endif /* __CONFIG_H */
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