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@ -177,6 +177,34 @@ static void mctl_set_master_priority_a64(void) |
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writel(0x81000004, &mctl_com->mdfs_bwlr[2]); |
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} |
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static void mctl_set_master_priority_h5(void) |
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{ |
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struct sunxi_mctl_com_reg * const mctl_com = |
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(struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE; |
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/* enable bandwidth limit windows and set windows size 1us */ |
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writel(399, &mctl_com->tmr); |
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writel((1 << 16), &mctl_com->bwcr); |
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/* set cpu high priority */ |
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writel(0x00000001, &mctl_com->mapr); |
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/* Port 2 is reserved per Allwinner's linux-3.10 source, yet
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* they initialise it */ |
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MBUS_CONF( CPU, true, HIGHEST, 0, 300, 260, 150); |
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MBUS_CONF( GPU, true, HIGHEST, 0, 600, 400, 200); |
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MBUS_CONF(UNUSED, true, HIGHEST, 0, 512, 256, 96); |
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MBUS_CONF( DMA, true, HIGHEST, 0, 256, 128, 32); |
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MBUS_CONF( VE, true, HIGHEST, 0, 1900, 1500, 1000); |
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MBUS_CONF( CSI, true, HIGHEST, 0, 150, 120, 100); |
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MBUS_CONF( NAND, true, HIGH, 0, 256, 128, 64); |
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MBUS_CONF( SS, true, HIGHEST, 0, 256, 128, 64); |
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MBUS_CONF( TS, true, HIGHEST, 0, 256, 128, 64); |
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MBUS_CONF( DI, true, HIGH, 0, 1024, 256, 64); |
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MBUS_CONF( DE, true, HIGHEST, 3, 3400, 2400, 1024); |
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MBUS_CONF(DE_CFD, true, HIGHEST, 0, 600, 400, 200); |
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} |
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static void mctl_set_master_priority(uint16_t socid) |
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{ |
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switch (socid) { |
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@ -186,6 +214,9 @@ static void mctl_set_master_priority(uint16_t socid) |
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case SOCID_A64: |
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mctl_set_master_priority_a64(); |
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return; |
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case SOCID_H5: |
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mctl_set_master_priority_h5(); |
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return; |
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} |
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} |
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@ -256,7 +287,7 @@ static void mctl_set_timing_params(uint16_t socid, struct dram_para *para) |
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/* set two rank timing */ |
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clrsetbits_le32(&mctl_ctl->dramtmg[8], (0xff << 8) | (0xff << 0), |
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(0x66 << 8) | (0x10 << 0)); |
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((socid == SOCID_H5 ? 0x33 : 0x66) << 8) | (0x10 << 0)); |
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/* set PHY interface timing, write latency and read latency configure */ |
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writel((0x2 << 24) | (t_rdata_en << 16) | (0x1 << 8) | |
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@ -391,7 +422,7 @@ static void mctl_sys_init(uint16_t socid, struct dram_para *para) |
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CCM_DRAMCLK_CFG_DIV(1) | |
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CCM_DRAMCLK_CFG_SRC_PLL11 | |
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CCM_DRAMCLK_CFG_UPD); |
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} else if (socid == SOCID_H3) { |
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} else if (socid == SOCID_H3 || socid == SOCID_H5) { |
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clock_set_pll5(CONFIG_DRAM_CLK * 2 * 1000000, false); |
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clrsetbits_le32(&ccm->dram_clk_cfg, |
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CCM_DRAMCLK_CFG_DIV_MASK | |
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@ -410,7 +441,7 @@ static void mctl_sys_init(uint16_t socid, struct dram_para *para) |
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setbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_RST); |
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udelay(10); |
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writel(0xc00e, &mctl_ctl->clken); |
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writel(socid == SOCID_H5 ? 0x8000 : 0xc00e, &mctl_ctl->clken); |
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udelay(500); |
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} |
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@ -434,7 +465,10 @@ static int mctl_channel_init(uint16_t socid, struct dram_para *para) |
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/* setting VTC, default disable all VT */ |
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clrbits_le32(&mctl_ctl->pgcr[0], (1 << 30) | 0x3f); |
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clrsetbits_le32(&mctl_ctl->pgcr[1], 1 << 24, 1 << 26); |
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if (socid == SOCID_H5) |
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setbits_le32(&mctl_ctl->pgcr[1], (1 << 24) | (1 << 26)); |
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else |
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clrsetbits_le32(&mctl_ctl->pgcr[1], 1 << 24, 1 << 26); |
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/* increase DFI_PHY_UPD clock */ |
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writel(PROTECT_MAGIC, &mctl_com->protect); |
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@ -444,15 +478,22 @@ static int mctl_channel_init(uint16_t socid, struct dram_para *para) |
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udelay(100); |
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/* set dramc odt */ |
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for (i = 0; i < 4; i++) |
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clrsetbits_le32(&mctl_ctl->dx[i].gcr, (0x3 << 4) | |
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(0x1 << 1) | (0x3 << 2) | (0x3 << 12) | |
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(0x3 << 14), |
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IS_ENABLED(CONFIG_DRAM_ODT_EN) ? |
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DX_GCR_ODT_DYNAMIC : DX_GCR_ODT_OFF); |
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for (i = 0; i < 4; i++) { |
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u32 clearmask = (0x3 << 4) | (0x1 << 1) | (0x3 << 2) | |
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(0x3 << 12) | (0x3 << 14); |
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u32 setmask = IS_ENABLED(CONFIG_DRAM_ODT_EN) ? |
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DX_GCR_ODT_DYNAMIC : DX_GCR_ODT_OFF; |
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if (socid == SOCID_H5) { |
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clearmask |= 0x2 << 8; |
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setmask |= 0x4 << 8; |
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} |
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clrsetbits_le32(&mctl_ctl->dx[i].gcr, clearmask, setmask); |
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} |
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/* AC PDR should always ON */ |
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setbits_le32(&mctl_ctl->aciocr, 0x1 << 1); |
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clrsetbits_le32(&mctl_ctl->aciocr, socid == SOCID_H5 ? (0x1 << 11) : 0, |
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0x1 << 1); |
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/* set DQS auto gating PD mode */ |
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setbits_le32(&mctl_ctl->pgcr[2], 0x3 << 6); |
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@ -464,7 +505,7 @@ static int mctl_channel_init(uint16_t socid, struct dram_para *para) |
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/* dphy & aphy phase select 270 degree */ |
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clrsetbits_le32(&mctl_ctl->pgcr[2], (0x3 << 10) | (0x3 << 8), |
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(0x1 << 10) | (0x2 << 8)); |
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} else if (socid == SOCID_A64) { |
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} else if (socid == SOCID_A64 || socid == SOCID_H5) { |
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/* dphy & aphy phase select ? */ |
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clrsetbits_le32(&mctl_ctl->pgcr[2], (0x3 << 10) | (0x3 << 8), |
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(0x0 << 10) | (0x3 << 8)); |
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@ -488,11 +529,12 @@ static int mctl_channel_init(uint16_t socid, struct dram_para *para) |
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mctl_phy_init(PIR_PLLINIT | PIR_DCAL | PIR_PHYRST | |
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PIR_DRAMRST | PIR_DRAMINIT | PIR_QSGATE); |
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} else if (socid == SOCID_A64) { |
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} else if (socid == SOCID_A64 || socid == SOCID_H5) { |
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clrsetbits_le32(&mctl_ctl->zqcr, 0xffffff, CONFIG_DRAM_ZQ); |
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mctl_phy_init(PIR_ZCAL | PIR_PLLINIT | PIR_DCAL | PIR_PHYRST | |
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PIR_DRAMRST | PIR_DRAMINIT | PIR_QSGATE); |
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/* no PIR_QSGATE for H5 ???? */ |
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} |
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/* detect ranks and bus width */ |
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@ -533,7 +575,7 @@ static int mctl_channel_init(uint16_t socid, struct dram_para *para) |
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/* set PGCR3, CKE polarity */ |
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if (socid == SOCID_H3) |
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writel(0x00aa0060, &mctl_ctl->pgcr[3]); |
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else if (socid == SOCID_A64) |
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else if (socid == SOCID_A64 || socid == SOCID_H5) |
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writel(0xc0aa0060, &mctl_ctl->pgcr[3]); |
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/* power down zq calibration module for power save */ |
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@ -604,6 +646,22 @@ static void mctl_auto_detect_dram_size(struct dram_para *para) |
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3, 4, 0, 3, 4, 1, 4, 0, \
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1, 1, 0, 1, 13, 5, 4 } |
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#define SUN8I_H5_DX_READ_DELAYS \ |
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{{ 14, 15, 17, 17, 17, 17, 17, 18, 17, 3, 3 }, \
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{ 21, 21, 12, 22, 21, 21, 21, 21, 21, 3, 3 }, \
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{ 16, 19, 19, 17, 22, 22, 21, 22, 19, 3, 3 }, \
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{ 21, 21, 22, 22, 20, 21, 19, 19, 19, 3, 3 } } |
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#define SUN8I_H5_DX_WRITE_DELAYS \ |
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{{ 1, 2, 3, 4, 3, 4, 4, 4, 6, 6, 6 }, \
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{ 6, 6, 6, 5, 5, 5, 5, 5, 6, 6, 6 }, \
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{ 0, 2, 4, 2, 6, 5, 5, 5, 6, 6, 6 }, \
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{ 3, 3, 3, 2, 2, 1, 1, 1, 4, 4, 4 } } |
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#define SUN8I_H5_AC_DELAYS \ |
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{ 0, 0, 5, 5, 0, 0, 0, 0, \
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0, 0, 0, 0, 3, 3, 3, 3, \
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3, 3, 3, 3, 3, 3, 3, 3, \
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3, 3, 3, 3, 2, 0, 0 } |
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unsigned long sunxi_dram_init(void) |
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{ |
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struct sunxi_mctl_com_reg * const mctl_com = |
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@ -625,6 +683,10 @@ unsigned long sunxi_dram_init(void) |
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.dx_read_delays = SUN50I_A64_DX_READ_DELAYS, |
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.dx_write_delays = SUN50I_A64_DX_WRITE_DELAYS, |
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.ac_delays = SUN50I_A64_AC_DELAYS, |
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#elif defined(CONFIG_MACH_SUN50I_H5) |
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.dx_read_delays = SUN8I_H5_DX_READ_DELAYS, |
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.dx_write_delays = SUN8I_H5_DX_WRITE_DELAYS, |
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.ac_delays = SUN8I_H5_AC_DELAYS, |
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#endif |
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}; |
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/*
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@ -636,6 +698,8 @@ unsigned long sunxi_dram_init(void) |
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uint16_t socid = SOCID_H3; |
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#elif defined(CONFIG_MACH_SUN50I) |
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uint16_t socid = SOCID_A64; |
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#elif defined(CONFIG_MACH_SUN50I_H5) |
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uint16_t socid = SOCID_H5; |
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#endif |
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mctl_sys_init(socid, ¶); |
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@ -652,8 +716,9 @@ unsigned long sunxi_dram_init(void) |
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if (socid == SOCID_H3) |
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writel(0x0c000400, &mctl_ctl->odtcfg); |
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if (socid == SOCID_A64) { |
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setbits_le32(&mctl_ctl->vtfcr, 2 << 8); |
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if (socid == SOCID_A64 || socid == SOCID_H5) { |
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setbits_le32(&mctl_ctl->vtfcr, |
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(socid == SOCID_H5 ? 3 : 2) << 8); |
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clrbits_le32(&mctl_ctl->pgcr[2], (1 << 13)); |
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} |
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Tom Rini
7 years ago