diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c
index 8c3b92c..e9bb0d7 100644
--- a/arch/x86/cpu/cpu.c
+++ b/arch/x86/cpu/cpu.c
@@ -140,6 +140,14 @@ int cpu_init_f(void) __attribute__((weak, alias("x86_cpu_init_f")));
 
 int x86_cpu_init_r(void)
 {
+	/* Initialize core interrupt and exception functionality of CPU */
+	cpu_init_interrupts();
+	return 0;
+}
+int cpu_init_r(void) __attribute__((weak, alias("x86_cpu_init_r")));
+
+void x86_enable_caches(void)
+{
 	const u32 nw_cd_rst = ~(X86_CR0_NW | X86_CR0_CD);
 
 	/* turn on the cache and disable write through */
@@ -147,12 +155,16 @@ int x86_cpu_init_r(void)
 	    "andl	%0, %%eax\n"
 	    "movl	%%eax, %%cr0\n"
 	    "wbinvd\n" : : "i" (nw_cd_rst) : "eax");
+}
+void enable_caches(void) __attribute__((weak, alias("x86_enable_caches")));
+
+int x86_init_cache(void)
+{
+	enable_caches();
 
-	/* Initialize core interrupt and exception functionality of CPU */
-	cpu_init_interrupts();
 	return 0;
 }
-int cpu_init_r(void) __attribute__((weak, alias("x86_cpu_init_r")));
+int init_cache(void) __attribute__((weak, alias("x86_init_cache")));
 
 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
diff --git a/arch/x86/include/asm/u-boot-x86.h b/arch/x86/include/asm/u-boot-x86.h
index 5540d51..878a1ee 100644
--- a/arch/x86/include/asm/u-boot-x86.h
+++ b/arch/x86/include/asm/u-boot-x86.h
@@ -39,6 +39,7 @@ int x86_cpu_init_f(void);
 int cpu_init_f(void);
 void init_gd(gd_t *id, u64 *gdt_addr);
 void setup_gdt(gd_t *id, u64 *gdt_addr);
+int init_cache(void);
 
 /* cpu/.../timer.c */
 void timer_isr(void *);
diff --git a/arch/x86/lib/board.c b/arch/x86/lib/board.c
index 3d82165..56acf35 100644
--- a/arch/x86/lib/board.c
+++ b/arch/x86/lib/board.c
@@ -140,6 +140,7 @@ init_fnc_t *init_sequence_f[] = {
 
 init_fnc_t *init_sequence_r[] = {
 	copy_gd_to_ram,
+	init_cache,
 	cpu_init_r,		/* basic cpu dependent setup */
 	board_early_init_r,	/* basic board dependent setup */
 	dram_init,		/* configure available RAM banks */