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@ -113,4 +113,142 @@ typedef struct at91_matrix { |
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#define AT91_MATRIX_CSA_EBI1_CS2A 0x00000008 |
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#if defined CONFIG_AT91SAM9261 |
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/* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ |
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#define AT91_MATRIX_MCFG_RCB0 (1 << 0) |
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/* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ |
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#define AT91_MATRIX_MCFG_RCB1 (1 << 1) |
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#endif |
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/* Undefined Length Burst Type */ |
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#if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9263) || \ |
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defined(CONFIG_AT91SAM9G45) |
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#define AT91_MATRIX_MCFG_ULBT_INFINITE 0x00000000 |
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#define AT91_MATRIX_MCFG_ULBT_SINGLE 0x00000001 |
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#define AT91_MATRIX_MCFG_ULBT_FOUR 0x00000002 |
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#define AT91_MATRIX_MCFG_ULBT_EIGHT 0x00000003 |
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#define AT91_MATRIX_MCFG_ULBT_SIXTEEN 0x00000004 |
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#endif |
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#if defined(CONFIG_AT91SAM9G45) |
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#define AT91_MATRIX_MCFG_ULBT_THIRTYTWO 0x00000005 |
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#define AT91_MATRIX_MCFG_ULBT_SIXTYFOUR 0x00000006 |
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#define AT91_MATRIX_MCFG_ULBT_128 0x00000007 |
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#endif |
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/* Default Master Type */ |
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#define AT91_MATRIX_SCFG_DEFMSTR_TYPE_NONE 0x00000000 |
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#define AT91_MATRIX_SCFG_DEFMSTR_TYPE_LAST 0x00010000 |
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#define AT91_MATRIX_SCFG_DEFMSTR_TYPE_FIXED 0x00020000 |
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/* Fixed Index of Default Master */ |
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#if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9263) |
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#define AT91_MATRIX_SCFG_FIXED_DEFMSTR(x) ((x & 0xf) << 18) |
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#elif defined(CONFIG_AT91SAM9261) || defined(CONFIG_AT91SAM9260) |
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#define AT91_MATRIX_SCFG_FIXED_DEFMSTR(x) ((x & 7) << 18) |
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#endif |
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/* Maximum Number of Allowed Cycles for a Burst */ |
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#if defined(CONFIG_AT91SAM9G45) |
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#define AT91_MATRIX_SCFG_SLOT_CYCLE(x) ((x & 0x1ff) << 0) |
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#elif defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9261) || \ |
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defined(CONFIG_AT91SAM9263) |
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#define AT91_MATRIX_SCFG_SLOT_CYCLE(x) ((x & 0xff) << 0) |
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#endif |
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/* Arbitration Type */ |
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#if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9263) |
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#define AT91_MATRIX_SCFG_ARBT_ROUND_ROBIN 0x00000000 |
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#define AT91_MATRIX_SCFG_ARBT_FIXED_PRIORITY 0x01000000 |
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#endif |
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/* Master Remap Control Register */ |
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#if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9263) || \ |
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defined(CONFIG_AT91SAM9G45) |
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/* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ |
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#define AT91_MATRIX_MRCR_RCB0 (1 << 0) |
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/* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ |
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#define AT91_MATRIX_MRCR_RCB1 (1 << 1) |
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#endif |
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#if defined(CONFIG_AT91SAM9263) || defined(CONFIG_AT91SAM9G45) |
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#define AT91_MATRIX_MRCR_RCB2 0x00000004 |
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#define AT91_MATRIX_MRCR_RCB3 0x00000008 |
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#define AT91_MATRIX_MRCR_RCB4 0x00000010 |
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#define AT91_MATRIX_MRCR_RCB5 0x00000020 |
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#define AT91_MATRIX_MRCR_RCB6 0x00000040 |
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#define AT91_MATRIX_MRCR_RCB7 0x00000080 |
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#define AT91_MATRIX_MRCR_RCB8 0x00000100 |
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#endif |
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#if defined(CONFIG_AT91SAM9G45) |
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#define AT91_MATRIX_MRCR_RCB9 0x00000200 |
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#define AT91_MATRIX_MRCR_RCB10 0x00000400 |
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#define AT91_MATRIX_MRCR_RCB11 0x00000800 |
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#endif |
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/* TCM Configuration Register */ |
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#if defined(CONFIG_AT91SAM9G45) |
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/* Size of ITCM enabled memory block */ |
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#define AT91_MATRIX_TCMR_ITCM_0 0x00000000 |
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#define AT91_MATRIX_TCMR_ITCM_32 0x00000040 |
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/* Size of DTCM enabled memory block */ |
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#define AT91_MATRIX_TCMR_DTCM_0 0x00000000 |
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#define AT91_MATRIX_TCMR_DTCM_32 0x00000060 |
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#define AT91_MATRIX_TCMR_DTCM_64 0x00000070 |
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/* Wait state TCM register */ |
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#define AT91_MATRIX_TCMR_TCM_NO_WS 0x00000000 |
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#define AT91_MATRIX_TCMR_TCM_ONE_WS 0x00000800 |
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#endif |
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#if defined(CONFIG_AT91SAM9263) |
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/* Size of ITCM enabled memory block */ |
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#define AT91_MATRIX_TCMR_ITCM_0 0x00000000 |
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#define AT91_MATRIX_TCMR_ITCM_16 0x00000005 |
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#define AT91_MATRIX_TCMR_ITCM_32 0x00000006 |
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/* Size of DTCM enabled memory block */ |
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#define AT91_MATRIX_TCMR_DTCM_0 0x00000000 |
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#define AT91_MATRIX_TCMR_DTCM_16 0x00000050 |
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#define AT91_MATRIX_TCMR_DTCM_32 0x00000060 |
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#endif |
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#if defined(CONFIG_AT91SAM9261) |
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/* Size of ITCM enabled memory block */ |
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#define AT91_MATRIX_TCMR_ITCM_0 0x00000000 |
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#define AT91_MATRIX_TCMR_ITCM_16 0x00000005 |
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#define AT91_MATRIX_TCMR_ITCM_32 0x00000006 |
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#define AT91_MATRIX_TCMR_ITCM_64 0x00000007 |
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/* Size of DTCM enabled memory block */ |
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#define AT91_MATRIX_TCMR_DTCM_0 0x00000000 |
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#define AT91_MATRIX_TCMR_DTCM_16 0x00000050 |
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#define AT91_MATRIX_TCMR_DTCM_32 0x00000060 |
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#define AT91_MATRIX_TCMR_DTCM_64 0x00000070 |
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#endif |
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#if defined(CONFIG_AT91SAM9G45) |
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/* Video Mode Configuration Register */ |
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#define AT91C_MATRIX_VDEC_SEL_OFF 0x00000000 |
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#define AT91C_MATRIX_VDEC_SEL_ON 0x00000001 |
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/* Write Protect Mode Register */ |
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#define AT91_MATRIX_WPMR_WP_WPDIS 0x00000000 |
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#define AT91_MATRIX_WPMR_WP_WPEN 0x00000001 |
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#define AT91_MATRIX_WPMR_WPKEY 0xFFFFFF00 /* Write Protect KEY */ |
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/* Write Protect Status Register */ |
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#define AT91_MATRIX_WPSR_NO_WPV 0x00000000 |
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#define AT91_MATRIX_WPSR_WPV 0x00000001 |
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#define AT91_MATRIX_WPSR_WPVSRC 0x00FFFF00 /* Write Protect Violation Source */ |
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#endif |
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/* USB Pad Pull-Up Control Register */ |
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#if defined(CONFIG_AT91SAM9261) |
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#define AT91_MATRIX_USBPUCR_PUON 0x40000000 |
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#endif |
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#define AT91_MATRIX_PRA_M0(x) ((x & 3) << 0) /* Master 0 Priority Reg. A*/ |
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#define AT91_MATRIX_PRA_M1(x) ((x & 3) << 4) /* Master 1 Priority Reg. A*/ |
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#define AT91_MATRIX_PRA_M2(x) ((x & 3) << 8) /* Master 2 Priority Reg. A*/ |
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#define AT91_MATRIX_PRA_M3(x) ((x & 3) << 12) /* Master 3 Priority Reg. A*/ |
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#define AT91_MATRIX_PRA_M4(x) ((x & 3) << 16) /* Master 4 Priority Reg. A*/ |
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#define AT91_MATRIX_PRA_M5(x) ((x & 3) << 20) /* Master 5 Priority Reg. A*/ |
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#define AT91_MATRIX_PRA_M6(x) ((x & 3) << 24) /* Master 6 Priority Reg. A*/ |
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#define AT91_MATRIX_PRA_M7(x) ((x & 3) << 28) /* Master 7 Priority Reg. A*/ |
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#define AT91_MATRIX_PRB_M8(x) ((x & 3) << 0) /* Master 8 Priority Reg. B) */ |
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#define AT91_MATRIX_PRB_M9(x) ((x & 3) << 4) /* Master 9 Priority Reg. B) */ |
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#define AT91_MATRIX_PRB_M10(x) ((x & 3) << 8) /* Master 10 Priority Reg. B) */ |
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#endif |
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