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ddr: altera: sequencer: Wrap RW_MGR_* macros

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Introduce structure socfpga_sdram_rw_mgr_config to wrap the RW manager
configuration values in board file. Introduce a complementary function,
socfpga_get_sdram_rwmgr_config(), which returns this the structure.
This is another step toward wrapping the nasty QTS generated macros
in board files and reducing the pollution of the namespace.

Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
master
Marek Vasut 9 years ago
parent 04955cf247
commit d718a26b0c
3 changed files with 140 additions and 0 deletions
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  1. 64
      arch/arm/mach-socfpga/include/mach/sdram.h
  2. 72
      board/altera/socfpga/wrap_sdram_config.c
  3. 4
      drivers/ddr/altera/sequencer.c

64
arch/arm/mach-socfpga/include/mach/sdram.h
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@ -16,6 +16,7 @@ const struct socfpga_sdram_config *socfpga_get_sdram_config(void);
void socfpga_get_seq_ac_init(const u32 **init, unsigned int *nelem);
void socfpga_get_seq_inst_init(const u32 **init, unsigned int *nelem);
const struct socfpga_sdram_rw_mgr_config *socfpga_get_sdram_rwmgr_config(void);
#define SDR_CTRLGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x5000)
@ -116,6 +117,69 @@ struct socfpga_sdram_config {
u32 phy_ctrl0;
};
struct socfpga_sdram_rw_mgr_config {
u8 activate_0_and_1;
u8 activate_0_and_1_wait1;
u8 activate_0_and_1_wait2;
u8 activate_1;
u8 clear_dqs_enable;
u8 guaranteed_read;
u8 guaranteed_read_cont;
u8 guaranteed_write;
u8 guaranteed_write_wait0;
u8 guaranteed_write_wait1;
u8 guaranteed_write_wait2;
u8 guaranteed_write_wait3;
u8 idle;
u8 idle_loop1;
u8 idle_loop2;
u8 init_reset_0_cke_0;
u8 init_reset_1_cke_0;
u8 lfsr_wr_rd_bank_0;
u8 lfsr_wr_rd_bank_0_data;
u8 lfsr_wr_rd_bank_0_dqs;
u8 lfsr_wr_rd_bank_0_nop;
u8 lfsr_wr_rd_bank_0_wait;
u8 lfsr_wr_rd_bank_0_wl_1;
u8 lfsr_wr_rd_dm_bank_0;
u8 lfsr_wr_rd_dm_bank_0_data;
u8 lfsr_wr_rd_dm_bank_0_dqs;
u8 lfsr_wr_rd_dm_bank_0_nop;
u8 lfsr_wr_rd_dm_bank_0_wait;
u8 lfsr_wr_rd_dm_bank_0_wl_1;
u8 mrs0_dll_reset;
u8 mrs0_dll_reset_mirr;
u8 mrs0_user;
u8 mrs0_user_mirr;
u8 mrs1;
u8 mrs1_mirr;
u8 mrs2;
u8 mrs2_mirr;
u8 mrs3;
u8 mrs3_mirr;
u8 precharge_all;
u8 read_b2b;
u8 read_b2b_wait1;
u8 read_b2b_wait2;
u8 refresh_all;
u8 rreturn;
u8 sgle_read;
u8 zqcl;
u8 true_mem_data_mask_width;
u8 mem_address_mirroring;
u8 mem_data_mask_width;
u8 mem_data_width;
u8 mem_dq_per_read_dqs;
u8 mem_dq_per_write_dqs;
u8 mem_if_read_dqs_width;
u8 mem_if_write_dqs_width;
u8 mem_number_of_cs_per_dimm;
u8 mem_number_of_ranks;
u8 mem_virtual_groups_per_read_dqs;
u8 mem_virtual_groups_per_write_dqs;
};
#define SDR_CTRLGRP_CTRLCFG_NODMPINS_LSB 23
#define SDR_CTRLGRP_CTRLCFG_NODMPINS_MASK 0x00800000
#define SDR_CTRLGRP_CTRLCFG_DQSTRKEN_LSB 22

72
board/altera/socfpga/wrap_sdram_config.c
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@ -12,6 +12,8 @@
#include "qts/sequencer_auto_ac_init.h"
#include "qts/sequencer_auto_inst_init.h"
#include "qts/sequencer_auto.h"
#include "qts/sequencer_defines.h"
static const struct socfpga_sdram_config sdram_config = {
.ctrl_cfg =
@ -182,6 +184,71 @@ static const struct socfpga_sdram_config sdram_config = {
.phy_ctrl0 = CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0,
};
static const struct socfpga_sdram_rw_mgr_config rw_mgr_config = {
.activate_0_and_1 = RW_MGR_ACTIVATE_0_AND_1,
.activate_0_and_1_wait1 = RW_MGR_ACTIVATE_0_AND_1_WAIT1,
.activate_0_and_1_wait2 = RW_MGR_ACTIVATE_0_AND_1_WAIT2,
.activate_1 = RW_MGR_ACTIVATE_1,
.clear_dqs_enable = RW_MGR_CLEAR_DQS_ENABLE,
.guaranteed_read = RW_MGR_GUARANTEED_READ,
.guaranteed_read_cont = RW_MGR_GUARANTEED_READ_CONT,
.guaranteed_write = RW_MGR_GUARANTEED_WRITE,
.guaranteed_write_wait0 = RW_MGR_GUARANTEED_WRITE_WAIT0,
.guaranteed_write_wait1 = RW_MGR_GUARANTEED_WRITE_WAIT1,
.guaranteed_write_wait2 = RW_MGR_GUARANTEED_WRITE_WAIT2,
.guaranteed_write_wait3 = RW_MGR_GUARANTEED_WRITE_WAIT3,
.idle = RW_MGR_IDLE,
.idle_loop1 = RW_MGR_IDLE_LOOP1,
.idle_loop2 = RW_MGR_IDLE_LOOP2,
.init_reset_0_cke_0 = RW_MGR_INIT_RESET_0_CKE_0,
.init_reset_1_cke_0 = RW_MGR_INIT_RESET_1_CKE_0,
.lfsr_wr_rd_bank_0 = RW_MGR_LFSR_WR_RD_BANK_0,
.lfsr_wr_rd_bank_0_data = RW_MGR_LFSR_WR_RD_BANK_0_DATA,
.lfsr_wr_rd_bank_0_dqs = RW_MGR_LFSR_WR_RD_BANK_0_DQS,
.lfsr_wr_rd_bank_0_nop = RW_MGR_LFSR_WR_RD_BANK_0_NOP,
.lfsr_wr_rd_bank_0_wait = RW_MGR_LFSR_WR_RD_BANK_0_WAIT,
.lfsr_wr_rd_bank_0_wl_1 = RW_MGR_LFSR_WR_RD_BANK_0_WL_1,
.lfsr_wr_rd_dm_bank_0 = RW_MGR_LFSR_WR_RD_DM_BANK_0,
.lfsr_wr_rd_dm_bank_0_data = RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA,
.lfsr_wr_rd_dm_bank_0_dqs = RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS,
.lfsr_wr_rd_dm_bank_0_nop = RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP,
.lfsr_wr_rd_dm_bank_0_wait = RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT,
.lfsr_wr_rd_dm_bank_0_wl_1 = RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1,
.mrs0_dll_reset = RW_MGR_MRS0_DLL_RESET,
.mrs0_dll_reset_mirr = RW_MGR_MRS0_DLL_RESET_MIRR,
.mrs0_user = RW_MGR_MRS0_USER,
.mrs0_user_mirr = RW_MGR_MRS0_USER_MIRR,
.mrs1 = RW_MGR_MRS1,
.mrs1_mirr = RW_MGR_MRS1_MIRR,
.mrs2 = RW_MGR_MRS2,
.mrs2_mirr = RW_MGR_MRS2_MIRR,
.mrs3 = RW_MGR_MRS3,
.mrs3_mirr = RW_MGR_MRS3_MIRR,
.precharge_all = RW_MGR_PRECHARGE_ALL,
.read_b2b = RW_MGR_READ_B2B,
.read_b2b_wait1 = RW_MGR_READ_B2B_WAIT1,
.read_b2b_wait2 = RW_MGR_READ_B2B_WAIT2,
.refresh_all = RW_MGR_REFRESH_ALL,
.rreturn = RW_MGR_RETURN,
.sgle_read = RW_MGR_SGLE_READ,
.zqcl = RW_MGR_ZQCL,
.true_mem_data_mask_width = RW_MGR_TRUE_MEM_DATA_MASK_WIDTH,
.mem_address_mirroring = RW_MGR_MEM_ADDRESS_MIRRORING,
.mem_data_mask_width = RW_MGR_MEM_DATA_MASK_WIDTH,
.mem_data_width = RW_MGR_MEM_DATA_WIDTH,
.mem_dq_per_read_dqs = RW_MGR_MEM_DQ_PER_READ_DQS,
.mem_dq_per_write_dqs = RW_MGR_MEM_DQ_PER_WRITE_DQS,
.mem_if_read_dqs_width = RW_MGR_MEM_IF_READ_DQS_WIDTH,
.mem_if_write_dqs_width = RW_MGR_MEM_IF_WRITE_DQS_WIDTH,
.mem_number_of_cs_per_dimm = RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM,
.mem_number_of_ranks = RW_MGR_MEM_NUMBER_OF_RANKS,
.mem_virtual_groups_per_read_dqs =
RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS,
.mem_virtual_groups_per_write_dqs =
RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS,
};
const struct socfpga_sdram_config *socfpga_get_sdram_config(void)
{
return &sdram_config;
@ -198,3 +265,8 @@ void socfpga_get_seq_inst_init(const u32 **init, unsigned int *nelem)
*init = inst_rom_init;
*nelem = ARRAY_SIZE(inst_rom_init);
}
const struct socfpga_sdram_rw_mgr_config *socfpga_get_sdram_rwmgr_config(void)
{
return &rw_mgr_config;
}

4
drivers/ddr/altera/sequencer.c
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@ -41,6 +41,8 @@ static struct socfpga_data_mgr *data_mgr =
static struct socfpga_sdr_ctrl *sdr_ctrl =
(struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;
const struct socfpga_sdram_rw_mgr_config *rwcfg;
#define DELTA_D 1
/*
@ -3696,6 +3698,8 @@ int sdram_calibration_full(void)
param = &my_param;
gbl = &my_gbl;
rwcfg = socfpga_get_sdram_rwmgr_config();
/* Set the calibration enabled by default */
gbl->phy_debug_mode_flags |= PHY_DEBUG_ENABLE_CAL_RPT;
/*

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