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@ -25,6 +25,7 @@ |
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#include <netdev.h> |
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#include <asm/arch/mx31.h> |
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#include <asm/arch/mx31-regs.h> |
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#include <asm/io.h> |
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#include <nand.h> |
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#include <fsl_pmic.h> |
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#include <mxc_gpio.h> |
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@ -97,6 +98,38 @@ int board_early_init_f (void) |
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mx31_gpio_mux(MUX_CSPI2_SCLK__CSPI2_CLK); |
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mx31_gpio_mux(MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B); |
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/* Setup pins for USB2 Host */ |
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mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_CLK, MUX_CTL_FUNC)); |
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mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_DIR, MUX_CTL_FUNC)); |
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mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_NXT, MUX_CTL_FUNC)); |
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mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_STP, MUX_CTL_FUNC)); |
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mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_DATA0, MUX_CTL_FUNC)); |
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mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_DATA1, MUX_CTL_FUNC)); |
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mx31_gpio_mux(IOMUX_MODE(MUX_CTL_STXD3, MUX_CTL_FUNC)); |
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mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SRXD3, MUX_CTL_FUNC)); |
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mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SCK3, MUX_CTL_FUNC)); |
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mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SFS3, MUX_CTL_FUNC)); |
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mx31_gpio_mux(IOMUX_MODE(MUX_CTL_STXD6, MUX_CTL_FUNC)); |
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mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SRXD6, MUX_CTL_FUNC)); |
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#define H2_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \ |
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PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU) |
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mx31_set_pad(MX31_PIN_USBH2_CLK, H2_PAD_CFG); |
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mx31_set_pad(MX31_PIN_USBH2_DIR, H2_PAD_CFG); |
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mx31_set_pad(MX31_PIN_USBH2_NXT, H2_PAD_CFG); |
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mx31_set_pad(MX31_PIN_USBH2_STP, H2_PAD_CFG); |
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mx31_set_pad(MX31_PIN_USBH2_DATA0, H2_PAD_CFG); /* USBH2_DATA0 */ |
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mx31_set_pad(MX31_PIN_USBH2_DATA1, H2_PAD_CFG); /* USBH2_DATA1 */ |
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mx31_set_pad(MX31_PIN_SRXD6, H2_PAD_CFG); /* USBH2_DATA2 */ |
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mx31_set_pad(MX31_PIN_STXD6, H2_PAD_CFG); /* USBH2_DATA3 */ |
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mx31_set_pad(MX31_PIN_SFS3, H2_PAD_CFG); /* USBH2_DATA4 */ |
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mx31_set_pad(MX31_PIN_SCK3, H2_PAD_CFG); /* USBH2_DATA5 */ |
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mx31_set_pad(MX31_PIN_SRXD3, H2_PAD_CFG); /* USBH2_DATA6 */ |
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mx31_set_pad(MX31_PIN_STXD3, H2_PAD_CFG); /* USBH2_DATA7 */ |
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writel(readl((IOMUXC_BASE + 0x8)) | (1 << 11), IOMUXC_BASE + 0x8); |
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return 0; |
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} |
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