Merge branch 'master' of git://git.denx.de/u-boot-mips

* 'master' of git://git.denx.de/u-boot-mips: MIPS: Jz4740: Add qi_lb60 board support MIPS: Jz4740: Add NAND driver MIPS: Ingenic XBurst Jz4740 processor support
14 years ago · d8fffa057c
parent 0dd78fb943 3c945542da
commit d8fffa057c
20 changed files with 2804 additions and 1 deletions
--- a/4
+++ b/4
@ -928,6 +928,10 @@ Stefan Roese <sr@denx.de>

 	vct_xxx		MIPS32 4Kc

+Xiangfu Liu <xiangfu@openmobilefree.net>
+
+	qi_lb60		MIPS32 (XBurst Jz4740 SoC)
+
 #########################################################################
 # Nios-II Systems:							#
 #									#
--- a/4
+++ b/4
@ -400,7 +400,9 @@ LIST_mips="		\
 ## MIPS Systems		(little endian)
 #########################################################################

-LIST_mips4kc_el=""
+LIST_mips4kc_el="	\
+	qi_lb60		\
+"

 LIST_mips5kc_el=""

--- a/1
+++ b/1
@ -181,6 +181,7 @@ Directory Hierarchy:
  /mips			Files generic to MIPS architecture
    /cpu		CPU specific files
      /mips32		Files specific to MIPS32 CPUs
+      /xburst		Files specific to Ingenic XBurst CPUs
    /lib		Architecture specific library files
  /nios2		Files generic to Altera NIOS2 architecture
    /cpu		CPU specific files
--- a/arch/mips/cpu/xburst/Makefile
+++ b/arch/mips/cpu/xburst/Makefile
@ -0,0 +1,49 @@
+#
+# Copyright (C) 2011 Xiangfu Liu <xiangfu@openmobilefree.net>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(CPU).o
+
+START	= start.o
+SOBJS-y	=
+COBJS-y	= cpu.o timer.o jz_serial.o
+
+COBJS-$(CONFIG_JZ4740) += jz4740.o
+
+SRCS	:= $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
+START	:= $(addprefix $(obj),$(START))
+
+all:	$(obj).depend $(START) $(LIB)
+
+$(LIB):	$(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- a/arch/mips/cpu/xburst/config.mk
+++ b/arch/mips/cpu/xburst/config.mk
@ -0,0 +1,24 @@
+#
+# Copyright (C) 2011 Xiangfu Liu <xiangfu@openmobilefree.net>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+PLATFORM_CPPFLAGS += -march=mips32 -EL
+PLATFORM_LDFLAGS += -EL
--- a/arch/mips/cpu/xburst/cpu.c
+++ b/arch/mips/cpu/xburst/cpu.c
@ -0,0 +1,152 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
+ * (C) Copyright 2011
+ * Xiangfu Liu <xiangfu@openmobilefree.net>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <netdev.h>
+#include <asm/mipsregs.h>
+#include <asm/cacheops.h>
+#include <asm/reboot.h>
+#include <asm/io.h>
+#include <asm/jz4740.h>
+
+#define cache_op(op, addr)		\
+	__asm__ __volatile__(		\
+		".set	push\n"		\
+		".set	noreorder\n"	\
+		".set	mips3\n"	\
+		"cache	%0, %1\n"	\
+		".set	pop\n"		\
+		:			\
+		: "i" (op), "R" (*(unsigned char *)(addr)))
+
+void __attribute__((weak)) _machine_restart(void)
+{
+	struct jz4740_wdt *wdt = (struct jz4740_wdt *)JZ4740_WDT_BASE;
+	struct jz4740_tcu *tcu = (struct jz4740_tcu *)JZ4740_TCU_BASE;
+	u16 tmp;
+
+	/* wdt_select_extalclk() */
+	tmp = readw(&wdt->tcsr);
+	tmp &= ~(WDT_TCSR_EXT_EN | WDT_TCSR_RTC_EN | WDT_TCSR_PCK_EN);
+	tmp |= WDT_TCSR_EXT_EN;
+	writew(tmp, &wdt->tcsr);
+
+	/* wdt_select_clk_div64() */
+	tmp = readw(&wdt->tcsr);
+	tmp &= ~WDT_TCSR_PRESCALE_MASK;
+	tmp |= WDT_TCSR_PRESCALE64,
+	writew(tmp, &wdt->tcsr);
+
+	writew(100, &wdt->tdr); /* wdt_set_data(100) */
+	writew(0, &wdt->tcnt); /* wdt_set_count(0); */
+	writew(TCU_TSSR_WDTSC, &tcu->tscr); /* tcu_start_wdt_clock */
+	writeb(readb(&wdt->tcer) | WDT_TCER_TCEN, &wdt->tcer); /* wdt start */
+
+	while (1)
+		;
+}
+
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	_machine_restart();
+
+	fprintf(stderr, "*** reset failed ***\n");
+	return 0;
+}
+
+void flush_cache(ulong start_addr, ulong size)
+{
+	unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
+	unsigned long addr = start_addr & ~(lsize - 1);
+	unsigned long aend = (start_addr + size - 1) & ~(lsize - 1);
+
+	for (; addr <= aend; addr += lsize) {
+		cache_op(Hit_Writeback_Inv_D, addr);
+		cache_op(Hit_Invalidate_I, addr);
+	}
+}
+
+void flush_dcache_range(ulong start_addr, ulong stop)
+{
+	unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
+	unsigned long addr = start_addr & ~(lsize - 1);
+	unsigned long aend = (stop - 1) & ~(lsize - 1);
+
+	for (; addr <= aend; addr += lsize)
+		cache_op(Hit_Writeback_Inv_D, addr);
+}
+
+void invalidate_dcache_range(ulong start_addr, ulong stop)
+{
+	unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
+	unsigned long addr = start_addr & ~(lsize - 1);
+	unsigned long aend = (stop - 1) & ~(lsize - 1);
+
+	for (; addr <= aend; addr += lsize)
+		cache_op(Hit_Invalidate_D, addr);
+}
+
+void flush_icache_all(void)
+{
+	u32 addr, t = 0;
+
+	__asm__ __volatile__("mtc0 $0, $28"); /* Clear Taglo */
+	__asm__ __volatile__("mtc0 $0, $29"); /* Clear TagHi */
+
+	for (addr = CKSEG0; addr < CKSEG0 + CONFIG_SYS_ICACHE_SIZE;
+	     addr += CONFIG_SYS_CACHELINE_SIZE) {
+		cache_op(Index_Store_Tag_I, addr);
+	}
+
+	/* invalidate btb */
+	__asm__ __volatile__(
+		".set mips32\n\t"
+		"mfc0 %0, $16, 7\n\t"
+		"nop\n\t"
+		"ori %0,2\n\t"
+		"mtc0 %0, $16, 7\n\t"
+		".set mips2\n\t"
+		:
+		: "r" (t));
+}
+
+void flush_dcache_all(void)
+{
+	u32 addr;
+
+	for (addr = CKSEG0; addr < CKSEG0 + CONFIG_SYS_DCACHE_SIZE;
+	     addr += CONFIG_SYS_CACHELINE_SIZE) {
+		cache_op(Index_Writeback_Inv_D, addr);
+	}
+
+	__asm__ __volatile__("sync");
+}
+
+void flush_cache_all(void)
+{
+	flush_dcache_all();
+	flush_icache_all();
+}
--- a/arch/mips/cpu/xburst/jz4740.c
+++ b/arch/mips/cpu/xburst/jz4740.c
@ -0,0 +1,248 @@
+/*
+ * Jz4740 common routines
+ * Copyright (c) 2006 Ingenic Semiconductor, <jlwei@ingenic.cn>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <asm/io.h>
+#include <asm/jz4740.h>
+
+void enable_interrupts(void)
+{
+}
+
+int disable_interrupts(void)
+{
+	return 0;
+}
+
+/*
+ * PLL output clock = EXTAL * NF / (NR * NO)
+ * NF = FD + 2, NR = RD + 2
+ * NO = 1 (if OD = 0), NO = 2 (if OD = 1 or 2), NO = 4 (if OD = 3)
+ */
+void pll_init(void)
+{
+	struct jz4740_cpm *cpm = (struct jz4740_cpm *)JZ4740_CPM_BASE;
+
+	register unsigned int cfcr, plcr1;
+	int n2FR[33] = {
+		0, 0, 1, 2, 3, 0, 4, 0, 5, 0, 0, 0, 6, 0, 0, 0,
+		7, 0, 0, 0, 0, 0, 0, 0, 8, 0, 0, 0, 0, 0, 0, 0,
+		9
+	};
+	int div[5] = {1, 3, 3, 3, 3}; /* divisors of I:S:P:L:M */
+	int nf, pllout2;
+
+	cfcr =	CPM_CPCCR_CLKOEN |
+		CPM_CPCCR_PCS |
+		(n2FR[div[0]] << CPM_CPCCR_CDIV_BIT) |
+		(n2FR[div[1]] << CPM_CPCCR_HDIV_BIT) |
+		(n2FR[div[2]] << CPM_CPCCR_PDIV_BIT) |
+		(n2FR[div[3]] << CPM_CPCCR_MDIV_BIT) |
+		(n2FR[div[4]] << CPM_CPCCR_LDIV_BIT);
+
+	pllout2 = (cfcr & CPM_CPCCR_PCS) ?
+		CONFIG_SYS_CPU_SPEED : (CONFIG_SYS_CPU_SPEED / 2);
+
+	/* Init USB Host clock, pllout2 must be n*48MHz */
+	writel(pllout2 / 48000000 - 1, &cpm->uhccdr);
+
+	nf = CONFIG_SYS_CPU_SPEED * 2 / CONFIG_SYS_EXTAL;
+	plcr1 = ((nf - 2) << CPM_CPPCR_PLLM_BIT) | /* FD */
+		(0 << CPM_CPPCR_PLLN_BIT) |	/* RD=0, NR=2 */
+		(0 << CPM_CPPCR_PLLOD_BIT) |	/* OD=0, NO=1 */
+		(0x20 << CPM_CPPCR_PLLST_BIT) |	/* PLL stable time */
+		CPM_CPPCR_PLLEN;		/* enable PLL */
+
+	/* init PLL */
+	writel(cfcr, &cpm->cpccr);
+	writel(plcr1, &cpm->cppcr);
+}
+
+void sdram_init(void)
+{
+	struct jz4740_emc *emc = (struct jz4740_emc *)JZ4740_EMC_BASE;
+
+	register unsigned int dmcr0, dmcr, sdmode, tmp, cpu_clk, mem_clk, ns;
+
+	unsigned int cas_latency_sdmr[2] = {
+		EMC_SDMR_CAS_2,
+		EMC_SDMR_CAS_3,
+	};
+
+	unsigned int cas_latency_dmcr[2] = {
+		1 << EMC_DMCR_TCL_BIT,	/* CAS latency is 2 */
+		2 << EMC_DMCR_TCL_BIT	/* CAS latency is 3 */
+	};
+
+	int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
+
+	cpu_clk = CONFIG_SYS_CPU_SPEED;
+	mem_clk = cpu_clk * div[__cpm_get_cdiv()] / div[__cpm_get_mdiv()];
+
+	writel(0, &emc->bcr);	/* Disable bus release */
+	writew(0, &emc->rtcsr);	/* Disable clock for counting */
+
+	/* Fault DMCR value for mode register setting*/
+#define SDRAM_ROW0	11
+#define SDRAM_COL0	8
+#define SDRAM_BANK40	0
+
+	dmcr0 = ((SDRAM_ROW0 - 11) << EMC_DMCR_RA_BIT) |
+		((SDRAM_COL0 - 8) << EMC_DMCR_CA_BIT) |
+		(SDRAM_BANK40 << EMC_DMCR_BA_BIT) |
+		(SDRAM_BW16 << EMC_DMCR_BW_BIT) |
+		EMC_DMCR_EPIN |
+		cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)];
+
+	/* Basic DMCR value */
+	dmcr = ((SDRAM_ROW - 11) << EMC_DMCR_RA_BIT) |
+		((SDRAM_COL - 8) << EMC_DMCR_CA_BIT) |
+		(SDRAM_BANK4 << EMC_DMCR_BA_BIT) |
+		(SDRAM_BW16 << EMC_DMCR_BW_BIT) |
+		EMC_DMCR_EPIN |
+		cas_latency_dmcr[((SDRAM_CASL == 3) ? 1 : 0)];
+
+	/* SDRAM timimg */
+	ns = 1000000000 / mem_clk;
+	tmp = SDRAM_TRAS / ns;
+	if (tmp < 4)
+		tmp = 4;
+	if (tmp > 11)
+		tmp = 11;
+	dmcr |= (tmp - 4) << EMC_DMCR_TRAS_BIT;
+	tmp = SDRAM_RCD / ns;
+
+	if (tmp > 3)
+		tmp = 3;
+	dmcr |= tmp << EMC_DMCR_RCD_BIT;
+	tmp = SDRAM_TPC / ns;
+
+	if (tmp > 7)
+		tmp = 7;
+	dmcr |= tmp << EMC_DMCR_TPC_BIT;
+	tmp = SDRAM_TRWL / ns;
+
+	if (tmp > 3)
+		tmp = 3;
+	dmcr |= tmp << EMC_DMCR_TRWL_BIT;
+	tmp = (SDRAM_TRAS + SDRAM_TPC) / ns;
+
+	if (tmp > 14)
+		tmp = 14;
+	dmcr |= ((tmp + 1) >> 1) << EMC_DMCR_TRC_BIT;
+
+	/* SDRAM mode value */
+	sdmode = EMC_SDMR_BT_SEQ |
+		 EMC_SDMR_OM_NORMAL |
+		 EMC_SDMR_BL_4 |
+		 cas_latency_sdmr[((SDRAM_CASL == 3) ? 1 : 0)];
+
+	/* Stage 1. Precharge all banks by writing SDMR with DMCR.MRSET=0 */
+	writel(dmcr, &emc->dmcr);
+	writeb(0, JZ4740_EMC_SDMR0 | sdmode);
+
+	/* Wait for precharge, > 200us */
+	tmp = (cpu_clk / 1000000) * 1000;
+	while (tmp--)
+		;
+
+	/* Stage 2. Enable auto-refresh */
+	writel(dmcr | EMC_DMCR_RFSH, &emc->dmcr);
+
+	tmp = SDRAM_TREF / ns;
+	tmp = tmp / 64 + 1;
+	if (tmp > 0xff)
+		tmp = 0xff;
+	writew(tmp, &emc->rtcor);
+	writew(0, &emc->rtcnt);
+	/* Divisor is 64, CKO/64 */
+	writew(EMC_RTCSR_CKS_64, &emc->rtcsr);
+
+	/* Wait for number of auto-refresh cycles */
+	tmp = (cpu_clk / 1000000) * 1000;
+	while (tmp--)
+		;
+
+	/* Stage 3. Mode Register Set */
+	writel(dmcr0 | EMC_DMCR_RFSH | EMC_DMCR_MRSET, &emc->dmcr);
+	writeb(0, JZ4740_EMC_SDMR0 | sdmode);
+
+	/* Set back to basic DMCR value */
+	writel(dmcr | EMC_DMCR_RFSH | EMC_DMCR_MRSET, &emc->dmcr);
+
+	/* everything is ok now */
+}
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void calc_clocks(void)
+{
+	unsigned int pllout;
+	unsigned int div[10] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
+
+	pllout = __cpm_get_pllout();
+
+	gd->cpu_clk = pllout / div[__cpm_get_cdiv()];
+	gd->sys_clk = pllout / div[__cpm_get_hdiv()];
+	gd->per_clk = pllout / div[__cpm_get_pdiv()];
+	gd->mem_clk = pllout / div[__cpm_get_mdiv()];
+	gd->dev_clk = CONFIG_SYS_EXTAL;
+}
+
+void rtc_init(void)
+{
+	struct jz4740_rtc *rtc = (struct jz4740_rtc *)JZ4740_RTC_BASE;
+
+	while (!(readl(&rtc->rcr) & RTC_RCR_WRDY))
+		;
+	writel(readl(&rtc->rcr) | RTC_RCR_AE, &rtc->rcr); /* enable alarm */
+
+	while (!(readl(&rtc->rcr) & RTC_RCR_WRDY))
+		;
+	writel(0x00007fff, &rtc->rgr); /* type value */
+
+	while (!(readl(&rtc->rcr) & RTC_RCR_WRDY))
+		;
+	writel(0x0000ffe0, &rtc->hwfcr); /* Power on delay 2s */
+
+	while (!(readl(&rtc->rcr) & RTC_RCR_WRDY))
+		;
+	writel(0x00000fe0, &rtc->hrcr); /* reset delay 125ms */
+}
+
+/* U-Boot common routines */
+phys_size_t initdram(int board_type)
+{
+	struct jz4740_emc *emc = (struct jz4740_emc *)JZ4740_EMC_BASE;
+	u32 dmcr;
+	u32 rows, cols, dw, banks;
+	ulong size;
+
+	dmcr = readl(&emc->dmcr);
+	rows = 11 + ((dmcr & EMC_DMCR_RA_MASK) >> EMC_DMCR_RA_BIT);
+	cols = 8 + ((dmcr & EMC_DMCR_CA_MASK) >> EMC_DMCR_CA_BIT);
+	dw = (dmcr & EMC_DMCR_BW) ? 2 : 4;
+	banks = (dmcr & EMC_DMCR_BA) ? 4 : 2;
+
+	size = (1 << (rows + cols)) * dw * banks;
+
+	return size;
+}
--- a/arch/mips/cpu/xburst/jz_serial.c
+++ b/arch/mips/cpu/xburst/jz_serial.c
@ -0,0 +1,114 @@
+/*
+ * Jz4740 UART support
+ * Copyright (c) 2011
+ * Qi Hardware, Xiangfu Liu <xiangfu@sharism.cc>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <asm/io.h>
+#include <asm/jz4740.h>
+
+/*
+ * serial_init - initialize a channel
+ *
+ * This routine initializes the number of data bits, parity
+ * and set the selected baud rate. Interrupts are disabled.
+ * Set the modem control signals if the option is selected.
+ *
+ * RETURNS: N/A
+ */
+struct jz4740_uart *uart = (struct jz4740_uart *)CONFIG_SYS_UART_BASE;
+
+int serial_init(void)
+{
+	/* Disable port interrupts while changing hardware */
+	writeb(0, &uart->dlhr_ier);
+
+	/* Disable UART unit function */
+	writeb(~UART_FCR_UUE, &uart->iir_fcr);
+
+	/* Set both receiver and transmitter in UART mode (not SIR) */
+	writeb(~(SIRCR_RSIRE | SIRCR_TSIRE), &uart->isr);
+
+	/*
+	 * Set databits, stopbits and parity.
+	 * (8-bit data, 1 stopbit, no parity)
+	 */
+	writeb(UART_LCR_WLEN_8 | UART_LCR_STOP_1, &uart->lcr);
+
+	/* Set baud rate */
+	serial_setbrg();
+
+	/* Enable UART unit, enable and clear FIFO */
+	writeb(UART_FCR_UUE | UART_FCR_FE | UART_FCR_TFLS | UART_FCR_RFLS,
+	       &uart->iir_fcr);
+
+	return 0;
+}
+
+void serial_setbrg(void)
+{
+	u32 baud_div, tmp;
+
+	baud_div = CONFIG_SYS_EXTAL / 16 / CONFIG_BAUDRATE;
+
+	tmp = readb(&uart->lcr);
+	tmp |= UART_LCR_DLAB;
+	writeb(tmp, &uart->lcr);
+
+	writeb((baud_div >> 8) & 0xff, &uart->dlhr_ier);
+	writeb(baud_div & 0xff, &uart->rbr_thr_dllr);
+
+	tmp &= ~UART_LCR_DLAB;
+	writeb(tmp, &uart->lcr);
+}
+
+int serial_tstc(void)
+{
+	if (readb(&uart->lsr) & UART_LSR_DR)
+		return 1;
+
+	return 0;
+}
+
+void serial_putc(const char c)
+{
+	if (c == '\n')
+		serial_putc('\r');
+
+	/* Wait for fifo to shift out some bytes */
+	while (!((readb(&uart->lsr) & (UART_LSR_TDRQ | UART_LSR_TEMT)) == 0x60))
+		;
+
+	writeb((u8)c, &uart->rbr_thr_dllr);
+}
+
+int serial_getc(void)
+{
+	while (!serial_tstc())
+		;
+
+	return readb(&uart->rbr_thr_dllr);
+}
+
+void serial_puts(const char *s)
+{
+	while (*s)
+		serial_putc(*s++);
+}
--- a/arch/mips/cpu/xburst/start.S
+++ b/arch/mips/cpu/xburst/start.S
@ -0,0 +1,171 @@
+/*
+ *  Startup Code for MIPS32 XBURST CPU-core
+ *
+ *  Copyright (c) 2010 Xiangfu Liu <xiangfu@sharism.cc>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/regdef.h>
+#include <asm/mipsregs.h>
+#include <asm/addrspace.h>
+#include <asm/cacheops.h>
+
+	.set noreorder
+
+	.globl _start
+	.text
+_start:
+	/* Initialize $gp */
+	bal	1f
+	 nop
+	.word	_gp
+1:
+	lw	gp, 0(ra)
+
+	/* Set up temporary stack */
+	li	sp, CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_INIT_SP_OFFSET
+
+	la	t9, board_init_f
+	jr	t9
+	 nop
+
+/*
+ * void relocate_code (addr_sp, gd, addr_moni)
+ *
+ * This "function" does not return, instead it continues in RAM
+ * after relocating the monitor code.
+ *
+ * a0 = addr_sp
+ * a1 = gd
+ * a2 = destination address
+ */
+	.globl	relocate_code
+	.ent	relocate_code
+relocate_code:
+	move	sp, a0			# set new stack pointer
+
+	li	t0, CONFIG_SYS_MONITOR_BASE
+	la	t3, in_ram
+	lw	t2, -12(t3)		# t2 <-- uboot_end_data
+	move	t1, a2
+
+	/*
+	 * Fix $gp:
+	 *
+	 * New $gp = (Old $gp - CONFIG_SYS_MONITOR_BASE) + Destination Address
+	 */
+	move	t6, gp
+	sub	gp, CONFIG_SYS_MONITOR_BASE
+	add	gp, a2			# gp now adjusted
+	sub	t6, gp, t6		# t6 <-- relocation offset
+
+	/*
+	 * t0 = source address
+	 * t1 = target address
+	 * t2 = source end address
+	 */
+1:
+	lw	t3, 0(t0)
+	sw	t3, 0(t1)
+	addu	t0, 4
+	ble	t0, t2, 1b
+	 addu	t1, 4
+
+	/* If caches were enabled, we would have to flush them here. */
+
+	/* flush d-cache */
+	li	t0, KSEG0
+	addi	t1, t0, CONFIG_SYS_DCACHE_SIZE
+2:
+	cache	Index_Writeback_Inv_D, 0(t0)
+	bne	t0, t1, 2b
+	 addi	t0, CONFIG_SYS_CACHELINE_SIZE
+
+	sync
+
+	/* flush i-cache */
+	li	t0, KSEG0
+	addi	t1, t0, CONFIG_SYS_ICACHE_SIZE
+3:
+	cache	Index_Invalidate_I, 0(t0)
+	bne	t0, t1, 3b
+	 addi	t0, CONFIG_SYS_CACHELINE_SIZE
+
+	/* Invalidate BTB */
+	mfc0	t0, CP0_CONFIG, 7
+	nop
+	ori	t0, 2
+	mtc0	t0, CP0_CONFIG, 7
+	nop
+
+	/* Jump to where we've relocated ourselves */
+	addi	t0, a2, in_ram - _start
+	jr	t0
+	 nop
+
+	.word	_gp
+	.word	_GLOBAL_OFFSET_TABLE_
+	.word	uboot_end_data
+	.word	uboot_end
+	.word	num_got_entries
+
+in_ram:
+	/*
+	 * Now we want to update GOT.
+	 *
+	 * GOT[0] is reserved. GOT[1] is also reserved for the dynamic object
+	 * generated by GNU ld. Skip these reserved entries from relocation.
+	 */
+	lw	t3, -4(t0)		# t3 <-- num_got_entries
+	lw	t4, -16(t0)		# t4 <-- _GLOBAL_OFFSET_TABLE_
+	lw	t5, -20(t0)		# t5 <-- _gp
+	sub	t4, t5			# compute offset
+	add	t4, t4, gp		# t4 now holds relocated _G_O_T_
+	addi	t4, t4, 8		# skipping first two entries
+	li	t2, 2
+1:
+	lw	t1, 0(t4)
+	beqz	t1, 2f
+	 add	t1, t6
+	sw	t1, 0(t4)
+2:
+	addi	t2, 1
+	blt	t2, t3, 1b
+	 addi	t4, 4
+
+	/* Clear BSS */
+	lw	t1, -12(t0)		# t1 <-- uboot_end_data
+	lw	t2, -8(t0)		# t2 <-- uboot_end
+	add	t1, t6			# adjust pointers
+	add	t2, t6
+
+	sub	t1, 4
+1:	addi	t1, 4
+	bltl	t1, t2, 1b
+	 sw	zero, 0(t1)
+
+	move	a0, a1			# a0 <-- gd
+	la	t9, board_init_r
+	jr	t9
+	 move	a1, a2
+
+	.end	relocate_code
--- a/arch/mips/cpu/xburst/timer.c
+++ b/arch/mips/cpu/xburst/timer.c
@ -0,0 +1,162 @@
+/*
+ *  Copyright (c) 2006
+ *  Ingenic Semiconductor, <jlwei@ingenic.cn>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <asm/io.h>
+
+#include <asm/jz4740.h>
+
+#define TIMER_CHAN  0
+#define TIMER_FDATA 0xffff  /* Timer full data value */
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct jz4740_tcu *tcu = (struct jz4740_tcu *)JZ4740_TCU_BASE;
+
+void reset_timer_masked(void)
+{
+	/* reset time */
+	gd->lastinc = readw(&tcu->tcnt0);
+	gd->tbl = 0;
+}
+
+ulong get_timer_masked(void)
+{
+	ulong now = readw(&tcu->tcnt0);
+
+	if (gd->lastinc <= now)
+		gd->tbl += now - gd->lastinc; /* normal mode */
+	else {
+		/* we have an overflow ... */
+		gd->tbl += TIMER_FDATA + now - gd->lastinc;
+	}
+
+	gd->lastinc = now;
+
+	return gd->tbl;
+}
+
+void udelay_masked(unsigned long usec)
+{
+	ulong tmo;
+	ulong endtime;
+	signed long diff;
+
+	/* normalize */
+	if (usec >= 1000) {
+		tmo = usec / 1000;
+		tmo *= CONFIG_SYS_HZ;
+		tmo /= 1000;
+	} else {
+		if (usec > 1) {
+			tmo = usec * CONFIG_SYS_HZ;
+			tmo /= 1000*1000;
+		} else
+			tmo = 1;
+	}
+
+	endtime = get_timer_masked() + tmo;
+
+	do {
+		ulong now = get_timer_masked();
+		diff = endtime - now;
+	} while (diff >= 0);
+}
+
+int timer_init(void)
+{
+	writew(TCU_TCSR_PRESCALE256 | TCU_TCSR_EXT_EN, &tcu->tcsr0);
+
+	writew(0, &tcu->tcnt0);
+	writew(0, &tcu->tdhr0);
+	writew(TIMER_FDATA, &tcu->tdfr0);
+
+	/* mask irqs */
+	writel((1 << TIMER_CHAN) | (1 << (TIMER_CHAN + 16)), &tcu->tmsr);
+	writel(1 << TIMER_CHAN, &tcu->tscr); /* enable timer clock */
+	writeb(1 << TIMER_CHAN, &tcu->tesr); /* start counting up */
+
+	gd->lastinc = 0;
+	gd->tbl = 0;
+
+	return 0;
+}
+
+void reset_timer(void)
+{
+	reset_timer_masked();
+}
+
+ulong get_timer(ulong base)
+{
+	return get_timer_masked() - base;
+}
+
+void set_timer(ulong t)
+{
+	gd->tbl = t;
+}
+
+void __udelay(unsigned long usec)
+{
+	ulong tmo, tmp;
+
+	/* normalize */
+	if (usec >= 1000) {
+		tmo = usec / 1000;
+		tmo *= CONFIG_SYS_HZ;
+		tmo /= 1000;
+	} else {
+		if (usec >= 1) {
+			tmo = usec * CONFIG_SYS_HZ;
+			tmo /= 1000 * 1000;
+		} else
+			tmo = 1;
+	}
+
+	/* check for rollover during this delay */
+	tmp = get_timer(0);
+	if ((tmp + tmo) < tmp)
+		reset_timer_masked();  /* timer would roll over */
+	else
+		tmo += tmp;
+
+	while (get_timer_masked() < tmo)
+		;
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On MIPS it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+	return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On MIPS it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+	return CONFIG_SYS_HZ;
+}
--- a/arch/mips/include/asm/global_data.h
+++ b/arch/mips/include/asm/global_data.h
@ -39,6 +39,17 @@
 typedef	struct	global_data {
 	bd_t		*bd;
 	unsigned long	flags;
+#ifdef CONFIG_JZSOC
+	/* There are other clocks in the jz4740 */
+	unsigned long	cpu_clk;	/* CPU core clock */
+	unsigned long	sys_clk;	/* System bus clock */
+	unsigned long	per_clk;	/* Peripheral bus clock */
+	unsigned long	mem_clk;	/* Memory bus clock */
+	unsigned long	dev_clk;	/* Device clock */
+	/* "static data" needed by most of timer.c */
+	unsigned long	tbl;
+	unsigned long	lastinc;
+#endif
 	unsigned long	baudrate;
 	unsigned long	have_console;	/* serial_init() was called */
 #ifdef CONFIG_PRE_CONSOLE_BUFFER
--- a/arch/mips/include/asm/jz4740.h
+++ b/arch/mips/include/asm/jz4740.h
--- a/board/qi/qi_lb60/Makefile
+++ b/board/qi/qi_lb60/Makefile
@ -0,0 +1,45 @@
+#
+# (C) Copyright 2006
+# Ingenic Semiconductor, <jlwei@ingenic.cn>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= $(BOARD).o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- a/board/qi/qi_lb60/config.mk
+++ b/board/qi/qi_lb60/config.mk
@ -0,0 +1,31 @@
+#
+# (C) Copyright 2006 Qi Hardware, Inc.
+# Author: Xiangfu Liu <xiangfu.z@gmail.com>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# Qi Hardware, Inc. Ben NanoNote (QI_LB60)
+#
+
+ifndef TEXT_BASE
+# ROM version
+# TEXT_BASE = 0x88000000
+
+# RAM version
+TEXT_BASE = 0x80100000
+endif
--- a/board/qi/qi_lb60/qi_lb60.c
+++ b/board/qi/qi_lb60/qi_lb60.c
@ -0,0 +1,104 @@
+/*
+ * Authors: Xiangfu Liu <xiangfu@sharism.cc>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 3 of the License, or (at your option) any later version.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/jz4740.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void gpio_init(void)
+{
+	unsigned int i;
+
+	/* Initialize NAND Flash Pins */
+	__gpio_as_nand();
+
+	/* Initialize SDRAM pins */
+	__gpio_as_sdram_16bit_4720();
+
+	/* Initialize LCD pins */
+	__gpio_as_lcd_18bit();
+
+	/* Initialize MSC pins */
+	__gpio_as_msc();
+
+	/* Initialize Other pins */
+	for (i = 0; i < 7; i++) {
+		__gpio_as_input(GPIO_KEYIN_BASE + i);
+		__gpio_enable_pull(GPIO_KEYIN_BASE + i);
+	}
+
+	for (i = 0; i < 8; i++) {
+		__gpio_as_output(GPIO_KEYOUT_BASE + i);
+		__gpio_clear_pin(GPIO_KEYOUT_BASE + i);
+	}
+
+	__gpio_as_input(GPIO_KEYIN_8);
+	__gpio_enable_pull(GPIO_KEYIN_8);
+
+	/* enable the TP4, TP5 as UART0 */
+	__gpio_jtag_to_uart0();
+
+	__gpio_as_output(GPIO_AUDIO_POP);
+	__gpio_set_pin(GPIO_AUDIO_POP);
+
+	__gpio_as_output(GPIO_LCD_CS);
+	__gpio_clear_pin(GPIO_LCD_CS);
+
+	__gpio_as_output(GPIO_AMP_EN);
+	__gpio_clear_pin(GPIO_AMP_EN);
+
+	__gpio_as_output(GPIO_SDPW_EN);
+	__gpio_disable_pull(GPIO_SDPW_EN);
+	__gpio_clear_pin(GPIO_SDPW_EN);
+
+	__gpio_as_input(GPIO_SD_DETECT);
+	__gpio_disable_pull(GPIO_SD_DETECT);
+
+	__gpio_as_input(GPIO_USB_DETECT);
+	__gpio_enable_pull(GPIO_USB_DETECT);
+}
+
+static void cpm_init(void)
+{
+	struct jz4740_cpm *cpm = (struct jz4740_cpm *)JZ4740_CPM_BASE;
+	uint32_t reg = readw(&cpm->clkgr);
+
+	reg |=	CPM_CLKGR_IPU |
+		CPM_CLKGR_CIM |
+		CPM_CLKGR_I2C |
+		CPM_CLKGR_SSI |
+		CPM_CLKGR_UART1 |
+		CPM_CLKGR_SADC |
+		CPM_CLKGR_UHC |
+		CPM_CLKGR_UDC |
+		CPM_CLKGR_AIC1;
+
+	writew(reg, &cpm->clkgr);
+}
+
+int board_early_init_f(void)
+{
+	gpio_init();
+	cpm_init();
+	calc_clocks();	/* calc the clocks */
+	rtc_init();	/* init rtc on any reset */
+
+	return 0;
+}
+
+/* U-Boot common routines */
+int checkboard(void)
+{
+	printf("Board: Qi LB60 (Ingenic XBurst Jz4740 SoC, Speed %ld MHz)\n",
+	       gd->cpu_clk / 1000000);
+
+	return 0;
+}
--- a/board/qi/qi_lb60/u-boot.lds
+++ b/board/qi/qi_lb60/u-boot.lds
@ -0,0 +1,61 @@
+/*
+ * (C) Copyright 2006
+ * Ingenic Semiconductor, <jlwei@ingenic.cn>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-tradlittlemips", "elf32-tradlittlemips", "elf32-tradlittlemips")
+
+OUTPUT_ARCH(mips)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text :
+	{
+	  *(.text*)
+	}
+
+	. = ALIGN(4);
+	.rodata  : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+	. = ALIGN(4);
+	.data  : { *(.data*) }
+
+	. = .;
+	_gp = ALIGN(16) + 0x7ff0;
+
+	__got_start = .;
+	.got  : { *(.got) }
+	__got_end = .;
+
+	.sdata  : { *(.sdata*) }
+
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	uboot_end_data = .;
+	num_got_entries = (__got_end - __got_start) >> 2;
+
+	. = ALIGN(4);
+	.sbss  : { *(.sbss*) }
+	.bss  : { *(.bss*) . = ALIGN(4); }
+	uboot_end = .;
+}
--- a/boards.cfg
+++ b/boards.cfg
@ -302,6 +302,7 @@ vct_platinumavc              mips        mips32      vct                 microna
 vct_platinumavc_small        mips        mips32      vct                 micronas       -           vct:VCT_PLATINUMAVC,VCT_SMALL_IMAGE
 vct_platinumavc_onenand      mips        mips32      vct                 micronas       -           vct:VCT_PLATINUMAVC,VCT_ONENAND
 vct_platinumavc_onenand_small mips       mips32      vct                 micronas       -           vct:VCT_PLATINUMAVC,VCT_ONENAND,VCT_SMALL_IMAGE
+qi_lb60                      mips        xburst      qi_lb60             qi
 nios2-generic                nios2       nios2       nios2-generic       altera
 PCI5441                      nios2       nios2       pci5441             psyent
 PK1C20                       nios2       nios2       pk1c20              psyent
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@ -45,6 +45,7 @@ COBJS-$(CONFIG_NAND_DAVINCI) += davinci_nand.o
 COBJS-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_nand.o
 COBJS-$(CONFIG_NAND_FSL_IFC) += fsl_ifc_nand.o
 COBJS-$(CONFIG_NAND_FSL_UPM) += fsl_upm.o
+COBJS-$(CONFIG_NAND_JZ4740) += jz4740_nand.o
 COBJS-$(CONFIG_NAND_KB9202) += kb9202_nand.o
 COBJS-$(CONFIG_NAND_KIRKWOOD) += kirkwood_nand.o
 COBJS-$(CONFIG_NAND_KMETER1) += kmeter1_nand.o
--- a/drivers/mtd/nand/jz4740_nand.c
+++ b/drivers/mtd/nand/jz4740_nand.c
@ -0,0 +1,261 @@
+/*
+ * Platform independend driver for JZ4740.
+ *
+ * Copyright (c) 2007 Ingenic Semiconductor Inc.
+ * Author: <jlwei@ingenic.cn>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+#include <common.h>
+
+#include <nand.h>
+#include <asm/io.h>
+#include <asm/jz4740.h>
+
+#define JZ_NAND_DATA_ADDR ((void __iomem *)0xB8000000)
+#define JZ_NAND_CMD_ADDR (JZ_NAND_DATA_ADDR + 0x8000)
+#define JZ_NAND_ADDR_ADDR (JZ_NAND_DATA_ADDR + 0x10000)
+
+#define BIT(x) (1 << (x))
+#define JZ_NAND_ECC_CTRL_ENCODING	BIT(3)
+#define JZ_NAND_ECC_CTRL_RS		BIT(2)
+#define JZ_NAND_ECC_CTRL_RESET		BIT(1)
+#define JZ_NAND_ECC_CTRL_ENABLE		BIT(0)
+
+#define EMC_SMCR1_OPT_NAND	0x094c4400
+/* Optimize the timing of nand */
+
+static struct jz4740_emc * emc = (struct jz4740_emc *)JZ4740_EMC_BASE;
+
+static struct nand_ecclayout qi_lb60_ecclayout_2gb = {
+	.eccbytes = 72,
+	.eccpos = {
+		12, 13, 14, 15, 16, 17, 18, 19,
+		20, 21, 22, 23, 24, 25, 26, 27,
+		28, 29, 30, 31, 32, 33, 34, 35,
+		36, 37, 38, 39, 40, 41, 42, 43,
+		44, 45, 46, 47, 48, 49, 50, 51,
+		52, 53, 54, 55, 56, 57, 58, 59,
+		60, 61, 62, 63, 64, 65, 66, 67,
+		68, 69, 70, 71, 72, 73, 74, 75,
+		76, 77, 78, 79, 80, 81, 82, 83 },
+	.oobfree = {
+		{.offset = 2,
+		 .length = 10 },
+		{.offset = 84,
+		 .length = 44 } }
+};
+
+static int is_reading;
+
+static void jz_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
+{
+	struct nand_chip *this = mtd->priv;
+	uint32_t reg;
+
+	if (ctrl & NAND_CTRL_CHANGE) {
+		if (ctrl & NAND_ALE)
+			this->IO_ADDR_W = JZ_NAND_ADDR_ADDR;
+		else if (ctrl & NAND_CLE)
+			this->IO_ADDR_W = JZ_NAND_CMD_ADDR;
+		else
+			this->IO_ADDR_W = JZ_NAND_DATA_ADDR;
+
+		reg = readl(&emc->nfcsr);
+		if (ctrl & NAND_NCE)
+			reg |= EMC_NFCSR_NFCE1;
+		else
+			reg &= ~EMC_NFCSR_NFCE1;
+		writel(reg, &emc->nfcsr);
+	}
+
+	if (cmd != NAND_CMD_NONE)
+		writeb(cmd, this->IO_ADDR_W);
+}
+
+static int jz_nand_device_ready(struct mtd_info *mtd)
+{
+	return (readl(GPIO_PXPIN(2)) & 0x40000000) ? 1 : 0;
+}
+
+void board_nand_select_device(struct nand_chip *nand, int chip)
+{
+	/*
+	 * Don't use "chip" to address the NAND device,
+	 * generate the cs from the address where it is encoded.
+	 */
+}
+
+static int jz_nand_rs_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
+				u_char *ecc_code)
+{
+	uint32_t status;
+	int i;
+
+	if (is_reading)
+		return 0;
+
+	do {
+		status = readl(&emc->nfints);
+	} while (!(status & EMC_NFINTS_ENCF));
+
+	/* disable ecc */
+	writel(readl(&emc->nfecr) & ~EMC_NFECR_ECCE, &emc->nfecr);
+
+	for (i = 0; i < 9; i++)
+		ecc_code[i] = readb(&emc->nfpar[i]);
+
+	return 0;
+}
+
+static void jz_nand_hwctl(struct mtd_info *mtd, int mode)
+{
+	uint32_t reg;
+
+	writel(0, &emc->nfints);
+	reg = readl(&emc->nfecr);
+	reg |= JZ_NAND_ECC_CTRL_RESET;
+	reg |= JZ_NAND_ECC_CTRL_ENABLE;
+	reg |= JZ_NAND_ECC_CTRL_RS;
+
+	switch (mode) {
+	case NAND_ECC_READ:
+		reg &= ~JZ_NAND_ECC_CTRL_ENCODING;
+		is_reading = 1;
+		break;
+	case NAND_ECC_WRITE:
+		reg |= JZ_NAND_ECC_CTRL_ENCODING;
+		is_reading = 0;
+		break;
+	default:
+		break;
+	}
+
+	writel(reg, &emc->nfecr);
+}
+
+/* Correct 1~9-bit errors in 512-bytes data */
+static void jz_rs_correct(unsigned char *dat, int idx, int mask)
+{
+	int i;
+
+	idx--;
+
+	i = idx + (idx >> 3);
+	if (i >= 512)
+		return;
+
+	mask <<= (idx & 0x7);
+
+	dat[i] ^= mask & 0xff;
+	if (i < 511)
+		dat[i + 1] ^= (mask >> 8) & 0xff;
+}
+
+static int jz_nand_rs_correct_data(struct mtd_info *mtd, u_char *dat,
+				   u_char *read_ecc, u_char *calc_ecc)
+{
+	int k;
+	uint32_t errcnt, index, mask, status;
+
+	/* Set PAR values */
+	const uint8_t all_ff_ecc[] = {
+		0xcd, 0x9d, 0x90, 0x58, 0xf4, 0x8b, 0xff, 0xb7, 0x6f };
+
+	if (read_ecc[0] == 0xff && read_ecc[1] == 0xff &&
+	    read_ecc[2] == 0xff && read_ecc[3] == 0xff &&
+	    read_ecc[4] == 0xff && read_ecc[5] == 0xff &&
+	    read_ecc[6] == 0xff && read_ecc[7] == 0xff &&
+	    read_ecc[8] == 0xff) {
+		for (k = 0; k < 9; k++)
+			writeb(all_ff_ecc[k], &emc->nfpar[k]);
+	} else {
+		for (k = 0; k < 9; k++)
+			writeb(read_ecc[k], &emc->nfpar[k]);
+	}
+	/* Set PRDY */
+	writel(readl(&emc->nfecr) | EMC_NFECR_PRDY, &emc->nfecr);
+
+	/* Wait for completion */
+	do {
+		status = readl(&emc->nfints);
+	} while (!(status & EMC_NFINTS_DECF));
+
+	/* disable ecc */
+	writel(readl(&emc->nfecr) & ~EMC_NFECR_ECCE, &emc->nfecr);
+
+	/* Check decoding */
+	if (!(status & EMC_NFINTS_ERR))
+		return 0;
+
+	if (status & EMC_NFINTS_UNCOR) {
+		printf("uncorrectable ecc\n");
+		return -1;
+	}
+
+	errcnt = (status & EMC_NFINTS_ERRCNT_MASK) >> EMC_NFINTS_ERRCNT_BIT;
+
+	switch (errcnt) {
+	case 4:
+		index = (readl(&emc->nferr[3]) & EMC_NFERR_INDEX_MASK) >>
+			EMC_NFERR_INDEX_BIT;
+		mask = (readl(&emc->nferr[3]) & EMC_NFERR_MASK_MASK) >>
+			EMC_NFERR_MASK_BIT;
+		jz_rs_correct(dat, index, mask);
+	case 3:
+		index = (readl(&emc->nferr[2]) & EMC_NFERR_INDEX_MASK) >>
+			EMC_NFERR_INDEX_BIT;
+		mask = (readl(&emc->nferr[2]) & EMC_NFERR_MASK_MASK) >>
+			EMC_NFERR_MASK_BIT;
+		jz_rs_correct(dat, index, mask);
+	case 2:
+		index = (readl(&emc->nferr[1]) & EMC_NFERR_INDEX_MASK) >>
+			EMC_NFERR_INDEX_BIT;
+		mask = (readl(&emc->nferr[1]) & EMC_NFERR_MASK_MASK) >>
+			EMC_NFERR_MASK_BIT;
+		jz_rs_correct(dat, index, mask);
+	case 1:
+		index = (readl(&emc->nferr[0]) & EMC_NFERR_INDEX_MASK) >>
+			EMC_NFERR_INDEX_BIT;
+		mask = (readl(&emc->nferr[0]) & EMC_NFERR_MASK_MASK) >>
+			EMC_NFERR_MASK_BIT;
+		jz_rs_correct(dat, index, mask);
+	default:
+		break;
+	}
+
+	return errcnt;
+}
+
+/*
+ * Main initialization routine
+ */
+int board_nand_init(struct nand_chip *nand)
+{
+	uint32_t reg;
+
+	reg = readl(&emc->nfcsr);
+	reg |= EMC_NFCSR_NFE1;	/* EMC setup, Set NFE bit */
+	writel(reg, &emc->nfcsr);
+
+	writel(EMC_SMCR1_OPT_NAND, &emc->smcr[1]);
+
+	nand->IO_ADDR_R		= JZ_NAND_DATA_ADDR;
+	nand->IO_ADDR_W		= JZ_NAND_DATA_ADDR;
+	nand->cmd_ctrl		= jz_nand_cmd_ctrl;
+	nand->dev_ready		= jz_nand_device_ready;
+	nand->ecc.hwctl		= jz_nand_hwctl;
+	nand->ecc.correct	= jz_nand_rs_correct_data;
+	nand->ecc.calculate	= jz_nand_rs_calculate_ecc;
+	nand->ecc.mode		= NAND_ECC_HW_OOB_FIRST;
+	nand->ecc.size		= CONFIG_SYS_NAND_ECCSIZE;
+	nand->ecc.bytes		= CONFIG_SYS_NAND_ECCBYTES;
+	nand->ecc.layout	= &qi_lb60_ecclayout_2gb;
+	nand->chip_delay	= 50;
+	nand->options		= NAND_USE_FLASH_BBT;
+
+	return 0;
+}
--- a/include/configs/qi_lb60.h
+++ b/include/configs/qi_lb60.h
@ -0,0 +1,211 @@
+/*
+ * Authors: Xiangfu Liu <xiangfu.z@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 3 of the License, or (at your option) any later version.
+ */
+
+#ifndef __CONFIG_QI_LB60_H
+#define __CONFIG_QI_LB60_H
+
+#define CONFIG_MIPS32		/* MIPS32 CPU core */
+#define CONFIG_JZSOC		/* Jz SoC */
+#define CONFIG_JZ4740		/* Jz4740 SoC */
+#define CONFIG_NAND_JZ4740
+
+#define CONFIG_SYS_CPU_SPEED	336000000	/* CPU clock: 336 MHz */
+#define CONFIG_SYS_EXTAL	12000000	/* EXTAL freq: 12 MHz */
+#define CONFIG_SYS_HZ		(CONFIG_SYS_EXTAL / 256) /* incrementer freq */
+#define CONFIG_SYS_MIPS_TIMER_FREQ	CONFIG_SYS_CPU_SPEED
+
+#define CONFIG_SYS_UART_BASE	JZ4740_UART0_BASE /* Base of the UART channel */
+#define CONFIG_BAUDRATE		57600
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_SYS_FLASH_BASE	0 /* init flash_base as 0 */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAUL)
+#define CONFIG_BOOTDELAY	0
+#define CONFIG_BOOTARGS		"mem=32M console=tty0 console=ttyS0,57600n8 ubi.mtd=2 rootfstype=ubifs root=ubi0:rootfs rw rootwait"
+#define CONFIG_BOOTCOMMAND	"nand read 0x80600000 0x400000 0x200000;bootm"
+
+/*
+ * Command line configuration.
+ */
+#define CONFIG_CMD_BOOTD	/* bootd			*/
+#define CONFIG_CMD_CONSOLE	/* coninfo			*/
+#define CONFIG_CMD_ECHO		/* echo arguments		*/
+
+#define CONFIG_CMD_LOADB	/* loadb			*/
+#define CONFIG_CMD_LOADS	/* loads			*/
+#define CONFIG_CMD_MEMORY	/* md mm nm mw cp cmp crc base loop mtest */
+#define CONFIG_CMD_MISC		/* Misc functions like sleep etc*/
+#define CONFIG_CMD_RUN		/* run command in env variable	*/
+#define CONFIG_CMD_SAVEENV	/* saveenv			*/
+#define CONFIG_CMD_SETGETDCR	/* DCR support on 4xx		*/
+#define CONFIG_CMD_SOURCE	/* "source" command support	*/
+#define CONFIG_CMD_NAND
+
+/*
+ * Serial download configuration
+ */
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_MAXARGS 16
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_PROMPT "NanoNote# "
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+
+#define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)
+#define CONFIG_SYS_BOOTPARAMS_LEN	(128 * 1024)
+
+#define CONFIG_SYS_SDRAM_BASE		0x80000000	/* Cached addr */
+#define CONFIG_SYS_INIT_SP_OFFSET	0x400000
+#define CONFIG_SYS_LOAD_ADDR		0x80600000
+#define CONFIG_SYS_MEMTEST_START	0x80100000
+#define CONFIG_SYS_MEMTEST_END		0x80800000
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_IS_IN_NAND		/* use NAND for environment vars */
+
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+/*
+ * if board nand flash is 1GB, set to 1
+ * if board nand flash is 2GB, set to 2
+ * for change the PAGE_SIZE and BLOCK_SIZE
+ * will delete when there is no 1GB flash
+ */
+#define NANONOTE_NAND_SIZE	2
+
+#define CONFIG_SYS_NAND_PAGE_SIZE	(2048 * NANONOTE_NAND_SIZE)
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(256 * NANONOTE_NAND_SIZE << 10)
+/* nand bad block was marked at this page in a block, start from 0 */
+#define CONFIG_SYS_NAND_BADBLOCK_PAGE	127
+#define CONFIG_SYS_NAND_PAGE_COUNT	128
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	0
+/* ECC offset position in oob area, default value is 6 if it isn't defined */
+#define CONFIG_SYS_NAND_ECC_POS		(6 * NANONOTE_NAND_SIZE)
+#define CONFIG_SYS_NAND_ECCSIZE		512
+#define CONFIG_SYS_NAND_ECCBYTES	9
+#define CONFIG_SYS_NAND_ECCSTEPS	\
+	(CONFIG_SYS_NAND_PAGE_SIZE / CONFIG_SYS_NAND_ECCSIZE)
+#define CONFIG_SYS_NAND_ECCTOTAL	\
+	(CONFIG_SYS_NAND_ECCBYTES * CONFIG_SYS_NAND_ECCSTEPS)
+#define CONFIG_SYS_NAND_ECCPOS		\
+		{12, 13, 14, 15, 16, 17, 18, 19,\
+		20, 21, 22, 23, 24, 25, 26, 27, \
+		28, 29, 30, 31, 32, 33, 34, 35, \
+		36, 37, 38, 39, 40, 41, 42, 43, \
+		44, 45, 46, 47, 48, 49, 50, 51, \
+		52, 53, 54, 55, 56, 57, 58, 59, \
+		60, 61, 62, 63, 64, 65, 66, 67, \
+		68, 69, 70, 71, 72, 73, 74, 75, \
+		76, 77, 78, 79, 80, 81, 82, 83}
+
+#define CONFIG_SYS_NAND_OOBSIZE		128
+#define CONFIG_SYS_NAND_BASE		0xB8000000
+#define CONFIG_SYS_ONENAND_BASE		CONFIG_SYS_NAND_BASE
+#define NAND_MAX_CHIPS			1
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_SELECT_DEVICE	1 /* nand driver supports mutipl.*/
+#define CONFIG_NAND_SPL_TEXT_BASE	0x80000000
+
+/*
+ * IPL (Initial Program Loader, integrated inside CPU)
+ * Will load first 8k from NAND (SPL) into cache and execute it from there.
+ *
+ * SPL (Secondary Program Loader)
+ * Will load special U-Boot version (NUB) from NAND and execute it. This SPL
+ * has to fit into 8kByte. It sets up the CPU and configures the SDRAM
+ * controller and the NAND controller so that the special U-Boot image can be
+ * loaded from NAND to SDRAM.
+ *
+ * NUB (NAND U-Boot)
+ * This NAND U-Boot (NUB) is a special U-Boot version which can be started
+ * from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
+ *
+ */
+#define CONFIG_SYS_NAND_U_BOOT_DST	0x80100000 /* Load NUB to this addr */
+#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_NAND_U_BOOT_DST
+/* Start NUB from this addr*/
+
+/*
+ * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
+ */
+#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) /* Offset to RAM U-Boot image */
+#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) /* Size of RAM U-Boot image */
+
+#define CONFIG_ENV_SIZE		(4 << 10)
+#define CONFIG_ENV_OFFSET	\
+	(CONFIG_SYS_NAND_BLOCK_SIZE + CONFIG_SYS_NAND_U_BOOT_SIZE)
+#define CONFIG_ENV_OFFSET_REDUND \
+	(CONFIG_ENV_OFFSET  + CONFIG_SYS_NAND_BLOCK_SIZE)
+
+#define CONFIG_SYS_TEXT_BASE	0x80100000
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
+
+/*
+ * SDRAM Info.
+ */
+#define CONFIG_NR_DRAM_BANKS	1
+
+/*
+ * Cache Configuration
+ */
+#define CONFIG_SYS_DCACHE_SIZE	16384
+#define CONFIG_SYS_ICACHE_SIZE	16384
+#define CONFIG_SYS_CACHELINE_SIZE	32
+
+/*
+ * GPIO definition
+ */
+#define GPIO_LCD_CS	(2 * 32 + 21)
+#define GPIO_AMP_EN	(3 * 32 + 4)
+
+#define GPIO_SDPW_EN	(3 * 32 + 2)
+#define GPIO_SD_DETECT	(3 * 32 + 0)
+
+#define GPIO_BUZZ_PWM	(3 * 32 + 27)
+#define GPIO_USB_DETECT	(3 * 32 + 28)
+
+#define GPIO_AUDIO_POP	(1 * 32 + 29)
+#define GPIO_COB_TEST	(1 * 32 + 30)
+
+#define GPIO_KEYOUT_BASE	(2 * 32 + 10)
+#define GPIO_KEYIN_BASE	(3 * 32 + 18)
+#define GPIO_KEYIN_8	(3 * 32 + 26)
+
+#define GPIO_SD_CD_N	GPIO_SD_DETECT		/* SD Card insert detect */
+#define GPIO_SD_VCC_EN_N	GPIO_SDPW_EN	/* SD Card Power Enable */
+
+#define SPEN	GPIO_LCD_CS	/* LCDCS :Serial command enable      */
+#define SPDA	(2 * 32 + 22)	/* LCDSCL:Serial command clock input */
+#define SPCK	(2 * 32 + 23)	/* LCDSDA:Serial command data input  */
+
+/* SDRAM paramters */
+#define SDRAM_BW16		1	/* Data bus width: 0-32bit, 1-16bit */
+#define SDRAM_BANK4		1	/* Banks each chip: 0-2bank, 1-4bank */
+#define SDRAM_ROW		13	/* Row address: 11 to 13 */
+#define SDRAM_COL		9	/* Column address: 8 to 12 */
+#define SDRAM_CASL		2	/* CAS latency: 2 or 3 */
+
+/* SDRAM Timings, unit: ns */
+#define SDRAM_TRAS		45	/* RAS# Active Time */
+#define SDRAM_RCD		20	/* RAS# to CAS# Delay */
+#define SDRAM_TPC		20	/* RAS# Precharge Time */
+#define SDRAM_TRWL		7	/* Write Latency Time */
+#define SDRAM_TREF		15625	/* Refresh period: 8192 cycles/64ms */
+
+#endif