Mike Frysinger
17 years ago
parent
76d21803dd
commit
d9a5d113b9
@ -0,0 +1 @@ |
||||
/u-boot.lds |
||||
@ -0,0 +1,58 @@ |
||||
#
|
||||
# U-boot - Makefile
|
||||
#
|
||||
# Copyright (c) 2005-2008 Analog Device Inc.
|
||||
#
|
||||
# (C) Copyright 2000-2006
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk |
||||
|
||||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
COBJS-y := $(BOARD).o
|
||||
COBJS-$(CONFIG_VIDEO) += video.o
|
||||
|
||||
SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS-y))
|
||||
SOBJS := $(addprefix $(obj),$(SOBJS-y))
|
||||
|
||||
$(LIB): $(obj).depend $(OBJS) $(SOBJS) $(obj)u-boot.lds |
||||
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
|
||||
|
||||
$(obj)u-boot.lds: u-boot.lds.S |
||||
$(CPP) $(CPPFLAGS) -D__ASSEMBLY__ -P $^ > $@
|
||||
|
||||
clean: |
||||
rm -f $(SOBJS) $(OBJS)
|
||||
|
||||
distclean: clean |
||||
rm -f $(LIB) core *.bak $(obj).depend
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk |
||||
|
||||
sinclude $(obj).depend |
||||
|
||||
#########################################################################
|
||||
@ -0,0 +1,77 @@ |
||||
/*
|
||||
* U-boot - main board file |
||||
* |
||||
* Copyright (c) 2005-2009 Analog Devices Inc. |
||||
* |
||||
* Licensed under the GPL-2 or later. |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <config.h> |
||||
#include <command.h> |
||||
#include <net.h> |
||||
#include <netdev.h> |
||||
#include <asm/blackfin.h> |
||||
#include <asm/net.h> |
||||
#include <asm/mach-common/bits/otp.h> |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
int checkboard(void) |
||||
{ |
||||
printf("Board: ADI BF527 EZ-Kit board\n"); |
||||
printf(" Support: http://blackfin.uclinux.org/\n"); |
||||
return 0; |
||||
} |
||||
|
||||
phys_size_t initdram(int board_type) |
||||
{ |
||||
gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; |
||||
gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE; |
||||
return gd->bd->bi_memsize; |
||||
} |
||||
|
||||
#ifdef CONFIG_BFIN_MAC |
||||
static void board_init_enetaddr(uchar *mac_addr) |
||||
{ |
||||
bool valid_mac = false; |
||||
|
||||
/* the MAC is stored in OTP memory page 0xDF */ |
||||
uint32_t ret; |
||||
uint64_t otp_mac; |
||||
|
||||
ret = bfrom_OtpRead(0xDF, OTP_LOWER_HALF, &otp_mac); |
||||
if (!(ret & OTP_MASTER_ERROR)) { |
||||
uchar *otp_mac_p = (uchar *)&otp_mac; |
||||
|
||||
for (ret = 0; ret < 6; ++ret) |
||||
mac_addr[ret] = otp_mac_p[5 - ret]; |
||||
|
||||
if (is_valid_ether_addr(mac_addr)) |
||||
valid_mac = true; |
||||
} |
||||
|
||||
if (!valid_mac) { |
||||
puts("Warning: Generating 'random' MAC address\n"); |
||||
bfin_gen_rand_mac(mac_addr); |
||||
} |
||||
|
||||
eth_setenv_enetaddr("ethaddr", mac_addr); |
||||
} |
||||
|
||||
int board_eth_init(bd_t *bis) |
||||
{ |
||||
return bfin_EMAC_initialize(bis); |
||||
} |
||||
#endif |
||||
|
||||
int misc_init_r(void) |
||||
{ |
||||
#ifdef CONFIG_BFIN_MAC |
||||
uchar enetaddr[6]; |
||||
if (!eth_getenv_enetaddr("ethaddr", enetaddr)) |
||||
board_init_enetaddr(enetaddr); |
||||
#endif |
||||
|
||||
return 0; |
||||
} |
||||
@ -0,0 +1,32 @@ |
||||
#
|
||||
# Copyright (c) 2005-2008 Analog Device Inc.
|
||||
#
|
||||
# (C) Copyright 2001
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
# This is not actually used for Blackfin boards so do not change it
|
||||
#TEXT_BASE = do-not-use-me
|
||||
|
||||
LDSCRIPT = $(obj)board/$(BOARDDIR)/u-boot.lds
|
||||
|
||||
# Set some default LDR flags based on boot mode.
|
||||
LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE))
|
||||
@ -0,0 +1,124 @@ |
||||
/* |
||||
* U-boot - u-boot.lds.S |
||||
* |
||||
* Copyright (c) 2005-2008 Analog Device Inc. |
||||
* |
||||
* (C) Copyright 2000-2004 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <config.h> |
||||
#include <asm/blackfin.h> |
||||
#undef ALIGN |
||||
#undef ENTRY |
||||
#undef bfin |
||||
|
||||
/* If we don't actually load anything into L1 data, this will avoid |
||||
* a syntax error. If we do actually load something into L1 data, |
||||
* we'll get a linker memory load error (which is what we'd want). |
||||
* This is here in the first place so we can quickly test building |
||||
* for different CPU's which may lack non-cache L1 data. |
||||
*/ |
||||
#ifndef L1_DATA_B_SRAM |
||||
# define L1_DATA_B_SRAM CONFIG_SYS_MONITOR_BASE |
||||
# define L1_DATA_B_SRAM_SIZE 0 |
||||
#endif |
||||
|
||||
OUTPUT_ARCH(bfin) |
||||
|
||||
MEMORY |
||||
{ |
||||
ram : ORIGIN = CONFIG_SYS_MONITOR_BASE, LENGTH = CONFIG_SYS_MONITOR_LEN |
||||
l1_code : ORIGIN = L1_INST_SRAM, LENGTH = L1_INST_SRAM_SIZE |
||||
l1_data : ORIGIN = L1_DATA_B_SRAM, LENGTH = L1_DATA_B_SRAM_SIZE |
||||
} |
||||
|
||||
ENTRY(_start) |
||||
SECTIONS |
||||
{ |
||||
.text : |
||||
{ |
||||
cpu/blackfin/start.o (.text .text.*) |
||||
__initcode_start = .;
|
||||
cpu/blackfin/initcode.o (.text .text.*) |
||||
__initcode_end = .;
|
||||
*(.text .text.*) |
||||
} >ram |
||||
|
||||
.rodata : |
||||
{ |
||||
. = ALIGN(4);
|
||||
*(.rodata .rodata.*) |
||||
*(.rodata1) |
||||
*(.eh_frame) |
||||
. = ALIGN(4);
|
||||
} >ram |
||||
|
||||
.data : |
||||
{ |
||||
. = ALIGN(256);
|
||||
*(.data .data.*) |
||||
*(.data1) |
||||
*(.sdata) |
||||
*(.sdata2) |
||||
*(.dynamic) |
||||
CONSTRUCTORS |
||||
} >ram |
||||
|
||||
.u_boot_cmd : |
||||
{ |
||||
___u_boot_cmd_start = .;
|
||||
*(.u_boot_cmd) |
||||
___u_boot_cmd_end = .;
|
||||
} >ram |
||||
|
||||
.text_l1 : |
||||
{ |
||||
. = ALIGN(4);
|
||||
__stext_l1 = .;
|
||||
*(.l1.text) |
||||
. = ALIGN(4);
|
||||
__etext_l1 = .;
|
||||
} >l1_code AT>ram |
||||
__stext_l1_lma = LOADADDR(.text_l1);
|
||||
|
||||
.data_l1 : |
||||
{ |
||||
. = ALIGN(4);
|
||||
__sdata_l1 = .;
|
||||
*(.l1.data) |
||||
*(.l1.bss) |
||||
. = ALIGN(4);
|
||||
__edata_l1 = .;
|
||||
} >l1_data AT>ram |
||||
__sdata_l1_lma = LOADADDR(.data_l1);
|
||||
|
||||
.bss : |
||||
{ |
||||
. = ALIGN(4);
|
||||
__bss_start = .;
|
||||
*(.sbss) *(.scommon) |
||||
*(.dynbss) |
||||
*(.bss .bss.*) |
||||
*(COMMON) |
||||
__bss_end = .;
|
||||
} >ram |
||||
} |
||||
@ -0,0 +1,317 @@ |
||||
/*
|
||||
* video.c - run splash screen on lcd |
||||
* |
||||
* Copyright (c) 2007-2008 Analog Devices Inc. |
||||
* |
||||
* Licensed under the GPL-2 or later. |
||||
*/ |
||||
|
||||
#include <stdarg.h> |
||||
#include <common.h> |
||||
#include <config.h> |
||||
#include <malloc.h> |
||||
#include <asm/blackfin.h> |
||||
#include <asm/mach-common/bits/dma.h> |
||||
#include <i2c.h> |
||||
#include <linux/types.h> |
||||
#include <devices.h> |
||||
|
||||
int gunzip(void *, int, unsigned char *, unsigned long *); |
||||
|
||||
#define DMA_SIZE16 2 |
||||
|
||||
#include <asm/mach-common/bits/ppi.h> |
||||
#include <asm/mach-common/bits/timer.h> |
||||
|
||||
#include <asm/bfin_logo_230x230.h> |
||||
|
||||
#define LCD_X_RES 320 /* Horizontal Resolution */ |
||||
#define LCD_Y_RES 240 /* Vertical Resolution */ |
||||
#define LCD_BPP 24 /* Bit Per Pixel */ |
||||
#define LCD_PIXEL_SIZE (LCD_BPP / 8) |
||||
|
||||
#define DMA_BUS_SIZE 16 |
||||
#define LCD_CLK (12*1000*1000) /* 12MHz */ |
||||
|
||||
#define CLOCKS_PER_PIX 3 |
||||
|
||||
/* HS and VS timing parameters (all in number of PPI clk ticks) */ |
||||
#define H_ACTPIX (LCD_X_RES * CLOCKS_PER_PIX) /* active horizontal pixel */ |
||||
#define H_PERIOD (408 * CLOCKS_PER_PIX) /* HS period */ |
||||
#define H_PULSE 90 /* HS pulse width */ |
||||
#define H_START 204 /* first valid pixel */ |
||||
|
||||
#define U_LINE 1 /* Blanking Lines */ |
||||
|
||||
#define V_LINES (LCD_Y_RES + U_LINE) /* total vertical lines */ |
||||
#define V_PULSE (3 * H_PERIOD) /* VS pulse width (1-5 H_PERIODs) */ |
||||
#define V_PERIOD (H_PERIOD * V_LINES) /* VS period */ |
||||
|
||||
#define ACTIVE_VIDEO_MEM_OFFSET (U_LINE * H_ACTPIX) |
||||
|
||||
#define PPI_TX_MODE 0x2 |
||||
#define PPI_XFER_TYPE_11 0xC |
||||
#define PPI_PORT_CFG_01 0x10 |
||||
#define PPI_PACK_EN 0x80 |
||||
#define PPI_POLS_1 0x8000 |
||||
|
||||
/* enable and disable PPI functions */ |
||||
void EnablePPI(void) |
||||
{ |
||||
*pPPI_CONTROL |= PORT_EN; |
||||
} |
||||
|
||||
void DisablePPI(void) |
||||
{ |
||||
*pPPI_CONTROL &= ~PORT_EN; |
||||
} |
||||
|
||||
void Init_Ports(void) |
||||
{ |
||||
*pPORTF_MUX &= ~PORT_x_MUX_0_MASK; |
||||
*pPORTF_MUX |= PORT_x_MUX_0_FUNC_1; |
||||
*pPORTF_FER |= PF0 | PF1 | PF2 | PF3 | PF4 | PF5 | PF6 | PF7; |
||||
|
||||
*pPORTG_MUX &= ~PORT_x_MUX_1_MASK; |
||||
*pPORTG_MUX |= PORT_x_MUX_1_FUNC_1; |
||||
*pPORTG_FER |= PG5; |
||||
} |
||||
|
||||
void Init_PPI(void) |
||||
{ |
||||
|
||||
*pPPI_DELAY = H_START; |
||||
*pPPI_COUNT = (H_ACTPIX-1); |
||||
*pPPI_FRAME = 0; |
||||
|
||||
/* PPI control, to be replaced with definitions */ |
||||
*pPPI_CONTROL = PPI_TX_MODE | /* output mode , PORT_DIR */ |
||||
PPI_XFER_TYPE_11 | /* sync mode XFR_TYPE */ |
||||
PPI_PORT_CFG_01 | /* two frame sync PORT_CFG */ |
||||
PPI_PACK_EN | /* packing enabled PACK_EN */ |
||||
PPI_POLS_1; /* faling edge syncs POLS */ |
||||
} |
||||
|
||||
void Init_DMA(void *dst) |
||||
{ |
||||
*pDMA0_START_ADDR = dst; |
||||
|
||||
/* X count */ |
||||
*pDMA0_X_COUNT = H_ACTPIX / 2; |
||||
*pDMA0_X_MODIFY = DMA_BUS_SIZE / 8; |
||||
|
||||
/* Y count */ |
||||
*pDMA0_Y_COUNT = V_LINES; |
||||
*pDMA0_Y_MODIFY = DMA_BUS_SIZE / 8; |
||||
|
||||
/* DMA Config */ |
||||
*pDMA0_CONFIG = |
||||
WDSIZE_16 | /* 16 bit DMA */ |
||||
DMA2D | /* 2D DMA */ |
||||
FLOW_AUTO; /* autobuffer mode */ |
||||
} |
||||
|
||||
|
||||
void EnableDMA(void) |
||||
{ |
||||
*pDMA0_CONFIG |= DMAEN; |
||||
} |
||||
|
||||
void DisableDMA(void) |
||||
{ |
||||
*pDMA0_CONFIG &= ~DMAEN; |
||||
} |
||||
|
||||
|
||||
/* Init TIMER0 as Frame Sync 1 generator */ |
||||
void InitTIMER0(void) |
||||
{ |
||||
*pTIMER_DISABLE |= TIMDIS0; /* disable Timer */ |
||||
SSYNC(); |
||||
*pTIMER_STATUS |= TIMIL0 | TOVF_ERR0 | TRUN0; /* clear status */ |
||||
SSYNC(); |
||||
|
||||
*pTIMER0_PERIOD = H_PERIOD; |
||||
SSYNC(); |
||||
*pTIMER0_WIDTH = H_PULSE; |
||||
SSYNC(); |
||||
|
||||
*pTIMER0_CONFIG = PWM_OUT | |
||||
PERIOD_CNT | |
||||
TIN_SEL | |
||||
CLK_SEL | |
||||
EMU_RUN; |
||||
SSYNC(); |
||||
} |
||||
|
||||
void EnableTIMER0(void) |
||||
{ |
||||
*pTIMER_ENABLE |= TIMEN0; |
||||
SSYNC(); |
||||
} |
||||
|
||||
void DisableTIMER0(void) |
||||
{ |
||||
*pTIMER_DISABLE |= TIMDIS0; |
||||
SSYNC(); |
||||
} |
||||
|
||||
|
||||
void InitTIMER1(void) |
||||
{ |
||||
*pTIMER_DISABLE |= TIMDIS1; /* disable Timer */ |
||||
SSYNC(); |
||||
*pTIMER_STATUS |= TIMIL1 | TOVF_ERR1 | TRUN1; /* clear status */ |
||||
SSYNC(); |
||||
|
||||
|
||||
*pTIMER1_PERIOD = V_PERIOD; |
||||
SSYNC(); |
||||
*pTIMER1_WIDTH = V_PULSE; |
||||
SSYNC(); |
||||
|
||||
*pTIMER1_CONFIG = PWM_OUT | |
||||
PERIOD_CNT | |
||||
TIN_SEL | |
||||
CLK_SEL | |
||||
EMU_RUN; |
||||
SSYNC(); |
||||
} |
||||
|
||||
void EnableTIMER1(void) |
||||
{ |
||||
*pTIMER_ENABLE |= TIMEN1; |
||||
SSYNC(); |
||||
} |
||||
|
||||
void DisableTIMER1(void) |
||||
{ |
||||
*pTIMER_DISABLE |= TIMDIS1; |
||||
SSYNC(); |
||||
} |
||||
|
||||
int video_init(void *dst) |
||||
{ |
||||
|
||||
Init_Ports(); |
||||
Init_DMA(dst); |
||||
EnableDMA(); |
||||
InitTIMER0(); |
||||
InitTIMER1(); |
||||
Init_PPI(); |
||||
EnablePPI(); |
||||
|
||||
/* Frame sync 2 (VS) needs to start at least one PPI clk earlier */ |
||||
EnableTIMER1(); |
||||
/* Add Some Delay ... */ |
||||
SSYNC(); |
||||
SSYNC(); |
||||
SSYNC(); |
||||
SSYNC(); |
||||
|
||||
/* now start frame sync 1 */ |
||||
EnableTIMER0(); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static void dma_bitblit(void *dst, fastimage_t *logo, int x, int y) |
||||
{ |
||||
if (dcache_status()) |
||||
blackfin_dcache_flush_range(logo->data, logo->data + logo->size); |
||||
|
||||
bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR); |
||||
|
||||
/* Setup destination start address */ |
||||
bfin_write_MDMA_D0_START_ADDR(dst + ((x & -2) * LCD_PIXEL_SIZE) |
||||
+ (y * LCD_X_RES * LCD_PIXEL_SIZE)); |
||||
/* Setup destination xcount */ |
||||
bfin_write_MDMA_D0_X_COUNT(logo->width * LCD_PIXEL_SIZE / DMA_SIZE16); |
||||
/* Setup destination xmodify */ |
||||
bfin_write_MDMA_D0_X_MODIFY(DMA_SIZE16); |
||||
|
||||
/* Setup destination ycount */ |
||||
bfin_write_MDMA_D0_Y_COUNT(logo->height); |
||||
/* Setup destination ymodify */ |
||||
bfin_write_MDMA_D0_Y_MODIFY((LCD_X_RES - logo->width) * LCD_PIXEL_SIZE + DMA_SIZE16); |
||||
|
||||
|
||||
/* Setup Source start address */ |
||||
bfin_write_MDMA_S0_START_ADDR(logo->data); |
||||
/* Setup Source xcount */ |
||||
bfin_write_MDMA_S0_X_COUNT(logo->width * LCD_PIXEL_SIZE / DMA_SIZE16); |
||||
/* Setup Source xmodify */ |
||||
bfin_write_MDMA_S0_X_MODIFY(DMA_SIZE16); |
||||
|
||||
/* Setup Source ycount */ |
||||
bfin_write_MDMA_S0_Y_COUNT(logo->height); |
||||
/* Setup Source ymodify */ |
||||
bfin_write_MDMA_S0_Y_MODIFY(DMA_SIZE16); |
||||
|
||||
|
||||
/* Enable source DMA */ |
||||
bfin_write_MDMA_S0_CONFIG(DMAEN | WDSIZE_16 | DMA2D); |
||||
SSYNC(); |
||||
bfin_write_MDMA_D0_CONFIG(WNR | DMAEN | WDSIZE_16 | DMA2D); |
||||
|
||||
while (bfin_read_MDMA_D0_IRQ_STATUS() & DMA_RUN); |
||||
|
||||
bfin_write_MDMA_S0_IRQ_STATUS(bfin_read_MDMA_S0_IRQ_STATUS() | DMA_DONE | DMA_ERR); |
||||
bfin_write_MDMA_D0_IRQ_STATUS(bfin_read_MDMA_D0_IRQ_STATUS() | DMA_DONE | DMA_ERR); |
||||
|
||||
} |
||||
|
||||
void video_putc(const char c) |
||||
{ |
||||
} |
||||
|
||||
void video_puts(const char *s) |
||||
{ |
||||
} |
||||
|
||||
int drv_video_init(void) |
||||
{ |
||||
int error, devices = 1; |
||||
device_t videodev; |
||||
|
||||
u8 *dst; |
||||
u32 fbmem_size = LCD_X_RES * LCD_Y_RES * LCD_PIXEL_SIZE + ACTIVE_VIDEO_MEM_OFFSET; |
||||
|
||||
dst = malloc(fbmem_size); |
||||
|
||||
if (dst == NULL) { |
||||
printf("Failed to alloc FB memory\n"); |
||||
return -1; |
||||
} |
||||
|
||||
#ifdef EASYLOGO_ENABLE_GZIP |
||||
unsigned char *data = EASYLOGO_DECOMP_BUFFER; |
||||
unsigned long src_len = EASYLOGO_ENABLE_GZIP; |
||||
if (gunzip(data, bfin_logo.size, bfin_logo.data, &src_len)) { |
||||
puts("Failed to decompress logo\n"); |
||||
free(dst); |
||||
return -1; |
||||
} |
||||
bfin_logo.data = data; |
||||
#endif |
||||
|
||||
memset(dst + ACTIVE_VIDEO_MEM_OFFSET, bfin_logo.data[0], fbmem_size - ACTIVE_VIDEO_MEM_OFFSET); |
||||
|
||||
dma_bitblit(dst + ACTIVE_VIDEO_MEM_OFFSET, &bfin_logo, |
||||
(LCD_X_RES - bfin_logo.width) / 2, |
||||
(LCD_Y_RES - bfin_logo.height) / 2); |
||||
|
||||
video_init(dst); /* Video initialization */ |
||||
|
||||
memset(&videodev, 0, sizeof(videodev)); |
||||
|
||||
strcpy(videodev.name, "video"); |
||||
videodev.ext = DEV_EXT_VIDEO; /* Video extensions */ |
||||
videodev.flags = DEV_FLAGS_SYSTEM; /* No Output */ |
||||
videodev.putc = video_putc; /* 'putc' function */ |
||||
videodev.puts = video_puts; /* 'puts' function */ |
||||
|
||||
error = device_register(&videodev); |
||||
|
||||
return (error == 0) ? devices : error; |
||||
} |
||||
@ -0,0 +1,172 @@ |
||||
/*
|
||||
* U-boot - Configuration file for BF537 STAMP board |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_BF527_EZKIT_H__ |
||||
#define __CONFIG_BF527_EZKIT_H__ |
||||
|
||||
#include <asm/blackfin-config-pre.h> |
||||
|
||||
|
||||
/*
|
||||
* Processor Settings |
||||
*/ |
||||
#define CONFIG_BFIN_CPU bf527-0.0 |
||||
#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA |
||||
|
||||
|
||||
/*
|
||||
* Clock Settings |
||||
* CCLK = (CLKIN * VCO_MULT) / CCLK_DIV |
||||
* SCLK = (CLKIN * VCO_MULT) / SCLK_DIV |
||||
*/ |
||||
/* CONFIG_CLKIN_HZ is any value in Hz */ |
||||
#define CONFIG_CLKIN_HZ 25000000 |
||||
/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ |
||||
/* 1 = CLKIN / 2 */ |
||||
#define CONFIG_CLKIN_HALF 0 |
||||
/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ |
||||
/* 1 = bypass PLL */ |
||||
#define CONFIG_PLL_BYPASS 0 |
||||
/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ |
||||
/* Values can range from 0-63 (where 0 means 64) */ |
||||
#define CONFIG_VCO_MULT 21 |
||||
/* CCLK_DIV controls the core clock divider */ |
||||
/* Values can be 1, 2, 4, or 8 ONLY */ |
||||
#define CONFIG_CCLK_DIV 1 |
||||
/* SCLK_DIV controls the system clock divider */ |
||||
/* Values can range from 1-15 */ |
||||
#define CONFIG_SCLK_DIV 4 |
||||
|
||||
|
||||
/*
|
||||
* Memory Settings |
||||
*/ |
||||
#define CONFIG_MEM_ADD_WDTH 10 |
||||
#define CONFIG_MEM_SIZE 64 |
||||
|
||||
#define CONFIG_EBIU_SDRRC_VAL 0x03F6 |
||||
#define CONFIG_EBIU_SDGCTL_VAL (SCTLE | CL_3 | PASR_ALL | TRAS_6 | TRP_3 | TRCD_3 | TWR_2 | PSS) |
||||
|
||||
#define CONFIG_EBIU_AMGCTL_VAL (AMCKEN | AMBEN_ALL) |
||||
#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_15 | B1RAT_15 | B1HT_3 | B1RDYPOL | B0WAT_15 | B0RAT_15 | B0HT_3 | B0RDYPOL) |
||||
#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_15 | B3RAT_15 | B3HT_3 | B3RDYPOL | B2WAT_15 | B2RAT_15 | B2HT_3 | B2RDYPOL) |
||||
|
||||
#define CONFIG_SYS_MONITOR_LEN (768 * 1024) |
||||
#define CONFIG_SYS_MALLOC_LEN (640 * 1024) |
||||
|
||||
|
||||
/*
|
||||
* NAND Settings |
||||
* (can't be used same time as ethernet) |
||||
*/ |
||||
#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND) |
||||
#define CONFIG_BFIN_NFC |
||||
#endif |
||||
#ifdef CONFIG_BFIN_NFC |
||||
#define CONFIG_BFIN_NFC_CTL_VAL 0x0033 |
||||
#define CONFIG_DRIVER_NAND_BFIN |
||||
#define CONFIG_SYS_NAND_BASE 0 /* not actually used */ |
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1 |
||||
#define NAND_MAX_CHIPS 1 |
||||
#define CONFIG_CMD_NAND |
||||
#endif |
||||
|
||||
|
||||
/*
|
||||
* Network Settings |
||||
*/ |
||||
#if !defined(__ADSPBF522__) && !defined(__ADSPBF523__) && \ |
||||
!defined(__ADSPBF524__) && !defined(__ADSPBF525__) && !defined(CONFIG_BFIN_NFC) |
||||
#define ADI_CMDS_NETWORK 1 |
||||
#define CONFIG_BFIN_MAC |
||||
#define CONFIG_RMII |
||||
#define CONFIG_NETCONSOLE 1 |
||||
#define CONFIG_NET_MULTI 1 |
||||
#endif |
||||
#define CONFIG_HOSTNAME bf527-ezkit |
||||
/* Uncomment next line to use fixed MAC address */ |
||||
/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */ |
||||
|
||||
|
||||
/*
|
||||
* Flash Settings |
||||
*/ |
||||
#define CONFIG_FLASH_CFI_DRIVER |
||||
#define CONFIG_SYS_FLASH_BASE 0x20000000 |
||||
#define CONFIG_SYS_FLASH_CFI |
||||
#define CONFIG_SYS_FLASH_PROTECTION |
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 |
||||
#define CONFIG_SYS_MAX_FLASH_SECT 259 |
||||
|
||||
|
||||
/*
|
||||
* SPI Settings |
||||
*/ |
||||
#define CONFIG_BFIN_SPI |
||||
#define CONFIG_ENV_SPI_MAX_HZ 30000000 |
||||
#define CONFIG_SF_DEFAULT_HZ 30000000 |
||||
#define CONFIG_SPI_FLASH |
||||
#define CONFIG_SPI_FLASH_STMICRO |
||||
|
||||
|
||||
/*
|
||||
* Env Storage Settings |
||||
*/ |
||||
#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) |
||||
#define CONFIG_ENV_IS_IN_SPI_FLASH |
||||
#define CONFIG_ENV_OFFSET 0x4000 |
||||
#define CONFIG_ENV_SIZE 0x2000 |
||||
#define CONFIG_ENV_SECT_SIZE 0x2000 |
||||
#else |
||||
#define CONFIG_ENV_IS_IN_FLASH |
||||
#define CONFIG_ENV_OFFSET 0x4000 |
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) |
||||
#define CONFIG_ENV_SIZE 0x2000 |
||||
#define CONFIG_ENV_SECT_SIZE 0x2000 |
||||
#endif |
||||
#define ENV_IS_EMBEDDED_CUSTOM |
||||
|
||||
|
||||
/*
|
||||
* I2C Settings |
||||
*/ |
||||
#define CONFIG_BFIN_TWI_I2C 1 |
||||
#define CONFIG_HARD_I2C 1 |
||||
#define CONFIG_SYS_I2C_SPEED 50000 |
||||
#define CONFIG_SYS_I2C_SLAVE 0 |
||||
|
||||
|
||||
/*
|
||||
* USB Settings |
||||
*/ |
||||
#if !defined(__ADSPBF522__) && !defined(__ADSPBF523__) |
||||
#define CONFIG_USB |
||||
#define CONFIG_MUSB_HCD |
||||
#define CONFIG_USB_BLACKFIN |
||||
#define CONFIG_USB_STORAGE |
||||
#define CONFIG_MUSB_TIMEOUT 100000 |
||||
#endif |
||||
|
||||
|
||||
/*
|
||||
* Misc Settings |
||||
*/ |
||||
#define CONFIG_MISC_INIT_R |
||||
#define CONFIG_RTC_BFIN |
||||
#define CONFIG_UART_CONSOLE 1 |
||||
|
||||
/* Don't waste time transferring a logo over the UART */ |
||||
#if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_UART) |
||||
# define CONFIG_VIDEO |
||||
#endif |
||||
|
||||
|
||||
/*
|
||||
* Pull in common ADI header for remaining command/environment setup |
||||
*/ |
||||
#include <configs/bfin_adi_common.h> |
||||
|
||||
#include <asm/blackfin-config-post.h> |
||||
|
||||
#endif |
||||
Loading…
Reference in new issue