This commit replaces hard-coded EMIF and PHY DDR3 configurations for predefined SODIMMs to a calculated configuration. The SODIMM parameters are read from SODIMM's SPD and used to calculated the configuration. The current commit supports calculation for DDR3 with 1600MHz and 1333MHz only. Signed-off-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>master
Vitaly Andrianov
9 years ago
committed by
Tom Rini
parent
ef76ebb1ef
commit
d9a76e77c8
@ -0,0 +1,453 @@ |
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/*
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* Keystone2: DDR3 SPD configuration |
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* |
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* (C) Copyright 2015-2016 Texas Instruments Incorporated, <www.ti.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <i2c.h> |
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#include <ddr_spd.h> |
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#include <asm/arch/ddr3.h> |
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#include <asm/arch/hardware.h> |
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#define DUMP_DDR_CONFIG 0 /* set to 1 to debug */ |
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#define debug_ddr_cfg(fmt, args...) \ |
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debug_cond(DUMP_DDR_CONFIG, fmt, ##args) |
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static void dump_phy_config(struct ddr3_phy_config *ptr) |
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{ |
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debug_ddr_cfg("\npllcr 0x%08X\n", ptr->pllcr); |
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debug_ddr_cfg("pgcr1_mask 0x%08X\n", ptr->pgcr1_mask); |
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debug_ddr_cfg("pgcr1_val 0x%08X\n", ptr->pgcr1_val); |
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debug_ddr_cfg("ptr0 0x%08X\n", ptr->ptr0); |
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debug_ddr_cfg("ptr1 0x%08X\n", ptr->ptr1); |
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debug_ddr_cfg("ptr2 0x%08X\n", ptr->ptr2); |
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debug_ddr_cfg("ptr3 0x%08X\n", ptr->ptr3); |
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debug_ddr_cfg("ptr4 0x%08X\n", ptr->ptr4); |
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debug_ddr_cfg("dcr_mask 0x%08X\n", ptr->dcr_mask); |
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debug_ddr_cfg("dcr_val 0x%08X\n", ptr->dcr_val); |
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debug_ddr_cfg("dtpr0 0x%08X\n", ptr->dtpr0); |
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debug_ddr_cfg("dtpr1 0x%08X\n", ptr->dtpr1); |
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debug_ddr_cfg("dtpr2 0x%08X\n", ptr->dtpr2); |
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debug_ddr_cfg("mr0 0x%08X\n", ptr->mr0); |
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debug_ddr_cfg("mr1 0x%08X\n", ptr->mr1); |
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debug_ddr_cfg("mr2 0x%08X\n", ptr->mr2); |
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debug_ddr_cfg("dtcr 0x%08X\n", ptr->dtcr); |
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debug_ddr_cfg("pgcr2 0x%08X\n", ptr->pgcr2); |
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debug_ddr_cfg("zq0cr1 0x%08X\n", ptr->zq0cr1); |
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debug_ddr_cfg("zq1cr1 0x%08X\n", ptr->zq1cr1); |
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debug_ddr_cfg("zq2cr1 0x%08X\n", ptr->zq2cr1); |
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debug_ddr_cfg("pir_v1 0x%08X\n", ptr->pir_v1); |
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debug_ddr_cfg("pir_v2 0x%08X\n\n", ptr->pir_v2); |
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}; |
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static void dump_emif_config(struct ddr3_emif_config *ptr) |
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{ |
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debug_ddr_cfg("\nsdcfg 0x%08X\n", ptr->sdcfg); |
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debug_ddr_cfg("sdtim1 0x%08X\n", ptr->sdtim1); |
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debug_ddr_cfg("sdtim2 0x%08X\n", ptr->sdtim2); |
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debug_ddr_cfg("sdtim3 0x%08X\n", ptr->sdtim3); |
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debug_ddr_cfg("sdtim4 0x%08X\n", ptr->sdtim4); |
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debug_ddr_cfg("zqcfg 0x%08X\n", ptr->zqcfg); |
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debug_ddr_cfg("sdrfc 0x%08X\n\n", ptr->sdrfc); |
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}; |
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#define TEMP NORMAL_TEMP |
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#define VBUS_CLKPERIOD 1.875 /* Corresponds to vbus=533MHz, */ |
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#define PLLGS_VAL (4000.0 / VBUS_CLKPERIOD) /* 4 us */ |
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#define PLLPD_VAL (1000.0 / VBUS_CLKPERIOD) /* 1 us */ |
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#define PLLLOCK_VAL (100000.0 / VBUS_CLKPERIOD) /* 100 us */ |
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#define PLLRST_VAL (9000.0 / VBUS_CLKPERIOD) /* 9 us */ |
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#define PHYRST_VAL 0x10 |
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#define DDR_TERM RZQ_4_TERM |
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#define SDRAM_DRIVE RZQ_7_IMP |
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#define DYN_ODT ODT_DISABLE |
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enum srt { |
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NORMAL_TEMP, |
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EXTENDED_TEMP |
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}; |
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enum out_impedance { |
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RZQ_6_IMP = 0, |
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RZQ_7_IMP |
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}; |
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enum die_term { |
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ODT_DISABLE = 0, |
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RZQ_4_TERM, |
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RZQ_2_TERM, |
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RZQ_6_TERM, |
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RZQ_12_TERM, |
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RZQ_8_TERM |
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}; |
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struct ddr3_sodimm { |
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u32 t_ck; |
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u32 freqsel; |
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u32 t_xp; |
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u32 t_cke; |
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u32 t_pllpd; |
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u32 t_pllgs; |
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u32 t_phyrst; |
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u32 t_plllock; |
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u32 t_pllrst; |
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u32 t_rfc; |
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u32 t_xs; |
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u32 t_dinit0; |
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u32 t_dinit1; |
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u32 t_dinit2; |
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u32 t_dinit3; |
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u32 t_rtp; |
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u32 t_wtr; |
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u32 t_rp; |
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u32 t_rcd; |
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u32 t_ras; |
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u32 t_rrd; |
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u32 t_rc; |
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u32 t_faw; |
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u32 t_mrd; |
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u32 t_mod; |
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u32 t_wlo; |
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u32 t_wlmrd; |
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u32 t_xsdll; |
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u32 t_xpdll; |
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u32 t_ckesr; |
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u32 t_dllk; |
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u32 t_wr; |
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u32 t_wr_bin; |
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u32 cas; |
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u32 cwl; |
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u32 asr; |
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u32 pasr; |
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u32 t_refprd; |
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u8 sdram_type; |
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u8 ibank; |
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u8 pagesize; |
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u8 t_rrd2; |
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u8 t_ras_max; |
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u8 t_zqcs; |
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u32 refresh_rate; |
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u8 t_csta; |
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u8 rank; |
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u8 mirrored; |
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u8 buswidth; |
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}; |
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static u8 cas_latancy(u16 temp) |
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{ |
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int loop; |
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u8 cas_bin = 0; |
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for (loop = 0; loop < 32; loop += 2, temp >>= 1) { |
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if (temp & 0x0001) |
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cas_bin = (loop > 15) ? loop - 15 : loop; |
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} |
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return cas_bin; |
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} |
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static int ddr3_get_size_in_mb(ddr3_spd_eeprom_t *buf) |
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{ |
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return (((buf->organization & 0x38) >> 3) + 1) * |
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(256 << (buf->density_banks & 0xf)); |
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} |
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static int ddrtimingcalculation(ddr3_spd_eeprom_t *buf, struct ddr3_sodimm *spd, |
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struct ddr3_spd_cb *spd_cb) |
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{ |
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u32 mtb, clk_freq; |
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if ((buf->mem_type != 0x0b) || |
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((buf->density_banks & 0x70) != 0x00)) |
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return 1; |
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spd->sdram_type = 0x03; |
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spd->ibank = 0x03; |
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mtb = buf->mtb_dividend * 1000 / buf->mtb_divisor; |
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spd->t_ck = buf->tck_min * mtb; |
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spd_cb->ddrspdclock = 2000000 / spd->t_ck; |
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clk_freq = spd_cb->ddrspdclock / 2; |
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spd->rank = ((buf->organization & 0x38) >> 3) + 1; |
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if (spd->rank > 2) |
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return 1; |
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spd->pagesize = (buf->addressing & 0x07) + 1; |
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if (spd->pagesize > 3) |
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return 1; |
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spd->buswidth = 8 << (buf->bus_width & 0x7); |
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if ((spd->buswidth < 16) || (spd->buswidth > 64)) |
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return 1; |
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spd->mirrored = buf->mod_section.unbuffered.addr_mapping & 1; |
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printf("DDR3A Speed will be configured for %d Operation.\n", |
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spd_cb->ddrspdclock); |
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if (spd_cb->ddrspdclock == 1333) { |
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spd->t_xp = ((3 * spd->t_ck) > 6000) ? |
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3 : ((5999 / spd->t_ck) + 1); |
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spd->t_cke = ((3 * spd->t_ck) > 5625) ? |
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3 : ((5624 / spd->t_ck) + 1); |
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} else if (spd_cb->ddrspdclock == 1600) { |
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spd->t_xp = ((3 * spd->t_ck) > 6000) ? |
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3 : ((5999 / spd->t_ck) + 1); |
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spd->t_cke = ((3 * spd->t_ck) > 5000) ? |
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3 : ((4999 / spd->t_ck) + 1); |
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} else { |
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printf("Unsupported DDR3 speed %d\n", spd_cb->ddrspdclock); |
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return 1; |
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} |
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spd->t_xpdll = (spd->t_ck > 2400) ? 10 : 24000 / spd->t_ck; |
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spd->t_ckesr = spd->t_cke + 1; |
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/* SPD Calculated Values */ |
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spd->cas = cas_latancy((buf->caslat_msb << 8) | |
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buf->caslat_lsb); |
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spd->t_wr = (buf->twr_min * mtb) / spd->t_ck; |
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spd->t_wr_bin = (spd->t_wr / 2) & 0x07; |
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spd->t_rcd = ((buf->trcd_min * mtb) - 1) / spd->t_ck + 1; |
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spd->t_rrd = ((buf->trrd_min * mtb) - 1) / spd->t_ck + 1; |
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spd->t_rp = (((buf->trp_min * mtb) - 1) / spd->t_ck) + 1; |
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spd->t_ras = (((buf->tras_trc_ext & 0x0f) << 8 | buf->tras_min_lsb) * |
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mtb) / spd->t_ck; |
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spd->t_rc = (((((buf->tras_trc_ext & 0xf0) << 4) | buf->trc_min_lsb) * |
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mtb) - 1) / spd->t_ck + 1; |
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spd->t_rfc = (buf->trfc_min_lsb | (buf->trfc_min_msb << 8)) * mtb / |
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1000; |
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spd->t_wtr = (buf->twtr_min * mtb) / spd->t_ck; |
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spd->t_rtp = (buf->trtp_min * mtb) / spd->t_ck; |
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spd->t_xs = (((spd->t_rfc + 10) * 1000) / spd->t_ck); |
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spd->t_rfc = ((spd->t_rfc * 1000) - 1) / spd->t_ck + 1; |
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spd->t_faw = (((buf->tfaw_msb << 8) | buf->tfaw_min) * mtb) / spd->t_ck; |
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spd->t_rrd2 = ((((buf->tfaw_msb << 8) | |
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buf->tfaw_min) * mtb) / (4 * spd->t_ck)) - 1; |
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/* Hard-coded values */ |
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spd->t_mrd = 0x00; |
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spd->t_mod = 0x00; |
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spd->t_wlo = 0x0C; |
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spd->t_wlmrd = 0x28; |
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spd->t_xsdll = 0x200; |
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spd->t_ras_max = 0x0F; |
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spd->t_csta = 0x05; |
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spd->t_dllk = 0x200; |
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/* CAS Write Latency */ |
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if (spd->t_ck >= 2500) |
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spd->cwl = 0; |
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else if (spd->t_ck >= 1875) |
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spd->cwl = 1; |
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else if (spd->t_ck >= 1500) |
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spd->cwl = 2; |
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else if (spd->t_ck >= 1250) |
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spd->cwl = 3; |
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else if (spd->t_ck >= 1071) |
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spd->cwl = 4; |
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else |
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spd->cwl = 5; |
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/* SD:RAM Thermal and Refresh Options */ |
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spd->asr = (buf->therm_ref_opt & 0x04) >> 2; |
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spd->pasr = (buf->therm_ref_opt & 0x80) >> 7; |
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spd->t_zqcs = 64; |
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spd->t_refprd = (TEMP == NORMAL_TEMP) ? 7812500 : 3906250; |
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spd->t_refprd = spd->t_refprd / spd->t_ck; |
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spd->refresh_rate = spd->t_refprd; |
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spd->t_refprd = spd->t_refprd * 5; |
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/* Set MISC PHY space registers fields */ |
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if ((clk_freq / 2) >= 166 && (clk_freq / 2 < 275)) |
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spd->freqsel = 0x03; |
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else if ((clk_freq / 2) > 225 && (clk_freq / 2 < 385)) |
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spd->freqsel = 0x01; |
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else if ((clk_freq / 2) > 335 && (clk_freq / 2 < 534)) |
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spd->freqsel = 0x00; |
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spd->t_dinit0 = 500000000 / spd->t_ck; /* CKE low time 500 us */ |
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spd->t_dinit1 = spd->t_xs; |
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spd->t_dinit2 = 200000000 / spd->t_ck; /* Reset low time 200 us */ |
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/* Time from ZQ initialization command to first command (1 us) */ |
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spd->t_dinit3 = 1000000 / spd->t_ck; |
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spd->t_pllgs = PLLGS_VAL + 1; |
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spd->t_pllpd = PLLPD_VAL + 1; |
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spd->t_plllock = PLLLOCK_VAL + 1; |
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spd->t_pllrst = PLLRST_VAL; |
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spd->t_phyrst = PHYRST_VAL; |
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spd_cb->ddr_size_gbyte = ddr3_get_size_in_mb(buf) / 1024; |
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return 0; |
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} |
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static void init_ddr3param(struct ddr3_spd_cb *spd_cb, |
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struct ddr3_sodimm *spd) |
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{ |
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spd_cb->phy_cfg.pllcr = (spd->freqsel & 3) << 18 | 0xE << 13; |
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spd_cb->phy_cfg.pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK); |
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spd_cb->phy_cfg.pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)); |
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spd_cb->phy_cfg.ptr0 = ((spd->t_pllpd & 0x7ff) << 21) | |
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((spd->t_pllgs & 0x7fff) << 6) | (spd->t_phyrst & 0x3f); |
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spd_cb->phy_cfg.ptr1 = ((spd->t_plllock & 0xffff) << 16) | |
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(spd->t_pllrst & 0x1fff); |
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spd_cb->phy_cfg.ptr2 = 0; |
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spd_cb->phy_cfg.ptr3 = ((spd->t_dinit1 & 0x1ff) << 20) | |
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(spd->t_dinit0 & 0xfffff); |
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spd_cb->phy_cfg.ptr4 = ((spd->t_dinit3 & 0x3ff) << 18) | |
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(spd->t_dinit2 & 0x3ffff); |
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spd_cb->phy_cfg.dcr_mask = PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK; |
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spd_cb->phy_cfg.dcr_val = 1 << 10; |
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if (spd->mirrored) { |
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spd_cb->phy_cfg.dcr_mask |= NOSRA_MASK | UDIMM_MASK; |
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spd_cb->phy_cfg.dcr_val |= (1 << 27) | (1 << 29); |
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} |
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spd_cb->phy_cfg.dtpr0 = (spd->t_rc & 0x3f) << 26 | |
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(spd->t_rrd & 0xf) << 22 | |
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(spd->t_ras & 0x3f) << 16 | (spd->t_rcd & 0xf) << 12 | |
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(spd->t_rp & 0xf) << 8 | (spd->t_wtr & 0xf) << 4 | |
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(spd->t_rtp & 0xf); |
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spd_cb->phy_cfg.dtpr1 = (spd->t_wlo & 0xf) << 26 | |
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(spd->t_wlmrd & 0x3f) << 20 | (spd->t_rfc & 0x1ff) << 11 | |
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(spd->t_faw & 0x3f) << 5 | (spd->t_mod & 0x7) << 2 | |
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(spd->t_mrd & 0x3); |
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spd_cb->phy_cfg.dtpr2 = 0 << 31 | 1 << 30 | 0 << 29 | |
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(spd->t_dllk & 0x3ff) << 19 | (spd->t_ckesr & 0xf) << 15; |
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spd_cb->phy_cfg.dtpr2 |= (((spd->t_xp > spd->t_xpdll) ? |
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spd->t_xp : spd->t_xpdll) & |
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0x1f) << 10; |
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spd_cb->phy_cfg.dtpr2 |= (((spd->t_xs > spd->t_xsdll) ? |
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spd->t_xs : spd->t_xsdll) & |
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0x3ff); |
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spd_cb->phy_cfg.mr0 = 1 << 12 | (spd->t_wr_bin & 0x7) << 9 | 0 << 8 | |
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0 << 7 | ((spd->cas & 0x0E) >> 1) << 4 | 0 << 3 | |
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(spd->cas & 0x01) << 2; |
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spd_cb->phy_cfg.mr1 = 0 << 12 | 0 << 11 | 0 << 7 | 0 << 3 | |
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((DDR_TERM >> 2) & 1) << 9 | ((DDR_TERM >> 1) & 1) << 6 | |
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(DDR_TERM & 0x1) << 2 | ((SDRAM_DRIVE >> 1) & 1) << 5 | |
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(SDRAM_DRIVE & 1) << 1 | 0 << 0; |
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spd_cb->phy_cfg.mr2 = DYN_ODT << 9 | TEMP << 7 | (spd->asr & 1) << 6 | |
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(spd->cwl & 7) << 3 | (spd->pasr & 7); |
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spd_cb->phy_cfg.dtcr = (spd->rank == 2) ? 0x730035C7 : 0x710035C7; |
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spd_cb->phy_cfg.pgcr2 = (0xF << 20) | ((int)spd->t_refprd & 0x3ffff); |
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spd_cb->phy_cfg.zq0cr1 = 0x0000005D; |
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spd_cb->phy_cfg.zq1cr1 = 0x0000005B; |
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spd_cb->phy_cfg.zq2cr1 = 0x0000005B; |
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spd_cb->phy_cfg.pir_v1 = 0x00000033; |
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spd_cb->phy_cfg.pir_v2 = 0x0000FF81; |
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/* EMIF Registers */ |
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spd_cb->emif_cfg.sdcfg = spd->sdram_type << 29 | (DDR_TERM & 7) << 25 | |
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(DYN_ODT & 3) << 22 | (spd->cwl & 0x7) << 14 | |
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(spd->cas & 0xf) << 8 | (spd->ibank & 3) << 5 | |
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(spd->buswidth & 3) << 12 | (spd->pagesize & 3); |
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if (spd->rank == 2) |
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spd_cb->emif_cfg.sdcfg |= 1 << 3; |
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spd_cb->emif_cfg.sdtim1 = ((spd->t_wr - 1) & 0x1f) << 25 | |
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((spd->t_ras - 1) & 0x7f) << 18 | |
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((spd->t_rc - 1) & 0xff) << 10 | |
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(spd->t_rrd2 & 0x3f) << 4 | |
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((spd->t_wtr - 1) & 0xf); |
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spd_cb->emif_cfg.sdtim2 = 0x07 << 10 | ((spd->t_rp - 1) & 0x1f) << 5 | |
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((spd->t_rcd - 1) & 0x1f); |
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spd_cb->emif_cfg.sdtim3 = ((spd->t_xp - 2) & 0xf) << 28 | |
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((spd->t_xs - 1) & 0x3ff) << 18 | |
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((spd->t_xsdll - 1) & 0x3ff) << 8 | |
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((spd->t_rtp - 1) & 0xf) << 4 | ((spd->t_cke) & 0xf); |
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spd_cb->emif_cfg.sdtim4 = (spd->t_csta & 0xf) << 28 | |
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((spd->t_ckesr - 1) & 0xf) << 24 | |
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((spd->t_zqcs - 1) & 0xff) << 16 | |
||||
((spd->t_rfc - 1) & 0x3ff) << 4 | |
||||
(spd->t_ras_max & 0xf); |
||||
|
||||
spd_cb->emif_cfg.sdrfc = (spd->refresh_rate - 1) & 0xffff; |
||||
|
||||
/* TODO zqcfg value fixed ,May be required correction for K2E evm. */ |
||||
spd_cb->emif_cfg.zqcfg = (spd->rank == 2) ? 0xF0073200 : 0x70073200; |
||||
} |
||||
|
||||
static int ddr3_read_spd(ddr3_spd_eeprom_t *spd_params) |
||||
{ |
||||
int ret; |
||||
int old_bus; |
||||
|
||||
i2c_init(CONFIG_SYS_DAVINCI_I2C_SPEED, CONFIG_SYS_DAVINCI_I2C_SLAVE); |
||||
|
||||
old_bus = i2c_get_bus_num(); |
||||
i2c_set_bus_num(1); |
||||
|
||||
ret = i2c_read(0x53, 0, 1, (unsigned char *)spd_params, 256); |
||||
|
||||
i2c_set_bus_num(old_bus); |
||||
|
||||
if (ret) { |
||||
printf("Cannot read DIMM params\n"); |
||||
return 1; |
||||
} |
||||
|
||||
if (ddr3_spd_check(spd_params)) |
||||
return 1; |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int ddr3_get_dimm_params_from_spd(struct ddr3_spd_cb *spd_cb) |
||||
{ |
||||
struct ddr3_sodimm spd; |
||||
ddr3_spd_eeprom_t spd_params; |
||||
|
||||
memset(&spd, 0, sizeof(spd)); |
||||
|
||||
if (ddr3_read_spd(&spd_params)) |
||||
return 1; |
||||
|
||||
if (ddrtimingcalculation(&spd_params, &spd, spd_cb)) { |
||||
printf("Timing caclulation error\n"); |
||||
return 1; |
||||
} |
||||
|
||||
strncpy(spd_cb->dimm_name, (char *)spd_params.mpart, 18); |
||||
spd_cb->dimm_name[18] = '\0'; |
||||
|
||||
init_ddr3param(spd_cb, &spd); |
||||
|
||||
dump_emif_config(&spd_cb->emif_cfg); |
||||
dump_phy_config(&spd_cb->phy_cfg); |
||||
|
||||
return 0; |
||||
} |
||||
@ -1,17 +1,17 @@ |
||||
#
|
||||
# KS2-EVM: board Makefile
|
||||
# (C) Copyright 2012-2014
|
||||
# (C) Copyright 2012-2015
|
||||
# Texas Instruments Incorporated, <www.ti.com>
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
obj-y += board.o
|
||||
obj-y += ddr3_cfg.o
|
||||
obj-$(CONFIG_K2HK_EVM) += board_k2hk.o
|
||||
obj-$(CONFIG_K2HK_EVM) += ddr3_k2hk.o
|
||||
obj-$(CONFIG_K2E_EVM) += board_k2e.o
|
||||
obj-$(CONFIG_K2E_EVM) += ddr3_k2e.o
|
||||
obj-$(CONFIG_K2L_EVM) += board_k2l.o
|
||||
obj-$(CONFIG_K2L_EVM) += ddr3_k2l.o
|
||||
obj-$(CONFIG_K2L_EVM) += ddr3_cfg.o
|
||||
obj-$(CONFIG_K2G_EVM) += board_k2g.o
|
||||
obj-$(CONFIG_K2G_EVM) += ddr3_k2g.o
|
||||
|
||||
Loading…
Reference in new issue