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ColdFire: MCF532x header files cleanup

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Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
Signed-off by: John Rigby <jrigby@freescale.com>
master
TsiChungLiew 17 years ago
parent 7af7751d04
commit d9aae62609
2 changed files with 6 additions and 468 deletions
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  1. 193
      include/asm-m68k/immap_5329.h
  2. 281
      include/asm-m68k/m5329.h

193
include/asm-m68k/immap_5329.h
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@ -68,6 +68,12 @@
#define MMAP_SSI 0xFC0BC000
#define MMAP_PLL 0xFC0C0000
#include <asm/coldfire/crossbar.h>
#include <asm/coldfire/edma.h>
#include <asm/coldfire/flexbus.h>
#include <asm/coldfire/lcd.h>
#include <asm/coldfire/ssi.h>
/* System control module registers */
typedef struct scm1_ctrl {
u32 mpr0; /* 0x00 Master Privilege Register 0 */
@ -159,61 +165,6 @@ typedef struct scm2_ctrl {
u32 bmt1; /* 0x54 Bus Monitor Timeout 1 */
} scm2_t;
/* Cross-Bar Switch Module */
typedef struct xbs_ctrl {
u32 prs1; /* 0x100 Priority Register Slave 1 */
u32 res1[3]; /* 0x104 - 0F */
u32 crs1; /* 0x110 Control Register Slave 1 */
u32 res2[187]; /* 0x114 - 0x3FF */
u32 prs4; /* 0x400 Priority Register Slave 4 */
u32 res3[3]; /* 0x404 - 0F */
u32 crs4; /* 0x410 Control Register Slave 4 */
u32 res4[123]; /* 0x414 - 0x5FF */
u32 prs6; /* 0x600 Priority Register Slave 6 */
u32 res5[3]; /* 0x604 - 0F */
u32 crs6; /* 0x610 Control Register Slave 6 */
u32 res6[59]; /* 0x614 - 0x6FF */
u32 prs7; /* 0x700 Priority Register Slave 7 */
u32 res7[3]; /* 0x704 - 0F */
u32 crs7; /* 0x710 Control Register Slave 7 */
} xbs_t;
/* Flexbus module Chip select registers */
typedef struct fbcs_ctrl {
u16 csar0; /* 0x00 Chip-Select Address Register 0 */
u16 res0;
u32 csmr0; /* 0x04 Chip-Select Mask Register 0 */
u32 cscr0; /* 0x08 Chip-Select Control Register 0 */
u16 csar1; /* 0x0C Chip-Select Address Register 1 */
u16 res1;
u32 csmr1; /* 0x10 Chip-Select Mask Register 1 */
u32 cscr1; /* 0x14 Chip-Select Control Register 1 */
u16 csar2; /* 0x18 Chip-Select Address Register 2 */
u16 res2;
u32 csmr2; /* 0x1C Chip-Select Mask Register 2 */
u32 cscr2; /* 0x20 Chip-Select Control Register 2 */
u16 csar3; /* 0x24 Chip-Select Address Register 3 */
u16 res3;
u32 csmr3; /* 0x28 Chip-Select Mask Register 3 */
u32 cscr3; /* 0x2C Chip-Select Control Register 3 */
u16 csar4; /* 0x30 Chip-Select Address Register 4 */
u16 res4;
u32 csmr4; /* 0x34 Chip-Select Mask Register 4 */
u32 cscr4; /* 0x38 Chip-Select Control Register 4 */
u16 csar5; /* 0x3C Chip-Select Address Register 5 */
u16 res5;
u32 csmr5; /* 0x40 Chip-Select Mask Register 5 */
u32 cscr5; /* 0x44 Chip-Select Control Register 5 */
} fbcs_t;
/* FlexCan module registers */
typedef struct can_ctrl {
u32 mcr; /* 0x00 Module Configuration register */
@ -255,64 +206,6 @@ typedef struct scm3_ctrl {
u32 cfdtr; /* 0x7C Core Fault Data Register */
} scm3_t;
/* eDMA module registers */
typedef struct edma_ctrl {
u32 cr; /* 0x00 Control Register */
u32 es; /* 0x04 Error Status Register */
u16 res1[3]; /* 0x08 - 0x0D */
u16 erq; /* 0x0E Enable Request Register */
u16 res2[3]; /* 0x10 - 0x15 */
u16 eei; /* 0x16 Enable Error Interrupt Request */
u8 serq; /* 0x18 Set Enable Request */
u8 cerq; /* 0x19 Clear Enable Request */
u8 seei; /* 0x1A Set Enable Error Interrupt Request */
u8 ceei; /* 0x1B Clear Enable Error Interrupt Request */
u8 cint; /* 0x1C Clear Interrupt Enable Register */
u8 cerr; /* 0x1D Clear Error Register */
u8 ssrt; /* 0x1E Set START Bit Register */
u8 cdne; /* 0x1F Clear DONE Status Bit Register */
u16 res3[3]; /* 0x20 - 0x25 */
u16 intr; /* 0x26 Interrupt Request Register */
u16 res4[3]; /* 0x28 - 0x2D */
u16 err; /* 0x2E Error Register */
u32 res5[52]; /* 0x30 - 0xFF */
u8 dchpri0; /* 0x100 Channel 0 Priority Register */
u8 dchpri1; /* 0x101 Channel 1 Priority Register */
u8 dchpri2; /* 0x102 Channel 2 Priority Register */
u8 dchpri3; /* 0x103 Channel 3 Priority Register */
u8 dchpri4; /* 0x104 Channel 4 Priority Register */
u8 dchpri5; /* 0x105 Channel 5 Priority Register */
u8 dchpri6; /* 0x106 Channel 6 Priority Register */
u8 dchpri7; /* 0x107 Channel 7 Priority Register */
u8 dchpri8; /* 0x108 Channel 8 Priority Register */
u8 dchpri9; /* 0x109 Channel 9 Priority Register */
u8 dchpri10; /* 0x110 Channel 10 Priority Register */
u8 dchpri11; /* 0x111 Channel 11 Priority Register */
u8 dchpri12; /* 0x112 Channel 12 Priority Register */
u8 dchpri13; /* 0x113 Channel 13 Priority Register */
u8 dchpri14; /* 0x114 Channel 14 Priority Register */
u8 dchpri15; /* 0x115 Channel 15 Priority Register */
} edma_t;
/* TCD - eDMA*/
typedef struct tcd_ctrl {
u32 saddr; /* 0x00 Source Address */
u16 attr; /* 0x04 Transfer Attributes */
u16 soff; /* 0x06 Signed Source Address Offset */
u32 nbytes; /* 0x08 Minor Byte Count */
u32 slast; /* 0x0C Last Source Address Adjustment */
u32 daddr; /* 0x10 Destination address */
u16 citer; /* 0x14 Current Minor Loop Link, Major Loop Count */
u16 doff; /* 0x16 Signed Destination Address Offset */
u32 dlast_sga; /* 0x18 Last Destination Address Adjustment/Scatter Gather Address */
u16 biter; /* 0x1C Beginning Minor Loop Link, Major Loop Count */
u16 csr; /* 0x1E Control and Status */
} tcd_st;
typedef struct tcd_multiple {
tcd_st tcd[16];
} tcd_t;
/* Interrupt module registers */
typedef struct int0_ctrl {
/* Interrupt Controller 0 */
@ -389,20 +282,6 @@ typedef struct intgack_ctrl1 {
u8 Lniack[7]; /* 0xE1 - 0xE7 Global Level 0 Interrupt Acknowledge */
} intgack_t;
/*I2C module registers */
typedef struct i2c_ctrl {
u8 adr; /* 0x00 address register */
u8 res1[3]; /* 0x01 - 0x03 */
u8 fdr; /* 0x04 frequency divider register */
u8 res2[3]; /* 0x05 - 0x07 */
u8 cr; /* 0x08 control register */
u8 res3[3]; /* 0x09 - 0x0B */
u8 sr; /* 0x0C status register */
u8 res4[3]; /* 0x0D - 0x0F */
u8 dr; /* 0x10 data register */
u8 res5[3]; /* 0x11 - 0x13 */
} i2c_t;
/* QSPI module registers */
typedef struct qspi_ctrl {
u16 qmr; /* Mode register */
@ -617,43 +496,6 @@ typedef struct gpio_ctrl {
u8 dscr_irq; /* 0x72 */
} gpio_t;
/* LCD module registers */
typedef struct lcd_ctrl {
u32 ssar; /* 0x00 Screen Start Address Register */
u32 sr; /* 0x04 LCD Size Register */
u32 vpw; /* 0x08 Virtual Page Width Register */
u32 cpr; /* 0x0C Cursor Position Register */
u32 cwhb; /* 0x10 Cursor Width Height and Blink Register */
u32 ccmr; /* 0x14 Color Cursor Mapping Register */
u32 pcr; /* 0x18 Panel Configuration Register */
u32 hcr; /* 0x1C Horizontal Configuration Register */
u32 vcr; /* 0x20 Vertical Configuration Register */
u32 por; /* 0x24 Panning Offset Register */
u32 scr; /* 0x28 Sharp Configuration Register */
u32 pccr; /* 0x2C PWM Contrast Control Register */
u32 dcr; /* 0x30 DMA Control Register */
u32 rmcr; /* 0x34 Refresh Mode Control Register */
u32 icr; /* 0x38 Refresh Mode Control Register */
u32 ier; /* 0x3C Interrupt Enable Register */
u32 isr; /* 0x40 Interrupt Status Register */
u32 res[4];
u32 gwsar; /* 0x50 Graphic Window Start Address Register */
u32 gwsr; /* 0x54 Graphic Window Size Register */
u32 gwvpw; /* 0x58 Graphic Window Virtual Page Width Register */
u32 gwpor; /* 0x5C Graphic Window Panning Offset Register */
u32 gwpr; /* 0x60 Graphic Window Position Register */
u32 gwcr; /* 0x64 Graphic Window Control Register */
u32 gwdcr; /* 0x68 Graphic Window DMA Control Register */
} lcd_t;
typedef struct lcdbg_ctrl {
u32 bglut[255];
} lcdbg_t;
typedef struct lcdgw_ctrl {
u32 gwlut[255];
} lcdgw_t;
/* USB OTG module registers */
typedef struct usb_otg {
u32 id; /* 0x000 Identification Register */
@ -758,29 +600,6 @@ typedef struct sdram_ctrl {
u32 cs1; /* 0x114 Chip Select 1 Configuration */
} sdram_t;
/* Synchronous serial interface */
typedef struct ssi_ctrl {
u32 tx0; /* 0x00 Transmit Data Register 0 */
u32 tx1; /* 0x04 Transmit Data Register 1 */
u32 rx0; /* 0x08 Receive Data Register 0 */
u32 rx1; /* 0x0C Receive Data Register 1 */
u32 cr; /* 0x10 Control Register */
u32 isr; /* 0x14 Interrupt Status Register */
u32 ier; /* 0x18 Interrupt Enable Register */
u32 tcr; /* 0x1C Transmit Configuration Register */
u32 rcr; /* 0x20 Receive Configuration Register */
u32 ccr; /* 0x24 Clock Control Register */
u32 res1; /* 0x28 */
u32 fcsr; /* 0x2C FIFO Control/Status Register */
u32 res2[2]; /* 0x30 - 0x37 */
u32 acr; /* 0x38 AC97 Control Register */
u32 acadd; /* 0x3C AC97 Command Address Register */
u32 acdat; /* 0x40 AC97 Command Data Register */
u32 atag; /* 0x44 AC97 Tag Register */
u32 tmask; /* 0x48 Transmit Time Slot Mask Register */
u32 rmask; /* 0x4C Receive Time Slot Mask Register */
} ssi_t;
/* Clock Module registers */
typedef struct pll_ctrl {
u8 podr; /* 0x00 Output Divider Register */

281
include/asm-m68k/m5329.h
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@ -1315,168 +1315,6 @@
/* Bit definitions and macros for GPIO_DSCR_IRQ */
#define GPIO_DSCR_IRQ_DSE(x) ((x)&0x03)
/* not done yet */
/*********************************************************************
* LCD Controller (LCDC)
*********************************************************************/
/* Bit definitions and macros for LCDC_LSSAR */
#define LCDC_LSSAR_SSA(x) (((x)&0x3FFFFFFF)<<2)
/* Bit definitions and macros for LCDC_LSR */
#define LCDC_LSR_YMAX(x) (((x)&0x000003FF)<<0)
#define LCDC_LSR_XMAX(x) (((x)&0x0000003F)<<20)
/* Bit definitions and macros for LCDC_LVPWR */
#define LCDC_LVPWR_VPW(x) (((x)&0x000003FF)<<0)
/* Bit definitions and macros for LCDC_LCPR */
#define LCDC_LCPR_CYP(x) (((x)&0x000003FF)<<0)
#define LCDC_LCPR_CXP(x) (((x)&0x000003FF)<<16)
#define LCDC_LCPR_OP (0x10000000)
#define LCDC_LCPR_CC(x) (((x)&0x00000003)<<30)
#define LCDC_LCPR_CC_TRANSPARENT (0x00000000)
#define LCDC_LCPR_CC_OR (0x40000000)
#define LCDC_LCPR_CC_XOR (0x80000000)
#define LCDC_LCPR_CC_AND (0xC0000000)
#define LCDC_LCPR_OP_ON (0x10000000)
#define LCDC_LCPR_OP_OFF (0x00000000)
/* Bit definitions and macros for LCDC_LCWHBR */
#define LCDC_LCWHBR_BD(x) (((x)&0x000000FF)<<0)
#define LCDC_LCWHBR_CH(x) (((x)&0x0000001F)<<16)
#define LCDC_LCWHBR_CW(x) (((x)&0x0000001F)<<24)
#define LCDC_LCWHBR_BK_EN (0x80000000)
#define LCDC_LCWHBR_BK_EN_ON (0x80000000)
#define LCDC_LCWHBR_BK_EN_OFF (0x00000000)
/* Bit definitions and macros for LCDC_LCCMR */
#define LCDC_LCCMR_CUR_COL_B(x) (((x)&0x0000003F)<<0)
#define LCDC_LCCMR_CUR_COL_G(x) (((x)&0x0000003F)<<6)
#define LCDC_LCCMR_CUR_COL_R(x) (((x)&0x0000003F)<<12)
/* Bit definitions and macros for LCDC_LPCR */
#define LCDC_LPCR_PCD(x) (((x)&0x0000003F)<<0)
#define LCDC_LPCR_SHARP (0x00000040)
#define LCDC_LPCR_SCLKSEL (0x00000080)
#define LCDC_LPCR_ACD(x) (((x)&0x0000007F)<<8)
#define LCDC_LPCR_ACDSEL (0x00008000)
#define LCDC_LPCR_REV_VS (0x00010000)
#define LCDC_LPCR_SWAP_SEL (0x00020000)
#define LCDC_LPCR_ENDSEL (0x00040000)
#define LCDC_LPCR_SCLKIDLE (0x00080000)
#define LCDC_LPCR_OEPOL (0x00100000)
#define LCDC_LPCR_CLKPOL (0x00200000)
#define LCDC_LPCR_LPPOL (0x00400000)
#define LCDC_LPCR_FLM (0x00800000)
#define LCDC_LPCR_PIXPOL (0x01000000)
#define LCDC_LPCR_BPIX(x) (((x)&0x00000007)<<25)
#define LCDC_LPCR_PBSIZ(x) (((x)&0x00000003)<<28)
#define LCDC_LPCR_COLOR (0x40000000)
#define LCDC_LPCR_TFT (0x80000000)
#define LCDC_LPCR_MODE_MONOCHROME (0x00000000)
#define LCDC_LPCR_MODE_CSTN (0x40000000)
#define LCDC_LPCR_MODE_TFT (0xC0000000)
#define LCDC_LPCR_PBSIZ_1 (0x00000000)
#define LCDC_LPCR_PBSIZ_2 (0x10000000)
#define LCDC_LPCR_PBSIZ_4 (0x20000000)
#define LCDC_LPCR_PBSIZ_8 (0x30000000)
#define LCDC_LPCR_BPIX_1bpp (0x00000000)
#define LCDC_LPCR_BPIX_2bpp (0x02000000)
#define LCDC_LPCR_BPIX_4bpp (0x04000000)
#define LCDC_LPCR_BPIX_8bpp (0x06000000)
#define LCDC_LPCR_BPIX_12bpp (0x08000000)
#define LCDC_LPCR_BPIX_16bpp (0x0A000000)
#define LCDC_LPCR_BPIX_18bpp (0x0C000000)
#define LCDC_LPCR_PANEL_TYPE(x) (((x)&0x00000003)<<30)
/* Bit definitions and macros for LCDC_LHCR */
#define LCDC_LHCR_H_WAIT_2(x) (((x)&0x000000FF)<<0)
#define LCDC_LHCR_H_WAIT_1(x) (((x)&0x000000FF)<<8)
#define LCDC_LHCR_H_WIDTH(x) (((x)&0x0000003F)<<26)
/* Bit definitions and macros for LCDC_LVCR */
#define LCDC_LVCR_V_WAIT_2(x) (((x)&0x000000FF)<<0)
#define LCDC_LVCR_V_WAIT_1(x) (((x)&0x000000FF)<<8)
#define LCDC_LVCR_V_WIDTH(x) (((x)&0x0000003F)<<26)
/* Bit definitions and macros for LCDC_LPOR */
#define LCDC_LPOR_POS(x) (((x)&0x0000001F)<<0)
/* Bit definitions and macros for LCDC_LPCCR */
#define LCDC_LPCCR_PW(x) (((x)&0x000000FF)<<0)
#define LCDC_LPCCR_CC_EN (0x00000100)
#define LCDC_LPCCR_SCR(x) (((x)&0x00000003)<<9)
#define LCDC_LPCCR_LDMSK (0x00008000)
#define LCDC_LPCCR_CLS_HI_WIDTH(x) (((x)&0x000001FF)<<16)
#define LCDC_LPCCR_SCR_LINEPULSE (0x00000000)
#define LCDC_LPCCR_SCR_PIXELCLK (0x00002000)
#define LCDC_LPCCR_SCR_LCDCLOCK (0x00004000)
/* Bit definitions and macros for LCDC_LDCR */
#define LCDC_LDCR_TM(x) (((x)&0x0000001F)<<0)
#define LCDC_LDCR_HM(x) (((x)&0x0000001F)<<16)
#define LCDC_LDCR_BURST (0x80000000)
/* Bit definitions and macros for LCDC_LRMCR */
#define LCDC_LRMCR_SEL_REF (0x00000001)
/* Bit definitions and macros for LCDC_LICR */
#define LCDC_LICR_INTCON (0x00000001)
#define LCDC_LICR_INTSYN (0x00000004)
#define LCDC_LICR_GW_INT_CON (0x00000010)
/* Bit definitions and macros for LCDC_LIER */
#define LCDC_LIER_BOF_EN (0x00000001)
#define LCDC_LIER_EOF_EN (0x00000002)
#define LCDC_LIER_ERR_RES_EN (0x00000004)
#define LCDC_LIER_UDR_ERR_EN (0x00000008)
#define LCDC_LIER_GW_BOF_EN (0x00000010)
#define LCDC_LIER_GW_EOF_EN (0x00000020)
#define LCDC_LIER_GW_ERR_RES_EN (0x00000040)
#define LCDC_LIER_GW_UDR_ERR_EN (0x00000080)
/* Bit definitions and macros for LCDC_LISR */
#define LCDC_LISR_BOF (0x00000001)
#define LCDC_LISR_EOF (0x00000002)
#define LCDC_LISR_ERR_RES (0x00000004)
#define LCDC_LISR_UDR_ERR (0x00000008)
#define LCDC_LISR_GW_BOF (0x00000010)
#define LCDC_LISR_GW_EOF (0x00000020)
#define LCDC_LISR_GW_ERR_RES (0x00000040)
#define LCDC_LISR_GW_UDR_ERR (0x00000080)
/* Bit definitions and macros for LCDC_LGWSAR */
#define LCDC_LGWSAR_GWSA(x) (((x)&0x3FFFFFFF)<<2)
/* Bit definitions and macros for LCDC_LGWSR */
#define LCDC_LGWSR_GWH(x) (((x)&0x000003FF)<<0)
#define LCDC_LGWSR_GWW(x) (((x)&0x0000003F)<<20)
/* Bit definitions and macros for LCDC_LGWVPWR */
#define LCDC_LGWVPWR_GWVPW(x) (((x)&0x000003FF)<<0)
/* Bit definitions and macros for LCDC_LGWPOR */
#define LCDC_LGWPOR_GWPO(x) (((x)&0x0000001F)<<0)
/* Bit definitions and macros for LCDC_LGWPR */
#define LCDC_LGWPR_GWYP(x) (((x)&0x000003FF)<<0)
#define LCDC_LGWPR_GWXP(x) (((x)&0x000003FF)<<16)
/* Bit definitions and macros for LCDC_LGWCR */
#define LCDC_LGWCR_GWCKB(x) (((x)&0x0000003F)<<0)
#define LCDC_LGWCR_GWCKG(x) (((x)&0x0000003F)<<6)
#define LCDC_LGWCR_GWCKR(x) (((x)&0x0000003F)<<12)
#define LCDC_LGWCR_GW_RVS (0x00200000)
#define LCDC_LGWCR_GWE (0x00400000)
#define LCDC_LGWCR_GWCKE (0x00800000)
#define LCDC_LGWCR_GWAV(x) (((x)&0x000000FF)<<24)
/* Bit definitions and macros for LCDC_LGWDCR */
#define LCDC_LGWDCR_GWTM(x) (((x)&0x0000001F)<<0)
#define LCDC_LGWDCR_GWHM(x) (((x)&0x0000001F)<<16)
#define LCDC_LGWDCR_GWBT (0x80000000)
/*********************************************************************
* SDRAM Controller (SDRAMC)
*********************************************************************/
@ -1541,125 +1379,6 @@
#define SDRAMC_SDCS_CSSZ_DIABLE (0x00000000)
/*********************************************************************
* Synchronous Serial Interface (SSI)
*********************************************************************/
/* Bit definitions and macros for SSI_CR */
#define SSI_CR_CIS (0x00000200)
#define SSI_CR_TCH (0x00000100)
#define SSI_CR_MCE (0x00000080)
#define SSI_CR_I2S_SLAVE (0x00000040)
#define SSI_CR_I2S_MASTER (0x00000020)
#define SSI_CR_I2S_NORMAL (0x00000000)
#define SSI_CR_SYN (0x00000010)
#define SSI_CR_NET (0x00000008)
#define SSI_CR_RE (0x00000004)
#define SSI_CR_TE (0x00000002)
#define SSI_CR_SSI_EN (0x00000001)
/* Bit definitions and macros for SSI_ISR */
#define SSI_ISR_CMDAU (0x00040000)
#define SSI_ISR_CMDDU (0x00020000)
#define SSI_ISR_RXT (0x00010000)
#define SSI_ISR_RDR1 (0x00008000)
#define SSI_ISR_RDR0 (0x00004000)
#define SSI_ISR_TDE1 (0x00002000)
#define SSI_ISR_TDE0 (0x00001000)
#define SSI_ISR_ROE1 (0x00000800)
#define SSI_ISR_ROE0 (0x00000400)
#define SSI_ISR_TUE1 (0x00000200)
#define SSI_ISR_TUE0 (0x00000100)
#define SSI_ISR_TFS (0x00000080)
#define SSI_ISR_RFS (0x00000040)
#define SSI_ISR_TLS (0x00000020)
#define SSI_ISR_RLS (0x00000010)
#define SSI_ISR_RFF1 (0x00000008)
#define SSI_ISR_RFF0 (0x00000004)
#define SSI_ISR_TFE1 (0x00000002)
#define SSI_ISR_TFE0 (0x00000001)
/* Bit definitions and macros for SSI_IER */
#define SSI_IER_RDMAE (0x00400000)
#define SSI_IER_RIE (0x00200000)
#define SSI_IER_TDMAE (0x00100000)
#define SSI_IER_TIE (0x00080000)
#define SSI_IER_CMDAU (0x00040000)
#define SSI_IER_CMDU (0x00020000)
#define SSI_IER_RXT (0x00010000)
#define SSI_IER_RDR1 (0x00008000)
#define SSI_IER_RDR0 (0x00004000)
#define SSI_IER_TDE1 (0x00002000)
#define SSI_IER_TDE0 (0x00001000)
#define SSI_IER_ROE1 (0x00000800)
#define SSI_IER_ROE0 (0x00000400)
#define SSI_IER_TUE1 (0x00000200)
#define SSI_IER_TUE0 (0x00000100)
#define SSI_IER_TFS (0x00000080)
#define SSI_IER_RFS (0x00000040)
#define SSI_IER_TLS (0x00000020)
#define SSI_IER_RLS (0x00000010)
#define SSI_IER_RFF1 (0x00000008)
#define SSI_IER_RFF0 (0x00000004)
#define SSI_IER_TFE1 (0x00000002)
#define SSI_IER_TFE0 (0x00000001)
/* Bit definitions and macros for SSI_TCR */
#define SSI_TCR_TXBIT0 (0x00000200)
#define SSI_TCR_TFEN1 (0x00000100)
#define SSI_TCR_TFEN0 (0x00000080)
#define SSI_TCR_TFDIR (0x00000040)
#define SSI_TCR_TXDIR (0x00000020)
#define SSI_TCR_TSHFD (0x00000010)
#define SSI_TCR_TSCKP (0x00000008)
#define SSI_TCR_TFSI (0x00000004)
#define SSI_TCR_TFSL (0x00000002)
#define SSI_TCR_TEFS (0x00000001)
/* Bit definitions and macros for SSI_RCR */
#define SSI_RCR_RXEXT (0x00000400)
#define SSI_RCR_RXBIT0 (0x00000200)
#define SSI_RCR_RFEN1 (0x00000100)
#define SSI_RCR_RFEN0 (0x00000080)
#define SSI_RCR_RSHFD (0x00000010)
#define SSI_RCR_RSCKP (0x00000008)
#define SSI_RCR_RFSI (0x00000004)
#define SSI_RCR_RFSL (0x00000002)
#define SSI_RCR_REFS (0x00000001)
/* Bit definitions and macros for SSI_CCR */
#define SSI_CCR_DIV2 (0x00040000)
#define SSI_CCR_PSR (0x00020000)
#define SSI_CCR_WL(x) (((x)&0x0000000F)<<13)
#define SSI_CCR_DC(x) (((x)&0x0000001F)<<8)
#define SSI_CCR_PM(x) ((x)&0x000000FF)
/* Bit definitions and macros for SSI_FCSR */
#define SSI_FCSR_RFCNT1(x) (((x)&0x0000000F)<<28)
#define SSI_FCSR_TFCNT1(x) (((x)&0x0000000F)<<24)
#define SSI_FCSR_RFWM1(x) (((x)&0x0000000F)<<20)
#define SSI_FCSR_TFWM1(x) (((x)&0x0000000F)<<16)
#define SSI_FCSR_RFCNT0(x) (((x)&0x0000000F)<<12)
#define SSI_FCSR_TFCNT0(x) (((x)&0x0000000F)<<8)
#define SSI_FCSR_RFWM0(x) (((x)&0x0000000F)<<4)
#define SSI_FCSR_TFWM0(x) ((x)&0x0000000F)
/* Bit definitions and macros for SSI_ACR */
#define SSI_ACR_FRDIV(x) (((x)&0x0000003F)<<5)
#define SSI_ACR_WR (0x00000010)
#define SSI_ACR_RD (0x00000008)
#define SSI_ACR_TIF (0x00000004)
#define SSI_ACR_FV (0x00000002)
#define SSI_ACR_AC97EN (0x00000001)
/* Bit definitions and macros for SSI_ACADD */
#define SSI_ACADD_SSI_ACADD(x) ((x)&0x0007FFFF)
/* Bit definitions and macros for SSI_ACDAT */
#define SSI_ACDAT_SSI_ACDAT(x) ((x)&0x0007FFFF)
/* Bit definitions and macros for SSI_ATAG */
#define SSI_ATAG_DDI_ATAG(x) ((x)&0x0000FFFF)
/*********************************************************************
* Phase Locked Loop (PLL)
*********************************************************************/
/* Bit definitions and macros for PLL_PODR */

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