Implemented support for MPC8548CDS board.
Added DDR II support based on SPD values for MPC85xx boards.
This roll-up patch also includes bugfies for the previously
published patches:
DDRII CPO, pre eTSEC, 8548 LBIU, Andy's TSEC, eTSEC 3&4 I/O
master
Jon Loeliger
20 years ago
parent
288693abe1
commit
d9b94f28a4
@ -0,0 +1,51 @@ |
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#
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# Copyright 2004 Freescale Semiconductor.
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# (C) Copyright 2001
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
|
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# modify it under the terms of the GNU General Public License as
|
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# published by the Free Software Foundation; either version 2 of
|
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# the License, or (at your option) any later version.
|
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#
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# This program is distributed in the hope that it will be useful,
|
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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# GNU General Public License for more details.
|
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#
|
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# You should have received a copy of the GNU General Public License
|
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# along with this program; if not, write to the Free Software
|
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk |
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LIB = lib$(BOARD).a
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OBJS := $(BOARD).o \
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../common/cadmus.o \
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../common/eeprom.o
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SOBJS := init.o
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$(LIB): $(OBJS) $(SOBJS) |
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$(AR) crv $@ $(OBJS)
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clean: |
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rm -f $(OBJS) $(SOBJS)
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distclean: clean |
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rm -f $(LIB) core *.bak .depend
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#########################################################################
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.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) |
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$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
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-include .depend |
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#########################################################################
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@ -0,0 +1,30 @@ |
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#
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# Copyright 2004 Freescale Semiconductor.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
|
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# modify it under the terms of the GNU General Public License as
|
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# published by the Free Software Foundation; either version 2 of
|
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# the License, or (at your option) any later version.
|
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#
|
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# This program is distributed in the hope that it will be useful,
|
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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# GNU General Public License for more details.
|
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#
|
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# You should have received a copy of the GNU General Public License
|
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# along with this program; if not, write to the Free Software
|
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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#
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# mpc8548cds board
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#
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TEXT_BASE = 0xfff80000
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PLATFORM_CPPFLAGS += -DCONFIG_E500=1
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PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1
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PLATFORM_CPPFLAGS += -DCONFIG_MPC8548=1
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@ -0,0 +1,255 @@ |
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/* |
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* Copyright 2004 Freescale Semiconductor. |
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* Copyright 2002,2003, Motorola Inc. |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or
|
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of
|
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <ppc_asm.tmpl> |
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#include <ppc_defs.h> |
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#include <asm/cache.h> |
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#include <asm/mmu.h> |
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#include <config.h> |
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#include <mpc85xx.h> |
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/* |
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* TLB0 and TLB1 Entries |
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* |
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* Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR. |
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* However, CCSRBAR is then relocated to CFG_CCSRBAR right after |
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* these TLB entries are established. |
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* |
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* The TLB entries for DDR are dynamically setup in spd_sdram() |
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* and use TLB1 Entries 8 through 15 as needed according to the |
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* size of DDR memory. |
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* |
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* MAS0: tlbsel, esel, nv |
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* MAS1: valid, iprot, tid, ts, tsize |
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* MAS2: epn, sharen, x0, x1, w, i, m, g, e |
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* MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr |
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*/ |
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#define entry_start \ |
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mflr r1 ; \
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bl 0f ;
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#define entry_end \ |
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0: mflr r0 ; \
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mtlr r1 ; \
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blr ;
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.section .bootpg, "ax" |
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.globl tlb1_entry
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tlb1_entry: |
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entry_start |
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/* |
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* Number of TLB0 and TLB1 entries in the following table |
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*/ |
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.long 13
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#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) |
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/* |
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* TLB0 4K Non-cacheable, guarded |
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* 0xff700000 4K Initial CCSRBAR mapping |
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* |
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* This ends up at a TLB0 Index==0 entry, and must not collide |
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* with other TLB0 Entries. |
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*/ |
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.long TLB1_MAS0(0, 0, 0) |
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.long TLB1_MAS1(1, 0, 0, 0, 0) |
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.long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0) |
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.long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1) |
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#else |
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#error("Update the number of table entries in tlb1_entry") |
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#endif |
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/* |
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* TLB0 16K Cacheable, non-guarded |
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* 0xd001_0000 16K Temporary Global data for initialization |
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* |
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* Use four 4K TLB0 entries. These entries must be cacheable |
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* as they provide the bootstrap memory before the memory |
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* controler and real memory have been configured. |
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* |
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* These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c, |
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* and must not collide with other TLB0 entries. |
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*/ |
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.long TLB1_MAS0(0, 0, 0) |
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.long TLB1_MAS1(1, 0, 0, 0, 0) |
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.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR), |
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0,0,0,0,0,0,0,0) |
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.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR), |
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0,0,0,0,0,1,0,1,0,1) |
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.long TLB1_MAS0(0, 0, 0) |
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.long TLB1_MAS1(1, 0, 0, 0, 0) |
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.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024), |
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0,0,0,0,0,0,0,0) |
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.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024), |
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0,0,0,0,0,1,0,1,0,1) |
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.long TLB1_MAS0(0, 0, 0) |
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.long TLB1_MAS1(1, 0, 0, 0, 0) |
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.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024), |
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0,0,0,0,0,0,0,0) |
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.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024), |
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0,0,0,0,0,1,0,1,0,1) |
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.long TLB1_MAS0(0, 0, 0) |
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.long TLB1_MAS1(1, 0, 0, 0, 0) |
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.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024), |
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0,0,0,0,0,0,0,0) |
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.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024), |
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0,0,0,0,0,1,0,1,0,1) |
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/* |
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* TLB 0: 16M Non-cacheable, guarded |
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* 0xff000000 16M FLASH |
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* Out of reset this entry is only 4K. |
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*/ |
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.long TLB1_MAS0(1, 0, 0) |
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.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M) |
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.long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0) |
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.long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1) |
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/* |
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* TLB 1: 256M Non-cacheable, guarded |
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* 0x80000000 256M PCI1 MEM First half |
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*/ |
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.long TLB1_MAS0(1, 1, 0) |
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.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) |
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.long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0) |
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.long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1) |
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/* |
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* TLB 2: 256M Non-cacheable, guarded |
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* 0x90000000 256M PCI1 MEM Second half |
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*/ |
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.long TLB1_MAS0(1, 2, 0) |
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.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) |
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.long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + 0x10000000), |
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0,0,0,0,1,0,1,0) |
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.long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + 0x10000000), |
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0,0,0,0,0,1,0,1,0,1) |
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/* |
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* TLB 3: 256M Non-cacheable, guarded |
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* 0xa0000000 256M PCI2 MEM First half |
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*/ |
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.long TLB1_MAS0(1, 3, 0) |
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.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) |
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.long TLB1_MAS2(E500_TLB_EPN(CFG_PCI2_MEM_BASE), 0,0,0,0,1,0,1,0) |
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.long TLB1_MAS3(E500_TLB_RPN(CFG_PCI2_MEM_BASE), 0,0,0,0,0,1,0,1,0,1) |
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/* |
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* TLB 4: 256M Non-cacheable, guarded |
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* 0xb0000000 256M PCI2 MEM Second half |
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*/ |
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.long TLB1_MAS0(1, 4, 0) |
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.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) |
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.long TLB1_MAS2(E500_TLB_EPN(CFG_PCI2_MEM_BASE + 0x10000000), |
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0,0,0,0,1,0,1,0) |
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.long TLB1_MAS3(E500_TLB_RPN(CFG_PCI2_MEM_BASE + 0x10000000), |
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0,0,0,0,0,1,0,1,0,1) |
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/* |
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* TLB 5: 64M Non-cacheable, guarded |
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* 0xe000_0000 1M CCSRBAR |
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* 0xe200_0000 16M PCI1 IO |
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* 0xe300_0000 16M PCI2 IO |
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*/ |
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.long TLB1_MAS0(1, 5, 0) |
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.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) |
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.long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0) |
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.long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1) |
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/* |
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* TLB 6: 64M Cacheable, non-guarded |
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* 0xf000_0000 64M LBC SDRAM |
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*/ |
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.long TLB1_MAS0(1, 6, 0) |
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.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) |
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.long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,0,0,0) |
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.long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1) |
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/* |
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* TLB 7: 1M Non-cacheable, guarded |
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* 0xf8000000 1M CADMUS registers |
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*/ |
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.long TLB1_MAS0(1, 7, 0) |
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.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M) |
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.long TLB1_MAS2(E500_TLB_EPN(CADMUS_BASE_ADDR), 0,0,0,0,1,0,1,0) |
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.long TLB1_MAS3(E500_TLB_RPN(CADMUS_BASE_ADDR), 0,0,0,0,0,1,0,1,0,1) |
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entry_end |
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/* |
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* LAW(Local Access Window) configuration: |
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* |
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* 0x0000_0000 0x7fff_ffff DDR 2G |
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* 0x8000_0000 0x9fff_ffff PCI1 MEM 512M |
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* 0xa000_0000 0xbfff_ffff PCI2 MEM 512M |
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* 0xe000_0000 0xe000_ffff CCSR 1M |
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* 0xe200_0000 0xe2ff_ffff PCI1 IO 16M |
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* 0xe300_0000 0xe3ff_ffff PCI2 IO 16M |
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* 0xf000_0000 0xf7ff_ffff SDRAM 128M |
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* 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M |
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* 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M |
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* 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M |
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* |
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* Notes: |
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* CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. |
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* If flash is 8M at default position (last 8M), no LAW needed. |
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* |
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* The defines below are 1-off of the actual LAWAR0 usage. |
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* So LAWAR3 define uses the LAWAR4 register in the ECM. |
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*/ |
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#define LAWBAR0 0 |
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#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN) |
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#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff) |
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#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M)) |
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|
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#define LAWBAR2 ((CFG_PCI2_MEM_BASE>>12) & 0xfffff) |
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#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M)) |
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|
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#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff) |
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#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_16M)) |
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|
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#define LAWBAR4 ((CFG_PCI2_IO_BASE>>12) & 0xfffff) |
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#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_16M)) |
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|
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/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */ |
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#define LAWBAR5 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff) |
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#define LAWAR5 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)) |
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.section .bootpg, "ax" |
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.globl law_entry
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law_entry: |
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entry_start |
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.long 6
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.long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3 |
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.long LAWBAR4,LAWAR4,LAWBAR5,LAWAR5 |
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entry_end |
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@ -0,0 +1,329 @@ |
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/*
|
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* Copyright 2004 Freescale Semiconductor. |
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* |
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* (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com> |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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|
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#include <common.h> |
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#include <pci.h> |
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#include <asm/processor.h> |
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#include <asm/immap_85xx.h> |
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#include <spd.h> |
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|
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#include "../common/cadmus.h" |
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#include "../common/eeprom.h" |
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|
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#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) |
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extern void ddr_enable_ecc(unsigned int dram_size); |
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#endif |
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|
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extern long int spd_sdram(void); |
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|
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void local_bus_init(void); |
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void sdram_init(void); |
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|
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int board_early_init_f (void) |
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{ |
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return 0; |
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} |
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|
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int checkboard (void) |
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{ |
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volatile immap_t *immap = (immap_t *) CFG_CCSRBAR; |
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volatile ccsr_gur_t *gur = &immap->im_gur; |
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|
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/* PCI slot in USER bits CSR[6:7] by convention. */ |
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uint pci_slot = get_pci_slot (); |
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|
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uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */ |
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uint pci1_32 = gur->pordevsr & 0x10000; /* PORDEVSR[15] */ |
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uint pci1_clk_sel = gur->porpllsr & 0x8000; /* PORPLLSR[16] */ |
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uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */ |
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|
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uint pci1_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */ |
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|
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uint cpu_board_rev = get_cpu_board_revision (); |
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|
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printf ("Board: CDS Version 0x%02x, PCI Slot %d\n", |
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get_board_version (), pci_slot); |
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|
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printf ("CPU Board Revision %d.%d (0x%04x)\n", |
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MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev), |
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MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev); |
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|
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printf (" PCI1: %d bit, %s MHz, %s\n", |
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(pci1_32) ? 32 : 64, |
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(pci1_speed == 33000000) ? "33" : |
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(pci1_speed == 66000000) ? "66" : "unknown", |
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pci1_clk_sel ? "sync" : "async"); |
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|
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if (pci_dual) { |
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printf (" PCI2: 32 bit, 66 MHz, %s\n", |
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pci2_clk_sel ? "sync" : "async"); |
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} else { |
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printf (" PCI2: disabled\n"); |
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} |
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|
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/*
|
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* Initialize local bus. |
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*/ |
||||
local_bus_init (); |
||||
|
||||
|
||||
/*
|
||||
* Hack TSEC 3 and 4 IO voltages. |
||||
*/ |
||||
gur->tsec34ioovcr = 0xe7e0; /* 1110 0111 1110 0xxx */ |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
long int |
||||
initdram(int board_type) |
||||
{ |
||||
long dram_size = 0; |
||||
volatile immap_t *immap = (immap_t *)CFG_IMMR; |
||||
|
||||
puts("Initializing\n"); |
||||
|
||||
#if defined(CONFIG_DDR_DLL) |
||||
{ |
||||
/*
|
||||
* Work around to stabilize DDR DLL MSYNC_IN. |
||||
* Errata DDR9 seems to have been fixed. |
||||
* This is now the workaround for Errata DDR11: |
||||
* Override DLL = 1, Course Adj = 1, Tap Select = 0 |
||||
*/ |
||||
|
||||
volatile ccsr_gur_t *gur= &immap->im_gur; |
||||
|
||||
gur->ddrdllcr = 0x81000000; |
||||
asm("sync;isync;msync"); |
||||
udelay(200); |
||||
} |
||||
#endif |
||||
dram_size = spd_sdram(); |
||||
|
||||
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) |
||||
/*
|
||||
* Initialize and enable DDR ECC. |
||||
*/ |
||||
ddr_enable_ecc(dram_size); |
||||
#endif |
||||
/*
|
||||
* SDRAM Initialization |
||||
*/ |
||||
sdram_init(); |
||||
|
||||
puts(" DDR: "); |
||||
return dram_size; |
||||
} |
||||
|
||||
/*
|
||||
* Initialize Local Bus |
||||
*/ |
||||
void |
||||
local_bus_init(void) |
||||
{ |
||||
volatile immap_t *immap = (immap_t *)CFG_IMMR; |
||||
volatile ccsr_gur_t *gur = &immap->im_gur; |
||||
volatile ccsr_lbc_t *lbc = &immap->im_lbc; |
||||
|
||||
uint clkdiv; |
||||
uint lbc_hz; |
||||
sys_info_t sysinfo; |
||||
|
||||
get_sys_info(&sysinfo); |
||||
clkdiv = (lbc->lcrr & 0x0f) * 2; |
||||
lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; |
||||
|
||||
gur->lbiuiplldcr1 = 0x00078080; |
||||
if (clkdiv == 16) { |
||||
gur->lbiuiplldcr0 = 0x7c0f1bf0; |
||||
} else if (clkdiv == 8) { |
||||
gur->lbiuiplldcr0 = 0x6c0f1bf0; |
||||
} else if (clkdiv == 4) { |
||||
gur->lbiuiplldcr0 = 0x5c0f1bf0; |
||||
} |
||||
|
||||
lbc->lcrr |= 0x00030000; |
||||
|
||||
asm("sync;isync;msync"); |
||||
} |
||||
|
||||
/*
|
||||
* Initialize SDRAM memory on the Local Bus. |
||||
*/ |
||||
void |
||||
sdram_init(void) |
||||
{ |
||||
#if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM) |
||||
|
||||
uint idx; |
||||
volatile immap_t *immap = (immap_t *)CFG_IMMR; |
||||
volatile ccsr_lbc_t *lbc = &immap->im_lbc; |
||||
uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE; |
||||
uint cpu_board_rev; |
||||
uint lsdmr_common; |
||||
|
||||
puts(" SDRAM: "); |
||||
|
||||
print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); |
||||
|
||||
/*
|
||||
* Setup SDRAM Base and Option Registers |
||||
*/ |
||||
lbc->or2 = CFG_OR2_PRELIM; |
||||
asm("msync"); |
||||
|
||||
lbc->br2 = CFG_BR2_PRELIM; |
||||
asm("msync"); |
||||
|
||||
lbc->lbcr = CFG_LBC_LBCR; |
||||
asm("msync"); |
||||
|
||||
|
||||
lbc->lsrt = CFG_LBC_LSRT; |
||||
lbc->mrtpr = CFG_LBC_MRTPR; |
||||
asm("msync"); |
||||
|
||||
/*
|
||||
* MPC8548 uses "new" 15-16 style addressing. |
||||
*/ |
||||
cpu_board_rev = get_cpu_board_revision(); |
||||
lsdmr_common = CFG_LBC_LSDMR_COMMON; |
||||
lsdmr_common |= CFG_LBC_LSDMR_BSMA1516; |
||||
|
||||
/*
|
||||
* Issue PRECHARGE ALL command. |
||||
*/ |
||||
lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_PCHALL; |
||||
asm("sync;msync"); |
||||
*sdram_addr = 0xff; |
||||
ppcDcbf((unsigned long) sdram_addr); |
||||
udelay(100); |
||||
|
||||
/*
|
||||
* Issue 8 AUTO REFRESH commands. |
||||
*/ |
||||
for (idx = 0; idx < 8; idx++) { |
||||
lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_ARFRSH; |
||||
asm("sync;msync"); |
||||
*sdram_addr = 0xff; |
||||
ppcDcbf((unsigned long) sdram_addr); |
||||
udelay(100); |
||||
} |
||||
|
||||
/*
|
||||
* Issue 8 MODE-set command. |
||||
*/ |
||||
lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_MRW; |
||||
asm("sync;msync"); |
||||
*sdram_addr = 0xff; |
||||
ppcDcbf((unsigned long) sdram_addr); |
||||
udelay(100); |
||||
|
||||
/*
|
||||
* Issue NORMAL OP command. |
||||
*/ |
||||
lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_NORMAL; |
||||
asm("sync;msync"); |
||||
*sdram_addr = 0xff; |
||||
ppcDcbf((unsigned long) sdram_addr); |
||||
udelay(200); /* Overkill. Must wait > 200 bus cycles */ |
||||
|
||||
#endif /* enable SDRAM init */ |
||||
} |
||||
|
||||
#if defined(CFG_DRAM_TEST) |
||||
int |
||||
testdram(void) |
||||
{ |
||||
uint *pstart = (uint *) CFG_MEMTEST_START; |
||||
uint *pend = (uint *) CFG_MEMTEST_END; |
||||
uint *p; |
||||
|
||||
printf("Testing DRAM from 0x%08x to 0x%08x\n", |
||||
CFG_MEMTEST_START, |
||||
CFG_MEMTEST_END); |
||||
|
||||
printf("DRAM test phase 1:\n"); |
||||
for (p = pstart; p < pend; p++) |
||||
*p = 0xaaaaaaaa; |
||||
|
||||
for (p = pstart; p < pend; p++) { |
||||
if (*p != 0xaaaaaaaa) { |
||||
printf ("DRAM test fails at: %08x\n", (uint) p); |
||||
return 1; |
||||
} |
||||
} |
||||
|
||||
printf("DRAM test phase 2:\n"); |
||||
for (p = pstart; p < pend; p++) |
||||
*p = 0x55555555; |
||||
|
||||
for (p = pstart; p < pend; p++) { |
||||
if (*p != 0x55555555) { |
||||
printf ("DRAM test fails at: %08x\n", (uint) p); |
||||
return 1; |
||||
} |
||||
} |
||||
|
||||
printf("DRAM test passed.\n"); |
||||
return 0; |
||||
} |
||||
#endif |
||||
|
||||
#if defined(CONFIG_PCI) |
||||
|
||||
/*
|
||||
* Initialize PCI Devices, report devices found. |
||||
*/ |
||||
|
||||
#ifndef CONFIG_PCI_PNP |
||||
static struct pci_config_table pci_mpc85xxcds_config_table[] = { |
||||
{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, |
||||
PCI_IDSEL_NUMBER, PCI_ANY_ID, |
||||
pci_cfgfunc_config_device, { PCI_ENET0_IOADDR, |
||||
PCI_ENET0_MEMADDR, |
||||
PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
||||
} }, |
||||
{ } |
||||
}; |
||||
#endif |
||||
|
||||
static struct pci_controller hose = { |
||||
#ifndef CONFIG_PCI_PNP |
||||
config_table: pci_mpc85xxcds_config_table, |
||||
#endif |
||||
}; |
||||
|
||||
#endif /* CONFIG_PCI */ |
||||
|
||||
void |
||||
pci_init_board(void) |
||||
{ |
||||
#ifdef CONFIG_PCI |
||||
extern void pci_mpc85xx_init(struct pci_controller *hose); |
||||
|
||||
pci_mpc85xx_init(&hose); |
||||
#endif |
||||
} |
||||
@ -0,0 +1,147 @@ |
||||
/* |
||||
* Copyright 2004 Freescale Semiconductor. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
OUTPUT_ARCH(powerpc) |
||||
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); |
||||
/* Do we need any of these for elf? |
||||
__DYNAMIC = 0; */ |
||||
SECTIONS |
||||
{ |
||||
.resetvec 0xFFFFFFFC : |
||||
{ |
||||
*(.resetvec) |
||||
} = 0xffff |
||||
|
||||
.bootpg 0xFFFFF000 : |
||||
{ |
||||
cpu/mpc85xx/start.o (.bootpg) |
||||
board/cds/mpc8548cds/init.o (.bootpg) |
||||
} = 0xffff |
||||
|
||||
/* Read-only sections, merged into text segment: */ |
||||
. = + SIZEOF_HEADERS; |
||||
.interp : { *(.interp) } |
||||
.hash : { *(.hash) } |
||||
.dynsym : { *(.dynsym) } |
||||
.dynstr : { *(.dynstr) } |
||||
.rel.text : { *(.rel.text) } |
||||
.rela.text : { *(.rela.text) } |
||||
.rel.data : { *(.rel.data) } |
||||
.rela.data : { *(.rela.data) } |
||||
.rel.rodata : { *(.rel.rodata) } |
||||
.rela.rodata : { *(.rela.rodata) } |
||||
.rel.got : { *(.rel.got) } |
||||
.rela.got : { *(.rela.got) } |
||||
.rel.ctors : { *(.rel.ctors) } |
||||
.rela.ctors : { *(.rela.ctors) } |
||||
.rel.dtors : { *(.rel.dtors) } |
||||
.rela.dtors : { *(.rela.dtors) } |
||||
.rel.bss : { *(.rel.bss) } |
||||
.rela.bss : { *(.rela.bss) } |
||||
.rel.plt : { *(.rel.plt) } |
||||
.rela.plt : { *(.rela.plt) } |
||||
.init : { *(.init) } |
||||
.plt : { *(.plt) } |
||||
.text : |
||||
{ |
||||
cpu/mpc85xx/start.o (.text) |
||||
board/cds/mpc8548cds/init.o (.text) |
||||
cpu/mpc85xx/traps.o (.text) |
||||
cpu/mpc85xx/interrupts.o (.text) |
||||
cpu/mpc85xx/cpu_init.o (.text) |
||||
cpu/mpc85xx/cpu.o (.text) |
||||
cpu/mpc85xx/tsec.o (.text) |
||||
cpu/mpc85xx/speed.o (.text) |
||||
cpu/mpc85xx/pci.o (.text) |
||||
common/dlmalloc.o (.text) |
||||
lib_generic/crc32.o (.text) |
||||
lib_ppc/extable.o (.text) |
||||
lib_generic/zlib.o (.text) |
||||
*(.text) |
||||
*(.fixup) |
||||
*(.got1) |
||||
} |
||||
_etext = .; |
||||
PROVIDE (etext = .); |
||||
.rodata : |
||||
{ |
||||
*(.rodata) |
||||
*(.rodata1) |
||||
*(.rodata.str1.4) |
||||
} |
||||
.fini : { *(.fini) } =0 |
||||
.ctors : { *(.ctors) } |
||||
.dtors : { *(.dtors) } |
||||
|
||||
/* Read-write section, merged into data segment: */ |
||||
. = (. + 0x00FF) & 0xFFFFFF00; |
||||
_erotext = .; |
||||
PROVIDE (erotext = .); |
||||
.reloc : |
||||
{ |
||||
*(.got) |
||||
_GOT2_TABLE_ = .; |
||||
*(.got2) |
||||
_FIXUP_TABLE_ = .; |
||||
*(.fixup) |
||||
} |
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; |
||||
__fixup_entries = (. - _FIXUP_TABLE_) >> 2; |
||||
|
||||
.data : |
||||
{ |
||||
*(.data) |
||||
*(.data1) |
||||
*(.sdata) |
||||
*(.sdata2) |
||||
*(.dynamic) |
||||
CONSTRUCTORS |
||||
} |
||||
_edata = .; |
||||
PROVIDE (edata = .); |
||||
|
||||
__u_boot_cmd_start = .; |
||||
.u_boot_cmd : { *(.u_boot_cmd) } |
||||
__u_boot_cmd_end = .; |
||||
|
||||
__start___ex_table = .; |
||||
__ex_table : { *(__ex_table) } |
||||
__stop___ex_table = .; |
||||
|
||||
. = ALIGN(256); |
||||
__init_begin = .; |
||||
.text.init : { *(.text.init) } |
||||
.data.init : { *(.data.init) } |
||||
. = ALIGN(256); |
||||
__init_end = .; |
||||
|
||||
__bss_start = .; |
||||
.bss : |
||||
{ |
||||
*(.sbss) *(.scommon) |
||||
*(.dynbss) |
||||
*(.bss) |
||||
*(COMMON) |
||||
} |
||||
_end = . ; |
||||
PROVIDE (end = .); |
||||
} |
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,521 @@ |
||||
/*
|
||||
* Copyright 2004 Freescale Semiconductor. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
/*
|
||||
* mpc8548cds board configuration file |
||||
* |
||||
* Please refer to doc/README.mpc85xxcds for more info. |
||||
* |
||||
*/ |
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/* High Level Configuration Options */ |
||||
#define CONFIG_BOOKE 1 /* BOOKE */ |
||||
#define CONFIG_E500 1 /* BOOKE e500 family */ |
||||
#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ |
||||
#define CONFIG_MPC8548 1 /* MPC8548 specific */ |
||||
#define CONFIG_MPC8548CDS 1 /* MPC8548CDS board specific */ |
||||
|
||||
#undef CONFIG_PCI |
||||
#define CONFIG_TSEC_ENET /* tsec ethernet support */ |
||||
#define CONFIG_ENV_OVERWRITE |
||||
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ |
||||
#define CONFIG_DDR_DLL /* possible DLL fix needed */ |
||||
#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ |
||||
|
||||
#define CONFIG_DDR_ECC /* only for ECC DDR module */ |
||||
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ |
||||
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef |
||||
|
||||
|
||||
/*
|
||||
* When initializing flash, if we cannot find the manufacturer ID, |
||||
* assume this is the AMD flash associated with the CDS board. |
||||
* This allows booting from a promjet. |
||||
*/ |
||||
#define CONFIG_ASSUME_AMD_FLASH |
||||
|
||||
#define MPC85xx_DDR_SDRAM_CLK_CNTL /* 85xx has clock control reg */ |
||||
|
||||
#ifndef __ASSEMBLY__ |
||||
extern unsigned long get_clock_freq(void); |
||||
#endif |
||||
#define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */ |
||||
|
||||
/*
|
||||
* These can be toggled for performance analysis, otherwise use default. |
||||
*/ |
||||
#define CONFIG_L2_CACHE /* toggle L2 cache */ |
||||
#define CONFIG_BTB /* toggle branch predition */ |
||||
#define CONFIG_ADDR_STREAMING /* toggle addr streaming */ |
||||
|
||||
/*
|
||||
* Only possible on E500 Version 2 or newer cores. |
||||
*/ |
||||
#define CONFIG_ENABLE_36BIT_PHYS 1 |
||||
|
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ |
||||
|
||||
#undef CFG_DRAM_TEST /* memory test, takes time */ |
||||
#define CFG_MEMTEST_START 0x00200000 /* memtest works on */ |
||||
#define CFG_MEMTEST_END 0x00400000 |
||||
|
||||
/*
|
||||
* Base addresses -- Note these are effective addresses where the |
||||
* actual resources get mapped (not physical addresses) |
||||
*/ |
||||
#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ |
||||
#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ |
||||
#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ |
||||
|
||||
/*
|
||||
* DDR Setup |
||||
*/ |
||||
#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ |
||||
#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE |
||||
|
||||
#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ |
||||
|
||||
/*
|
||||
* Make sure required options are set |
||||
*/ |
||||
#ifndef CONFIG_SPD_EEPROM |
||||
#error ("CONFIG_SPD_EEPROM is required") |
||||
#endif |
||||
|
||||
#undef CONFIG_CLOCKS_IN_MHZ |
||||
|
||||
|
||||
/*
|
||||
* Local Bus Definitions |
||||
*/ |
||||
|
||||
/*
|
||||
* FLASH on the Local Bus |
||||
* Two banks, 8M each, using the CFI driver. |
||||
* Boot from BR0/OR0 bank at 0xff00_0000 |
||||
* Alternate BR1/OR1 bank at 0xff80_0000 |
||||
* |
||||
* BR0, BR1: |
||||
* Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0 |
||||
* Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0 |
||||
* Port Size = 16 bits = BRx[19:20] = 10 |
||||
* Use GPCM = BRx[24:26] = 000 |
||||
* Valid = BRx[31] = 1 |
||||
* |
||||
* 0 4 8 12 16 20 24 28 |
||||
* 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0 |
||||
* 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1 |
||||
* |
||||
* OR0, OR1: |
||||
* Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0 |
||||
* Reserved ORx[17:18] = 11, confusion here? |
||||
* CSNT = ORx[20] = 1 |
||||
* ACS = half cycle delay = ORx[21:22] = 11 |
||||
* SCY = 6 = ORx[24:27] = 0110 |
||||
* TRLX = use relaxed timing = ORx[29] = 1 |
||||
* EAD = use external address latch delay = OR[31] = 1 |
||||
* |
||||
* 0 4 8 12 16 20 24 28 |
||||
* 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx |
||||
*/ |
||||
|
||||
#define CFG_FLASH_BASE 0xff000000 /* start of FLASH 8M */ |
||||
|
||||
#define CFG_BR0_PRELIM 0xff801001 |
||||
#define CFG_BR1_PRELIM 0xff001001 |
||||
|
||||
#define CFG_OR0_PRELIM 0xff806e65 |
||||
#define CFG_OR1_PRELIM 0xff806e65 |
||||
|
||||
#define CFG_FLASH_BANKS_LIST {0xff800000, CFG_FLASH_BASE} |
||||
#define CFG_MAX_FLASH_BANKS 2 /* number of banks */ |
||||
#define CFG_MAX_FLASH_SECT 128 /* sectors per device */ |
||||
#undef CFG_FLASH_CHECKSUM |
||||
#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ |
||||
#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ |
||||
|
||||
#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ |
||||
|
||||
#define CFG_FLASH_CFI_DRIVER |
||||
#define CFG_FLASH_CFI |
||||
#define CFG_FLASH_EMPTY_INFO |
||||
|
||||
|
||||
/*
|
||||
* SDRAM on the Local Bus |
||||
*/ |
||||
#define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ |
||||
#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ |
||||
|
||||
/*
|
||||
* Base Register 2 and Option Register 2 configure SDRAM. |
||||
* The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000. |
||||
* |
||||
* For BR2, need: |
||||
* Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 |
||||
* port-size = 32-bits = BR2[19:20] = 11 |
||||
* no parity checking = BR2[21:22] = 00 |
||||
* SDRAM for MSEL = BR2[24:26] = 011 |
||||
* Valid = BR[31] = 1 |
||||
* |
||||
* 0 4 8 12 16 20 24 28 |
||||
* 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 |
||||
* |
||||
* FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into |
||||
* FIXME: the top 17 bits of BR2. |
||||
*/ |
||||
|
||||
#define CFG_BR2_PRELIM 0xf0001861 |
||||
|
||||
/*
|
||||
* The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64. |
||||
* |
||||
* For OR2, need: |
||||
* 64MB mask for AM, OR2[0:7] = 1111 1100 |
||||
* XAM, OR2[17:18] = 11 |
||||
* 9 columns OR2[19-21] = 010 |
||||
* 13 rows OR2[23-25] = 100 |
||||
* EAD set for extra time OR[31] = 1 |
||||
* |
||||
* 0 4 8 12 16 20 24 28 |
||||
* 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 |
||||
*/ |
||||
|
||||
#define CFG_OR2_PRELIM 0xfc006901 |
||||
|
||||
#define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */ |
||||
#define CFG_LBC_LBCR 0x00000000 /* LB config reg */ |
||||
#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ |
||||
#define CFG_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ |
||||
|
||||
/*
|
||||
* LSDMR masks |
||||
*/ |
||||
#define CFG_LBC_LSDMR_RFEN (1 << (31 - 1)) |
||||
#define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10)) |
||||
#define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10)) |
||||
#define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16)) |
||||
#define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19)) |
||||
#define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22)) |
||||
#define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22)) |
||||
#define CFG_LBC_LSDMR_BL8 (1 << (31 - 23)) |
||||
#define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27)) |
||||
#define CFG_LBC_LSDMR_CL3 (3 << (31 - 31)) |
||||
|
||||
#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) |
||||
#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) |
||||
#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) |
||||
#define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4)) |
||||
#define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) |
||||
#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) |
||||
#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) |
||||
#define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) |
||||
|
||||
/*
|
||||
* Common settings for all Local Bus SDRAM commands. |
||||
* At run time, either BSMA1516 (for CPU 1.1) |
||||
* or BSMA1617 (for CPU 1.0) (old) |
||||
* is OR'ed in too. |
||||
*/ |
||||
#define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_RFCR16 \ |
||||
| CFG_LBC_LSDMR_PRETOACT7 \
|
||||
| CFG_LBC_LSDMR_ACTTORW7 \
|
||||
| CFG_LBC_LSDMR_BL8 \
|
||||
| CFG_LBC_LSDMR_WRC4 \
|
||||
| CFG_LBC_LSDMR_CL3 \
|
||||
| CFG_LBC_LSDMR_RFEN \
|
||||
) |
||||
|
||||
/*
|
||||
* The CADMUS registers are connected to CS3 on CDS. |
||||
* The new memory map places CADMUS at 0xf8000000. |
||||
* |
||||
* For BR3, need: |
||||
* Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0 |
||||
* port-size = 8-bits = BR[19:20] = 01 |
||||
* no parity checking = BR[21:22] = 00 |
||||
* GPMC for MSEL = BR[24:26] = 000 |
||||
* Valid = BR[31] = 1 |
||||
* |
||||
* 0 4 8 12 16 20 24 28 |
||||
* 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801 |
||||
* |
||||
* For OR3, need: |
||||
* 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0 |
||||
* disable buffer ctrl OR[19] = 0 |
||||
* CSNT OR[20] = 1 |
||||
* ACS OR[21:22] = 11 |
||||
* XACS OR[23] = 1 |
||||
* SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe |
||||
* SETA OR[28] = 0 |
||||
* TRLX OR[29] = 1 |
||||
* EHTR OR[30] = 1 |
||||
* EAD extra time OR[31] = 1 |
||||
* |
||||
* 0 4 8 12 16 20 24 28 |
||||
* 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7 |
||||
*/ |
||||
|
||||
#define CADMUS_BASE_ADDR 0xf8000000 |
||||
#define CFG_BR3_PRELIM 0xf8000801 |
||||
#define CFG_OR3_PRELIM 0xfff00ff7 |
||||
|
||||
#define CONFIG_L1_INIT_RAM |
||||
#define CFG_INIT_RAM_LOCK 1 |
||||
#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ |
||||
#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ |
||||
|
||||
#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ |
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET |
||||
|
||||
#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ |
||||
#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ |
||||
|
||||
/* Serial Port */ |
||||
#define CONFIG_CONS_INDEX 2 |
||||
#undef CONFIG_SERIAL_SOFTWARE_FIFO |
||||
#define CFG_NS16550 |
||||
#define CFG_NS16550_SERIAL |
||||
#define CFG_NS16550_REG_SIZE 1 |
||||
#define CFG_NS16550_CLK get_bus_freq(0) |
||||
|
||||
#define CFG_BAUDRATE_TABLE \ |
||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} |
||||
|
||||
#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) |
||||
#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) |
||||
|
||||
/* Use the HUSH parser */ |
||||
#define CFG_HUSH_PARSER |
||||
#ifdef CFG_HUSH_PARSER |
||||
#define CFG_PROMPT_HUSH_PS2 "> " |
||||
#endif |
||||
|
||||
/* I2C */ |
||||
#define CONFIG_HARD_I2C /* I2C with hardware support */ |
||||
#undef CONFIG_SOFT_I2C /* I2C bit-banged */ |
||||
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ |
||||
#define CFG_I2C_EEPROM_ADDR 0x57 |
||||
#define CFG_I2C_SLAVE 0x7F |
||||
#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ |
||||
|
||||
/*
|
||||
* General PCI |
||||
* Addresses are mapped 1-1. |
||||
*/ |
||||
#define CFG_PCI1_MEM_BASE 0x80000000 |
||||
#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE |
||||
#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ |
||||
#define CFG_PCI1_IO_BASE 0xe2000000 |
||||
#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE |
||||
#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ |
||||
|
||||
#define CFG_PCI2_MEM_BASE 0xa0000000 |
||||
#define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE |
||||
#define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */ |
||||
#define CFG_PCI2_IO_BASE 0xe3000000 |
||||
#define CFG_PCI2_IO_PHYS CFG_PCI2_IO_BASE |
||||
#define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */ |
||||
|
||||
|
||||
#if defined(CONFIG_PCI) |
||||
|
||||
#define CONFIG_NET_MULTI |
||||
#define CONFIG_PCI_PNP /* do pci plug-and-play */ |
||||
|
||||
#undef CONFIG_EEPRO100 |
||||
#undef CONFIG_TULIP |
||||
|
||||
#if !defined(CONFIG_PCI_PNP) |
||||
#define PCI_ENET0_IOADDR 0xe0000000 |
||||
#define PCI_ENET0_MEMADDR 0xe0000000 |
||||
#define PCI_IDSEL_NUMBER 0x0c /*slot0->3(IDSEL)=12->15*/ |
||||
#endif |
||||
|
||||
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
||||
#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ |
||||
|
||||
#endif /* CONFIG_PCI */ |
||||
|
||||
|
||||
#if defined(CONFIG_TSEC_ENET) |
||||
|
||||
#ifndef CONFIG_NET_MULTI |
||||
#define CONFIG_NET_MULTI 1 |
||||
#endif |
||||
|
||||
#define CONFIG_MII 1 /* MII PHY management */ |
||||
#define CONFIG_MPC85XX_TSEC1 1 |
||||
#define CONFIG_MPC85XX_TSEC1_NAME "eTSEC0" |
||||
#define CONFIG_MPC85XX_TSEC2 1 |
||||
#define CONFIG_MPC85XX_TSEC2_NAME "eTSEC1" |
||||
#define CONFIG_MPC85XX_TSEC3 1 |
||||
#define CONFIG_MPC85XX_TSEC3_NAME "eTSEC2" |
||||
#define CONFIG_MPC85XX_TSEC4 1 |
||||
#define CONFIG_MPC85XX_TSEC4_NAME "eTSEC3" |
||||
#undef CONFIG_MPC85XX_FEC |
||||
|
||||
#define TSEC1_PHY_ADDR 0 |
||||
#define TSEC2_PHY_ADDR 1 |
||||
#define TSEC3_PHY_ADDR 2 |
||||
#define TSEC4_PHY_ADDR 3 |
||||
#define FEC_PHY_ADDR 3 |
||||
|
||||
#define TSEC1_PHYIDX 0 |
||||
#define TSEC2_PHYIDX 0 |
||||
#define TSEC3_PHYIDX 0 |
||||
#define TSEC4_PHYIDX 0 |
||||
#define FEC_PHYIDX 0 |
||||
|
||||
/* Options are: eTSEC[0-3] */ |
||||
#define CONFIG_ETHPRIME "eTSEC0" |
||||
|
||||
#endif /* CONFIG_TSEC_ENET */ |
||||
|
||||
/*
|
||||
* Environment |
||||
*/ |
||||
#define CFG_ENV_IS_IN_FLASH 1 |
||||
#define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) |
||||
#define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ |
||||
#define CFG_ENV_SIZE 0x2000 |
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
||||
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
||||
|
||||
#if defined(CONFIG_PCI) |
||||
#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ |
||||
| CFG_CMD_PCI \
|
||||
| CFG_CMD_PING \
|
||||
| CFG_CMD_I2C \
|
||||
| CFG_CMD_MII) |
||||
#else |
||||
#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ |
||||
| CFG_CMD_PING \
|
||||
| CFG_CMD_I2C \
|
||||
| CFG_CMD_MII) |
||||
#endif |
||||
#include <cmd_confdefs.h> |
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */ |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CFG_LONGHELP /* undef to save memory */ |
||||
#define CFG_LOAD_ADDR 0x2000000 /* default load address */ |
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#else |
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#endif |
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CFG_MAXARGS 16 /* max number of command args */ |
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
||||
#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 8 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization. |
||||
*/ |
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ |
||||
|
||||
/* Cache Configuration */ |
||||
#define CFG_DCACHE_SIZE 32768 |
||||
#define CFG_CACHELINE_SIZE 32 |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ |
||||
#endif |
||||
|
||||
/*
|
||||
* Internal Definitions |
||||
* |
||||
* Boot Flags |
||||
*/ |
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */ |
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
||||
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ |
||||
#endif |
||||
|
||||
/*
|
||||
* Environment Configuration |
||||
*/ |
||||
|
||||
/* The mac addresses for all ethernet interface */ |
||||
#if defined(CONFIG_TSEC_ENET) |
||||
#define CONFIG_ETHADDR 00:E0:0C:00:00:FD |
||||
#define CONFIG_HAS_ETH1 |
||||
#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD |
||||
#define CONFIG_HAS_ETH2 |
||||
#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD |
||||
#endif |
||||
|
||||
#define CONFIG_IPADDR 192.168.1.253 |
||||
|
||||
#define CONFIG_HOSTNAME unknown |
||||
#define CONFIG_ROOTPATH /nfsroot |
||||
#define CONFIG_BOOTFILE your.uImage |
||||
|
||||
#define CONFIG_SERVERIP 192.168.1.1 |
||||
#define CONFIG_GATEWAYIP 192.168.1.1 |
||||
#define CONFIG_NETMASK 255.255.255.0 |
||||
|
||||
#define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/ |
||||
|
||||
#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ |
||||
#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ |
||||
|
||||
#define CONFIG_BAUDRATE 115200 |
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"netdev=eth0\0" \
|
||||
"consoledev=ttyS1\0" \
|
||||
"ramdiskaddr=400000\0" \
|
||||
"ramdiskfile=your.ramdisk.u-boot\0" |
||||
|
||||
#define CONFIG_NFSBOOTCOMMAND \ |
||||
"setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=$serverip:$rootpath " \
|
||||
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
|
||||
"console=$consoledev,$baudrate $othbootargs;" \
|
||||
"tftp $loadaddr $bootfile;" \
|
||||
"bootm $loadaddr" |
||||
|
||||
#define CONFIG_RAMBOOTCOMMAND \ |
||||
"setenv bootargs root=/dev/ram rw " \
|
||||
"console=$consoledev,$baudrate $othbootargs;" \
|
||||
"tftp $ramdiskaddr $ramdiskfile;" \
|
||||
"tftp $loadaddr $bootfile;" \
|
||||
"bootm $loadaddr $ramdiskaddr" |
||||
|
||||
#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND |
||||
|
||||
#endif /* __CONFIG_H */ |
||||
Loading…
Reference in new issue