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@ -78,6 +78,13 @@ DECLARE_GLOBAL_DATA_PTR; |
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PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
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PAD_CTL_ODE | PAD_CTL_SRE_FAST) |
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#define IRQ_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ |
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PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
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PAD_CTL_DSE_34ohm | PAD_CTL_HYS | PAD_CTL_SRE_FAST) |
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#define DIO_PAD_CFG (MUX_PAD_CTRL(DIO_PAD_CTRL) | MUX_MODE_SION) |
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/*
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* EEPROM board info struct populated by read_eeprom so that we only have to |
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* read it once. |
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@ -187,7 +194,7 @@ iomux_v3_cfg_t const usdhc3_pads[] = { |
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IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), |
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IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), |
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/* CD */ |
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IOMUX_PADS(PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL)), |
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IOMUX_PADS(PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(IRQ_PAD_CTRL)), |
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}; |
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/* ENET */ |
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@ -211,7 +218,7 @@ iomux_v3_cfg_t const enet_pads[] = { |
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IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | |
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MUX_PAD_CTRL(ENET_PAD_CTRL)), |
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/* PHY nRST */ |
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IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL)), |
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IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30 | DIO_PAD_CFG), |
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}; |
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/* NAND */ |
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@ -281,10 +288,10 @@ static void setup_iomux_uart(void) |
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#ifdef CONFIG_USB_EHCI_MX6 |
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iomux_v3_cfg_t const usb_pads[] = { |
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IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(DIO_PAD_CTRL)), |
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IOMUX_PADS(PAD_KEY_COL4__USB_OTG_OC | MUX_PAD_CTRL(DIO_PAD_CTRL)), |
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IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID | DIO_PAD_CFG), |
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IOMUX_PADS(PAD_KEY_COL4__USB_OTG_OC | DIO_PAD_CFG), |
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/* OTG PWR */ |
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IOMUX_PADS(PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(DIO_PAD_CTRL)), |
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IOMUX_PADS(PAD_EIM_D22__GPIO3_IO22 | DIO_PAD_CFG), |
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}; |
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int board_ehci_hcd_init(int port) |
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@ -296,15 +303,13 @@ int board_ehci_hcd_init(int port) |
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/* Reset USB HUB (present on GW54xx/GW53xx) */ |
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switch (info->model[3]) { |
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case '3': /* GW53xx */ |
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SETUP_IOMUX_PAD(PAD_GPIO_9__GPIO1_IO09 | |
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MUX_PAD_CTRL(NO_PAD_CTRL)); |
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SETUP_IOMUX_PAD(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG); |
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gpio_direction_output(IMX_GPIO_NR(1, 9), 0); |
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mdelay(2); |
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gpio_set_value(IMX_GPIO_NR(1, 9), 1); |
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break; |
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case '4': /* GW54xx */ |
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SETUP_IOMUX_PAD(PAD_SD1_DAT0__GPIO1_IO16 | |
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MUX_PAD_CTRL(NO_PAD_CTRL)); |
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SETUP_IOMUX_PAD(PAD_SD1_DAT0__GPIO1_IO16 | DIO_PAD_CFG); |
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gpio_direction_output(IMX_GPIO_NR(1, 16), 0); |
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mdelay(2); |
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gpio_set_value(IMX_GPIO_NR(1, 16), 1); |
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@ -426,7 +431,7 @@ static void enable_lvds(struct display_info_t const *dev) |
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writel(reg, &iomux->gpr[2]); |
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/* Enable Backlight */ |
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SETUP_IOMUX_PAD(PAD_SD1_CMD__GPIO1_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL)); |
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SETUP_IOMUX_PAD(PAD_SD1_CMD__GPIO1_IO18 | DIO_PAD_CFG); |
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gpio_direction_output(IMX_GPIO_NR(1, 18), 1); |
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} |
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@ -523,7 +528,7 @@ static void setup_display(void) |
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writel(reg, &iomux->gpr[3]); |
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/* Backlight CABEN on LVDS connector */ |
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SETUP_IOMUX_PAD(PAD_SD2_CLK__GPIO1_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL)); |
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SETUP_IOMUX_PAD(PAD_SD2_CLK__GPIO1_IO10 | DIO_PAD_CFG); |
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gpio_direction_output(IMX_GPIO_NR(1, 10), 0); |
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} |
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#endif /* CONFIG_VIDEO_IPUV3 */ |
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@ -535,120 +540,120 @@ static void setup_display(void) |
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/* common to add baseboards */ |
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static iomux_v3_cfg_t const gw_gpio_pads[] = { |
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/* MSATA_EN */ |
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IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL)), |
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IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | DIO_PAD_CFG), |
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/* RS232_EN# */ |
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IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL)), |
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IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG), |
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}; |
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/* prototype */ |
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static iomux_v3_cfg_t const gwproto_gpio_pads[] = { |
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/* PANLEDG# */ |
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IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL)), |
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IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG), |
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/* PANLEDR# */ |
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IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL)), |
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IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), |
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/* LOCLED# */ |
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IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL)), |
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IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG), |
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/* RS485_EN */ |
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IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01 | MUX_PAD_CTRL(NO_PAD_CTRL)), |
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IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01 | DIO_PAD_CFG), |
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/* IOEXP_PWREN# */ |
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IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL)), |
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IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG), |
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/* IOEXP_IRQ# */ |
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IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL)), |
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IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)), |
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/* VID_EN */ |
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IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL)), |
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IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG), |
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/* DIOI2C_DIS# */ |
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IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL)), |
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IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG), |
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/* PCICK_SSON */ |
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IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL)), |
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IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20 | DIO_PAD_CFG), |
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/* PCI_RST# */ |
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IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)), |
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IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG), |
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}; |
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static iomux_v3_cfg_t const gw51xx_gpio_pads[] = { |
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/* PANLEDG# */ |
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IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL)), |
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IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG), |
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/* PANLEDR# */ |
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IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL)), |
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IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), |
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/* IOEXP_PWREN# */ |
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IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL)), |
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IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG), |
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/* IOEXP_IRQ# */ |
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IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL)), |
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IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)), |
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/* GPS_SHDN */ |
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IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL)), |
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IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG), |
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/* VID_PWR */ |
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IOMUX_PADS(PAD_CSI0_DATA_EN__GPIO5_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL)), |
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IOMUX_PADS(PAD_CSI0_DATA_EN__GPIO5_IO20 | DIO_PAD_CFG), |
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/* PCI_RST# */ |
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IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL)), |
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IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | DIO_PAD_CFG), |
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}; |
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static iomux_v3_cfg_t const gw52xx_gpio_pads[] = { |
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/* PANLEDG# */ |
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IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL)), |
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IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG), |
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/* PANLEDR# */ |
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IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL)), |
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IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), |
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/* IOEXP_PWREN# */ |
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IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL)), |
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IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG), |
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/* IOEXP_IRQ# */ |
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IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL)), |
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IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)), |
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/* MX6_LOCLED# */ |
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IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL)), |
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IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG), |
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/* GPS_SHDN */ |
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IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL)), |
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IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | DIO_PAD_CFG), |
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/* USBOTG_SEL */ |
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IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL)), |
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IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG), |
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/* VID_PWR */ |
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IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL)), |
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IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG), |
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/* PCI_RST# */ |
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IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)), |
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IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG), |
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}; |
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static iomux_v3_cfg_t const gw53xx_gpio_pads[] = { |
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/* PANLEDG# */ |
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IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL)), |
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IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG), |
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/* PANLEDR# */ |
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IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL)), |
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IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), |
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/* IOEXP_PWREN# */ |
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IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL)), |
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IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG), |
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/* IOEXP_IRQ# */ |
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IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL)), |
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IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)), |
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/* DIOI2C_DIS# */ |
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IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL)), |
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IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG), |
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/* MX6_LOCLED# */ |
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IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL)), |
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IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG), |
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/* GPS_SHDN */ |
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IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL)), |
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IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | DIO_PAD_CFG), |
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/* VID_EN */ |
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IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL)), |
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IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG), |
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/* PCI_RST# */ |
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IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)), |
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IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG), |
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}; |
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static iomux_v3_cfg_t const gw54xx_gpio_pads[] = { |
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/* PANLEDG# */ |
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IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL)), |
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IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG), |
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/* PANLEDR# */ |
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IOMUX_PADS(PAD_KEY_COL2__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL)), |
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IOMUX_PADS(PAD_KEY_COL2__GPIO4_IO10 | DIO_PAD_CFG), |
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/* MX6_LOCLED# */ |
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IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL)), |
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IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG), |
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/* MIPI_DIO */ |
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IOMUX_PADS(PAD_SD1_DAT3__GPIO1_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL)), |
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IOMUX_PADS(PAD_SD1_DAT3__GPIO1_IO21 | DIO_PAD_CFG), |
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/* RS485_EN */ |
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IOMUX_PADS(PAD_EIM_D24__GPIO3_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL)), |
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IOMUX_PADS(PAD_EIM_D24__GPIO3_IO24 | DIO_PAD_CFG), |
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/* IOEXP_PWREN# */ |
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IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL)), |
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IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), |
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/* IOEXP_IRQ# */ |
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IOMUX_PADS(PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL)), |
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IOMUX_PADS(PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(IRQ_PAD_CTRL)), |
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/* DIOI2C_DIS# */ |
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IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL)), |
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IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG), |
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/* PCICK_SSON */ |
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IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL)), |
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IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20 | DIO_PAD_CFG), |
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/* PCI_RST# */ |
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IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)), |
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IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG), |
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/* VID_EN */ |
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IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL)), |
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IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG), |
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}; |
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/*
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@ -1024,15 +1029,17 @@ static void setup_board_gpio(int board) |
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*/ |
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for (i = 0; i < 4; i++) { |
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struct dio_cfg *cfg = &gpio_cfg[board].dio_cfg[i]; |
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unsigned ctrl = DIO_PAD_CTRL; |
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iomux_v3_cfg_t ctrl = DIO_PAD_CFG; |
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unsigned cputype = is_cpu_type(MXC_CPU_MX6Q) ? 0 : 1; |
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sprintf(arg, "dio%d", i); |
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if (!hwconfig(arg)) |
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continue; |
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s = hwconfig_subarg(arg, "padctrl", &len); |
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if (s) |
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ctrl = simple_strtoul(s, NULL, 16) & 0x3ffff; |
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if (s) { |
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ctrl = MUX_PAD_CTRL(simple_strtoul(s, NULL, 16) |
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& 0x1ffff) | MUX_MODE_SION; |
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} |
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if (hwconfig_subarg_cmp(arg, "mode", "gpio")) { |
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if (!quiet) { |
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printf("DIO%d: GPIO%d_IO%02d (gpio-%d)\n", i, |
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@ -1041,7 +1048,7 @@ static void setup_board_gpio(int board) |
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cfg->gpio_param); |
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} |
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imx_iomux_v3_setup_pad(cfg->gpio_padmux[cputype] | |
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MUX_PAD_CTRL(ctrl)); |
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ctrl); |
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gpio_direction_input(cfg->gpio_param); |
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} else if (hwconfig_subarg_cmp("dio2", "mode", "pwm") && |
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cfg->pwm_padmux) { |
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