Tom Rini
7 years ago
commit
d9d76023ea
@ -0,0 +1,37 @@ |
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/* |
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* (C) 2017 Theobroma Systems Design und Consulting GmbH |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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|
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#include <config.h> |
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#include <asm/assembler.h> |
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#include <linux/linkage.h> |
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|
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.pushsection .text.setjmp, "ax" |
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ENTRY(setjmp) |
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/* |
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* A subroutine must preserve the contents of the registers |
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* r4-r8, r10, r11 (v1-v5, v7 and v8) and SP (and r9 in PCS |
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* variants that designate r9 as v6). |
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*/ |
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mov ip, sp |
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stm a1, {v1-v8, ip, lr} |
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mov a1, #0 |
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bx lr |
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ENDPROC(setjmp) |
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.popsection |
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|
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.pushsection .text.longjmp, "ax" |
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ENTRY(longjmp) |
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ldm a1, {v1-v8, ip, lr} |
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mov sp, ip |
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mov a1, a2 |
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/* If we were passed a return value of zero, return one instead */ |
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cmp a1, #0 |
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bne 1f |
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mov a1, #1 |
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1: |
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bx lr |
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ENDPROC(longjmp) |
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.popsection |
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@ -0,0 +1,42 @@ |
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/* |
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* (C) 2017 Theobroma Systems Design und Consulting GmbH |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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|
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#include <config.h> |
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#include <asm/macro.h> |
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#include <linux/linkage.h> |
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|
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.pushsection .text.setjmp, "ax" |
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ENTRY(setjmp) |
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/* Preserve all callee-saved registers and the SP */ |
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stp x19, x20, [x0,#0] |
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stp x21, x22, [x0,#16] |
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stp x23, x24, [x0,#32] |
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stp x25, x26, [x0,#48] |
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stp x27, x28, [x0,#64] |
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stp x29, x30, [x0,#80] |
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mov x2, sp |
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str x2, [x0, #96] |
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mov x0, #0 |
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ret |
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ENDPROC(setjmp) |
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.popsection |
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|
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.pushsection .text.longjmp, "ax" |
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ENTRY(longjmp) |
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ldp x19, x20, [x0,#0] |
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ldp x21, x22, [x0,#16] |
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ldp x23, x24, [x0,#32] |
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ldp x25, x26, [x0,#48] |
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ldp x27, x28, [x0,#64] |
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ldp x29, x30, [x0,#80] |
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ldr x2, [x0,#96] |
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mov sp, x2 |
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/* Move the return value in place, but return 1 if passed 0. */ |
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adds x0, xzr, x1 |
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csinc x0, x0, xzr, ne |
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ret |
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ENDPROC(longjmp) |
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.popsection |
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@ -0,0 +1,76 @@ |
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/*
|
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* (C) Copyright 2016 Rockchip Electronics Co., Ltd |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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|
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#include <common.h> |
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#include <adc.h> |
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#include <asm/io.h> |
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#include <asm/arch/boot_mode.h> |
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|
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void set_back_to_bootrom_dnl_flag(void) |
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{ |
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writel(BOOT_BROM_DOWNLOAD, CONFIG_ROCKCHIP_BOOT_MODE_REG); |
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} |
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|
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/*
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* detect download key status by adc, most rockchip |
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* based boards use adc sample the download key status, |
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* but there are also some use gpio. So it's better to |
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* make this a weak function that can be override by |
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* some special boards. |
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*/ |
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#define KEY_DOWN_MIN_VAL 0 |
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#define KEY_DOWN_MAX_VAL 30 |
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__weak int rockchip_dnl_key_pressed(void) |
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{ |
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unsigned int val; |
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if (adc_channel_single_shot("saradc", 1, &val)) { |
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pr_err("%s: adc_channel_single_shot fail!\n", __func__); |
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return false; |
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} |
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if ((val >= KEY_DOWN_MIN_VAL) && (val <= KEY_DOWN_MAX_VAL)) |
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return true; |
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else |
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return false; |
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} |
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|
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void rockchip_dnl_mode_check(void) |
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{ |
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if (rockchip_dnl_key_pressed()) { |
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printf("download key pressed, entering download mode..."); |
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set_back_to_bootrom_dnl_flag(); |
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do_reset(NULL, 0, 0, NULL); |
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} |
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} |
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|
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int setup_boot_mode(void) |
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{ |
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void *reg = (void *)CONFIG_ROCKCHIP_BOOT_MODE_REG; |
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int boot_mode = readl(reg); |
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rockchip_dnl_mode_check(); |
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boot_mode = readl(reg); |
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debug("%s: boot mode 0x%08x\n", __func__, boot_mode); |
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/* Clear boot mode */ |
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writel(BOOT_NORMAL, reg); |
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switch (boot_mode) { |
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case BOOT_FASTBOOT: |
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debug("%s: enter fastboot!\n", __func__); |
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env_set("preboot", "setenv preboot; fastboot usb0"); |
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break; |
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case BOOT_UMS: |
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debug("%s: enter UMS!\n", __func__); |
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env_set("preboot", "setenv preboot; ums mmc 0"); |
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break; |
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} |
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return 0; |
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} |
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@ -1,86 +0,0 @@ |
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/*
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* (C) Copyright 2015 Google, Inc |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <debug_uart.h> |
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#include <spl.h> |
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#include <asm/io.h> |
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#include <asm/arch/bootrom.h> |
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#include <asm/arch/pmu_rk3188.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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/* track how often we were entered */ |
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static int rk3188_num_entries __attribute__ ((section(".data"))); |
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#define PMU_BASE 0x20004000 |
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#define SPL_ENTRY 0x10080C00 |
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static void jump_to_spl(void) |
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{ |
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typedef void __noreturn (*image_entry_noargs_t)(void); |
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struct rk3188_pmu * const pmu = (void *)PMU_BASE; |
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image_entry_noargs_t tpl_entry = |
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(image_entry_noargs_t)(unsigned long)SPL_ENTRY; |
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/* Store the SAVE_SP_ADDR in a location shared with SPL. */ |
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writel(SAVE_SP_ADDR, &pmu->sys_reg[2]); |
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tpl_entry(); |
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} |
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|
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void board_init_f(ulong dummy) |
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{ |
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/* Example code showing how to enable the debug UART on RK3188 */ |
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#ifdef EARLY_UART |
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#include <asm/arch/grf_rk3188.h> |
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/* Enable early UART on the RK3188 */ |
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#define GRF_BASE 0x20008000 |
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struct rk3188_grf * const grf = (void *)GRF_BASE; |
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rk_clrsetreg(&grf->gpio1b_iomux, |
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GPIO1B1_MASK << GPIO1B1_SHIFT | |
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GPIO1B0_MASK << GPIO1B0_SHIFT, |
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GPIO1B1_UART2_SOUT << GPIO1B1_SHIFT | |
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GPIO1B0_UART2_SIN << GPIO1B0_SHIFT); |
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/*
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* Debug UART can be used from here if required: |
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* |
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* debug_uart_init(); |
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* printch('a'); |
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* printhex8(0x1234); |
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* printascii("string"); |
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*/ |
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debug_uart_init(); |
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printch('t'); |
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printch('p'); |
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printch('l'); |
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printch('-'); |
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printch(rk3188_num_entries + 1 + '0'); |
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printch('\n'); |
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#endif |
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rk3188_num_entries++; |
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if (rk3188_num_entries == 1) { |
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/*
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* The original loader did some very basic integrity |
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* checking at this point, but the remaining few bytes |
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* could be used for any improvement making sense |
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* really early on. |
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*/ |
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back_to_bootrom(); |
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} else { |
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/*
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* TPL part of the loader should now wait for us |
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* at offset 0xC00 in the sram. Should never return |
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* from there. |
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*/ |
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jump_to_spl(); |
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} |
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} |
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@ -0,0 +1,14 @@ |
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/*
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* Copyright (c) 2017 Rockchip Electronics Co., Ltd |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <asm/arch/boot_mode.h> |
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int board_late_init(void) |
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{ |
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setup_boot_mode(); |
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return 0; |
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} |
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@ -1,69 +0,0 @@ |
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/* |
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* (C) Copyright 2016 Rockchip Electronics Co., Ltd |
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* (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <linux/linkage.h> |
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#if defined(CONFIG_ARM64) |
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.globl SAVE_SP_ADDR
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SAVE_SP_ADDR: |
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.quad 0
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ENTRY(save_boot_params) |
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sub sp, sp, #0x60 |
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stp x29, x30, [sp, #0x50] |
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stp x27, x28, [sp, #0x40] |
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stp x25, x26, [sp, #0x30] |
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stp x23, x24, [sp, #0x20] |
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stp x21, x22, [sp, #0x10] |
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stp x19, x20, [sp, #0] |
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ldr x8, =SAVE_SP_ADDR |
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mov x9, sp |
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str x9, [x8] |
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b save_boot_params_ret /* back to my caller */ |
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ENDPROC(save_boot_params) |
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.globl _back_to_bootrom_s
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ENTRY(_back_to_bootrom_s) |
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ldr x0, =SAVE_SP_ADDR |
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ldr x0, [x0] |
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mov sp, x0 |
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ldp x29, x30, [sp, #0x50] |
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ldp x27, x28, [sp, #0x40] |
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ldp x25, x26, [sp, #0x30] |
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ldp x23, x24, [sp, #0x20] |
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ldp x21, x22, [sp, #0x10] |
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ldp x19, x20, [sp] |
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add sp, sp, #0x60 |
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mov x0, xzr |
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ret |
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ENDPROC(_back_to_bootrom_s) |
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#else |
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.globl SAVE_SP_ADDR
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SAVE_SP_ADDR: |
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.word 0
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/* |
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* void save_boot_params |
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* |
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* Save sp, lr, r1~r12 |
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*/ |
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ENTRY(save_boot_params) |
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push {r1-r12, lr} |
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ldr r0, =SAVE_SP_ADDR |
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str sp, [r0] |
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b save_boot_params_ret @ back to my caller
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ENDPROC(save_boot_params) |
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.globl _back_to_bootrom_s
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ENTRY(_back_to_bootrom_s) |
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ldr r0, =SAVE_SP_ADDR |
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ldr sp, [r0] |
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mov r0, #0 |
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pop {r1-r12, pc} |
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ENDPROC(_back_to_bootrom_s) |
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#endif |
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@ -1,45 +0,0 @@ |
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/*
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* (C) Copyright 2015 Rockchip Electronics Co., Ltd |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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|
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#include <common.h> |
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#include <dm.h> |
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#include <errno.h> |
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#include <sysreset.h> |
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#include <asm/io.h> |
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#include <asm/arch/clock.h> |
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#include <asm/arch/cru_rk3036.h> |
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#include <asm/arch/hardware.h> |
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#include <linux/err.h> |
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|
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int rk3036_sysreset_request(struct udevice *dev, enum sysreset_t type) |
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{ |
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struct rk3036_cru *cru = rockchip_get_cru(); |
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if (IS_ERR(cru)) |
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return PTR_ERR(cru); |
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switch (type) { |
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case SYSRESET_WARM: |
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writel(0xeca8, &cru->cru_glb_srst_snd_value); |
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break; |
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case SYSRESET_COLD: |
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writel(0xfdb9, &cru->cru_glb_srst_fst_value); |
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break; |
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default: |
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return -EPROTONOSUPPORT; |
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} |
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|
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return -EINPROGRESS; |
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} |
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static struct sysreset_ops rk3036_sysreset = { |
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.request = rk3036_sysreset_request, |
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}; |
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U_BOOT_DRIVER(sysreset_rk3036) = { |
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.name = "rk3036_sysreset", |
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.id = UCLASS_SYSRESET, |
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.ops = &rk3036_sysreset, |
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}; |
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@ -1,62 +0,0 @@ |
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/*
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* (C) Copyright 2015 Google, Inc |
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* |
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* SPDX-License-Identifier: GPL-2.0 |
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*/ |
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|
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#include <common.h> |
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#include <dm.h> |
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#include <errno.h> |
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#include <syscon.h> |
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#include <sysreset.h> |
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#include <asm/io.h> |
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#include <asm/arch/clock.h> |
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#include <asm/arch/cru_rk3188.h> |
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#include <asm/arch/grf_rk3188.h> |
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#include <asm/arch/hardware.h> |
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#include <linux/err.h> |
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|
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int rk3188_sysreset_request(struct udevice *dev, enum sysreset_t type) |
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{ |
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struct rk3188_cru *cru = rockchip_get_cru(); |
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struct rk3188_grf *grf; |
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if (IS_ERR(cru)) |
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return PTR_ERR(cru); |
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switch (type) { |
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case SYSRESET_WARM: |
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grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); |
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if (IS_ERR(grf)) |
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return -EPROTONOSUPPORT; |
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|
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/*
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* warm-reset keeps the remap value, |
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* so make sure it's disabled. |
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*/ |
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rk_clrsetreg(&grf->soc_con0, |
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NOC_REMAP_MASK << NOC_REMAP_SHIFT, |
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0 << NOC_REMAP_SHIFT); |
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|
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rk_clrreg(&cru->cru_mode_con, 0xffff); |
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writel(0xeca8, &cru->cru_glb_srst_snd_value); |
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break; |
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case SYSRESET_COLD: |
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rk_clrreg(&cru->cru_mode_con, 0xffff); |
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writel(0xfdb9, &cru->cru_glb_srst_fst_value); |
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break; |
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default: |
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return -EPROTONOSUPPORT; |
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} |
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|
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return -EINPROGRESS; |
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} |
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|
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static struct sysreset_ops rk3188_sysreset = { |
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.request = rk3188_sysreset_request, |
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}; |
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|
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U_BOOT_DRIVER(sysreset_rk3188) = { |
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.name = "rk3188_sysreset", |
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.id = UCLASS_SYSRESET, |
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.ops = &rk3188_sysreset, |
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}; |
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@ -1,45 +0,0 @@ |
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/*
|
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* (C) Copyright 2017 Rockchip Electronics Co., Ltd |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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|
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#include <common.h> |
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#include <dm.h> |
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#include <errno.h> |
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#include <sysreset.h> |
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#include <asm/io.h> |
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#include <asm/arch/clock.h> |
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#include <asm/arch/cru_rk322x.h> |
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#include <asm/arch/hardware.h> |
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#include <linux/err.h> |
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|
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int rk322x_sysreset_request(struct udevice *dev, enum sysreset_t type) |
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{ |
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struct rk322x_cru *cru = rockchip_get_cru(); |
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|
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if (IS_ERR(cru)) |
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return PTR_ERR(cru); |
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switch (type) { |
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case SYSRESET_WARM: |
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writel(0xeca8, &cru->cru_glb_srst_snd_value); |
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break; |
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case SYSRESET_COLD: |
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writel(0xfdb9, &cru->cru_glb_srst_fst_value); |
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break; |
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default: |
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return -EPROTONOSUPPORT; |
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} |
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|
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return -EINPROGRESS; |
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} |
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|
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static struct sysreset_ops rk322x_sysreset = { |
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.request = rk322x_sysreset_request, |
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}; |
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|
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U_BOOT_DRIVER(sysreset_rk322x) = { |
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.name = "rk322x_sysreset", |
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.id = UCLASS_SYSRESET, |
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.ops = &rk322x_sysreset, |
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}; |
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@ -1,47 +0,0 @@ |
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/*
|
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* (C) Copyright 2015 Google, Inc |
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* |
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* SPDX-License-Identifier: GPL-2.0 |
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*/ |
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|
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#include <common.h> |
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#include <dm.h> |
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#include <errno.h> |
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#include <sysreset.h> |
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#include <asm/io.h> |
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#include <asm/arch/clock.h> |
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#include <asm/arch/cru_rk3288.h> |
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#include <asm/arch/hardware.h> |
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#include <linux/err.h> |
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|
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int rk3288_sysreset_request(struct udevice *dev, enum sysreset_t type) |
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{ |
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struct rk3288_cru *cru = rockchip_get_cru(); |
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|
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if (IS_ERR(cru)) |
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return PTR_ERR(cru); |
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switch (type) { |
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case SYSRESET_WARM: |
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rk_clrreg(&cru->cru_mode_con, 0xffff); |
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writel(0xeca8, &cru->cru_glb_srst_snd_value); |
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break; |
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case SYSRESET_COLD: |
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rk_clrreg(&cru->cru_mode_con, 0xffff); |
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writel(0xfdb9, &cru->cru_glb_srst_fst_value); |
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break; |
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default: |
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return -EPROTONOSUPPORT; |
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} |
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|
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return -EINPROGRESS; |
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} |
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|
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static struct sysreset_ops rk3288_sysreset = { |
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.request = rk3288_sysreset_request, |
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}; |
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|
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U_BOOT_DRIVER(sysreset_rk3288) = { |
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.name = "rk3288_sysreset", |
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.id = UCLASS_SYSRESET, |
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.ops = &rk3288_sysreset, |
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}; |
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@ -1,45 +0,0 @@ |
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/*
|
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* (C) Copyright 2016 Rockchip Electronics Co., Ltd |
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* |
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* SPDX-License-Identifier: GPL-2.0 |
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*/ |
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|
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#include <common.h> |
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#include <dm.h> |
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#include <errno.h> |
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#include <sysreset.h> |
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#include <asm/arch/clock.h> |
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#include <asm/arch/cru_rk3328.h> |
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#include <asm/arch/hardware.h> |
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#include <asm/io.h> |
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#include <linux/err.h> |
||||
|
||||
int rk3328_sysreset_request(struct udevice *dev, enum sysreset_t type) |
||||
{ |
||||
struct rk3328_cru *cru = rockchip_get_cru(); |
||||
|
||||
if (IS_ERR(cru)) |
||||
return PTR_ERR(cru); |
||||
switch (type) { |
||||
case SYSRESET_WARM: |
||||
writel(0xeca8, &cru->glb_srst_snd_value); |
||||
break; |
||||
case SYSRESET_COLD: |
||||
writel(0xfdb9, &cru->glb_srst_fst_value); |
||||
break; |
||||
default: |
||||
return -EPROTONOSUPPORT; |
||||
} |
||||
|
||||
return -EINPROGRESS; |
||||
} |
||||
|
||||
static struct sysreset_ops rk3328_sysreset = { |
||||
.request = rk3328_sysreset_request, |
||||
}; |
||||
|
||||
U_BOOT_DRIVER(sysreset_rk3328) = { |
||||
.name = "rk3328_sysreset", |
||||
.id = UCLASS_SYSRESET, |
||||
.ops = &rk3328_sysreset, |
||||
}; |
||||
@ -1,62 +0,0 @@ |
||||
/*
|
||||
* (C) Copyright Rockchip Electronics Co., Ltd |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0 |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <dm.h> |
||||
#include <errno.h> |
||||
#include <sysreset.h> |
||||
#include <asm/io.h> |
||||
#include <asm/arch/clock.h> |
||||
#include <asm/arch/cru_rk3368.h> |
||||
#include <asm/arch/hardware.h> |
||||
#include <linux/err.h> |
||||
|
||||
static void rk3368_pll_enter_slow_mode(struct rk3368_cru *cru) |
||||
{ |
||||
struct rk3368_pll *pll; |
||||
int i; |
||||
|
||||
for (i = 0; i < 6; i++) { |
||||
pll = &cru->pll[i]; |
||||
rk_clrreg(&pll->con3, PLL_MODE_MASK); |
||||
} |
||||
} |
||||
|
||||
static int rk3368_sysreset_request(struct udevice *dev, enum sysreset_t type) |
||||
{ |
||||
struct rk3368_cru *cru = rockchip_get_cru(); |
||||
|
||||
if (IS_ERR(cru)) |
||||
return PTR_ERR(cru); |
||||
switch (type) { |
||||
case SYSRESET_WARM: |
||||
rk3368_pll_enter_slow_mode(cru); |
||||
rk_clrsetreg(&cru->glb_rst_con, PMU_GLB_SRST_CTRL_MASK, |
||||
PMU_RST_BY_SND_GLB_SRST << PMU_GLB_SRST_CTRL_SHIFT); |
||||
writel(0xeca8, &cru->glb_srst_snd_val); |
||||
break; |
||||
case SYSRESET_COLD: |
||||
rk3368_pll_enter_slow_mode(cru); |
||||
rk_clrsetreg(&cru->glb_rst_con, PMU_GLB_SRST_CTRL_MASK, |
||||
PMU_RST_BY_FST_GLB_SRST << PMU_GLB_SRST_CTRL_SHIFT); |
||||
writel(0xfdb9, &cru->glb_srst_fst_val); |
||||
break; |
||||
default: |
||||
return -EPROTONOSUPPORT; |
||||
} |
||||
|
||||
return -EINPROGRESS; |
||||
} |
||||
|
||||
static struct sysreset_ops rk3368_sysreset = { |
||||
.request = rk3368_sysreset_request, |
||||
}; |
||||
|
||||
U_BOOT_DRIVER(sysreset_rk3368) = { |
||||
.name = "rk3368_sysreset", |
||||
.id = UCLASS_SYSRESET, |
||||
.ops = &rk3368_sysreset, |
||||
}; |
||||
@ -1,45 +0,0 @@ |
||||
/*
|
||||
* (C) Copyright 2016 Rockchip Electronics Co., Ltd |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0 |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <dm.h> |
||||
#include <errno.h> |
||||
#include <sysreset.h> |
||||
#include <asm/io.h> |
||||
#include <asm/arch/clock.h> |
||||
#include <asm/arch/cru_rk3399.h> |
||||
#include <asm/arch/hardware.h> |
||||
#include <linux/err.h> |
||||
|
||||
int rk3399_sysreset_request(struct udevice *dev, enum sysreset_t type) |
||||
{ |
||||
struct rk3399_cru *cru = rockchip_get_cru(); |
||||
|
||||
if (IS_ERR(cru)) |
||||
return PTR_ERR(cru); |
||||
switch (type) { |
||||
case SYSRESET_WARM: |
||||
writel(0xeca8, &cru->glb_srst_snd_value); |
||||
break; |
||||
case SYSRESET_COLD: |
||||
writel(0xfdb9, &cru->glb_srst_fst_value); |
||||
break; |
||||
default: |
||||
return -EPROTONOSUPPORT; |
||||
} |
||||
|
||||
return -EINPROGRESS; |
||||
} |
||||
|
||||
static struct sysreset_ops rk3399_sysreset = { |
||||
.request = rk3399_sysreset_request, |
||||
}; |
||||
|
||||
U_BOOT_DRIVER(sysreset_rk3399) = { |
||||
.name = "rk3399_sysreset", |
||||
.id = UCLASS_SYSRESET, |
||||
.ops = &rk3399_sysreset, |
||||
}; |
||||
@ -0,0 +1,47 @@ |
||||
/*
|
||||
* (C) Copyright 2017 Rockchip Electronics Co., Ltd |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0 |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <dm.h> |
||||
#include <errno.h> |
||||
#include <sysreset.h> |
||||
#include <asm/io.h> |
||||
#include <asm/arch/clock.h> |
||||
#include <asm/arch/cru_rk3328.h> |
||||
#include <asm/arch/hardware.h> |
||||
#include <linux/err.h> |
||||
|
||||
int rockchip_sysreset_request(struct udevice *dev, enum sysreset_t type) |
||||
{ |
||||
struct sysreset_reg *offset = dev_get_priv(dev); |
||||
unsigned long cru_base = (unsigned long)rockchip_get_cru(); |
||||
|
||||
if (IS_ERR_VALUE(cru_base)) |
||||
return (int)cru_base; |
||||
|
||||
switch (type) { |
||||
case SYSRESET_WARM: |
||||
writel(0xeca8, cru_base + offset->glb_srst_snd_value); |
||||
break; |
||||
case SYSRESET_COLD: |
||||
writel(0xfdb9, cru_base + offset->glb_srst_fst_value); |
||||
break; |
||||
default: |
||||
return -EPROTONOSUPPORT; |
||||
} |
||||
|
||||
return -EINPROGRESS; |
||||
} |
||||
|
||||
static struct sysreset_ops rockchip_sysreset = { |
||||
.request = rockchip_sysreset_request, |
||||
}; |
||||
|
||||
U_BOOT_DRIVER(sysreset_rockchip) = { |
||||
.name = "rockchip_sysreset", |
||||
.id = UCLASS_SYSRESET, |
||||
.ops = &rockchip_sysreset, |
||||
}; |
||||
@ -1,46 +0,0 @@ |
||||
/*
|
||||
* (C) Copyright 2015 Rockchip Electronics Co., Ltd |
||||
* Author: Andy Yan <andy.yan@rock-chips.com> |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <dm.h> |
||||
#include <errno.h> |
||||
#include <sysreset.h> |
||||
#include <asm/io.h> |
||||
#include <asm/arch/clock.h> |
||||
#include <asm/arch/cru_rv1108.h> |
||||
#include <asm/arch/hardware.h> |
||||
#include <linux/err.h> |
||||
|
||||
int rv1108_sysreset_request(struct udevice *dev, enum sysreset_t type) |
||||
{ |
||||
struct rv1108_cru *cru = rockchip_get_cru(); |
||||
|
||||
if (IS_ERR(cru)) |
||||
return PTR_ERR(cru); |
||||
|
||||
switch (type) { |
||||
case SYSRESET_WARM: |
||||
writel(0xeca8, &cru->glb_srst_snd_val); |
||||
break; |
||||
case SYSRESET_COLD: |
||||
writel(0xfdb9, &cru->glb_srst_fst_val); |
||||
break; |
||||
default: |
||||
return -EPROTONOSUPPORT; |
||||
} |
||||
|
||||
return -EINPROGRESS; |
||||
} |
||||
|
||||
static struct sysreset_ops rv1108_sysreset = { |
||||
.request = rv1108_sysreset_request, |
||||
}; |
||||
|
||||
U_BOOT_DRIVER(sysreset_rv1108) = { |
||||
.name = "rv1108_sysreset", |
||||
.id = UCLASS_SYSRESET, |
||||
.ops = &rv1108_sysreset, |
||||
}; |
||||
Loading…
Reference in new issue