@ -67,8 +67,8 @@ const struct pad_conf_entry core_padconf_array_essential_x15[] = {
{ GPMC_WEN , ( M14 | PIN_INPUT_PULLUP ) } , /* gpmc_wen.gpio2_25 */
{ GPMC_BEN0 , ( M9 | PIN_INPUT_PULLDOWN ) } , /* gpmc_ben0.dma_evt3 */
{ GPMC_BEN1 , ( M9 | PIN_INPUT_PULLDOWN ) } , /* gpmc_ben1.dma_evt4 */
{ GPMC_WAIT0 , ( M14 | PIN_INPUT_PULLUP ) } , /* gpmc_wait0.gpio2_28 */
{ VIN1B_CLK1 , ( M14 | PIN_INPUT_PULLDOWN ) } , /* vin1b_clk1.gpio2_31 */
{ GPMC_WAIT0 , ( M14 | PIN_INPUT_PULLUP | SLEWCONTROL ) } , /* gpmc_wait0.gpio2_28 */
{ VIN1B_CLK1 , ( M14 | PIN_INPUT_SLEW ) } , /* vin1b_clk1.gpio2_31 */
{ VIN1A_D2 , ( M14 | PIN_INPUT_PULLDOWN ) } , /* vin1a_d2.gpio3_6 */
{ VIN1A_D3 , ( M14 | PIN_INPUT_PULLDOWN ) } , /* vin1a_d3.gpio3_7 */
{ VIN1A_D4 , ( M14 | PIN_INPUT_PULLDOWN ) } , /* vin1a_d4.gpio3_8 */
@ -87,14 +87,14 @@ const struct pad_conf_entry core_padconf_array_essential_x15[] = {
{ VIN2A_CLK0 , ( M14 | PIN_INPUT_PULLDOWN ) } , /* vin2a_clk0.gpio3_28 */
{ VIN2A_DE0 , ( M14 | PIN_INPUT_PULLDOWN ) } , /* vin2a_de0.gpio3_29 */
{ VIN2A_FLD0 , ( M14 | PIN_INPUT_PULLDOWN ) } , /* vin2a_fld0.gpio3_30 */
{ VIN2A_HSYNC0 , ( M11 | PIN_INPUT_PULLDOWN ) } , /* vin2a_hsync0.pr1_uart0_cts_n */
{ VIN2A_HSYNC0 , ( M11 | PIN_INPUT_PULLUP ) } , /* vin2a_hsync0.pr1_uart0_cts_n */
{ VIN2A_VSYNC0 , ( M11 | PIN_OUTPUT_PULLUP ) } , /* vin2a_vsync0.pr1_uart0_rts_n */
{ VIN2A_D0 , ( M11 | PIN_INPUT_PULLDOWN ) } , /* vin2a_d0.pr1_uart0_rxd */
{ VIN2A_D1 , ( M11 | PIN_OUTPUT_PULLDOWN ) } , /* vin2a_d1.pr1_uart0_txd */
{ VIN2A_D2 , ( M8 | PIN_INPUT_PULLDOWN ) } , /* vin2a_d2.uart10_rxd */
{ VIN2A_D3 , ( M8 | PIN_OUTPUT_PULLDOWN ) } , /* vin2a_d3.uart10_txd */
{ VIN2A_D4 , ( M8 | PIN_INPUT_PULLDOWN ) } , /* vin2a_d4.uart10_ctsn */
{ VIN2A_D5 , ( M8 | PIN_OUTPUT_PULLDOWN ) } , /* vin2a_d5.uart10_rtsn */
{ VIN2A_D0 , ( M11 | PIN_INPUT_PULLUP ) } , /* vin2a_d0.pr1_uart0_rxd */
{ VIN2A_D1 , ( M11 | PIN_OUTPUT ) } , /* vin2a_d1.pr1_uart0_txd */
{ VIN2A_D2 , ( M8 | PIN_INPUT_PULLUP ) } , /* vin2a_d2.uart10_rxd */
{ VIN2A_D3 , ( M8 | PIN_OUTPUT ) } , /* vin2a_d3.uart10_txd */
{ VIN2A_D4 , ( M8 | PIN_INPUT_PULLUP ) } , /* vin2a_d4.uart10_ctsn */
{ VIN2A_D5 , ( M8 | PIN_OUTPUT_PULLUP ) } , /* vin2a_d5.uart10_rtsn */
{ VIN2A_D6 , ( M14 | PIN_INPUT_PULLDOWN ) } , /* vin2a_d6.gpio4_7 */
{ VIN2A_D7 , ( M14 | PIN_INPUT_PULLDOWN ) } , /* vin2a_d7.gpio4_8 */
{ VIN2A_D8 , ( M14 | PIN_INPUT_PULLDOWN ) } , /* vin2a_d8.gpio4_9 */
@ -113,40 +113,12 @@ const struct pad_conf_entry core_padconf_array_essential_x15[] = {
{ VIN2A_D21 , ( M3 | PIN_INPUT | MANUAL_MODE ) } , /* vin2a_d21.rgmii1_rxd2 */
{ VIN2A_D22 , ( M3 | PIN_INPUT | MANUAL_MODE ) } , /* vin2a_d22.rgmii1_rxd1 */
{ VIN2A_D23 , ( M3 | PIN_INPUT | MANUAL_MODE ) } , /* vin2a_d23.rgmii1_rxd0 */
{ VOUT1_CLK , ( M0 | PIN_OUTPUT ) } , /* vout1_clk.vout1_clk */
{ VOUT1_DE , ( M0 | PIN_OUTPUT ) } , /* vout1_de.vout1_de */
{ VOUT1_FLD , ( M14 | PIN_INPUT ) } , /* vout1_fld.gpio4_21 */
{ VOUT1_HSYNC , ( M0 | PIN_OUTPUT ) } , /* vout1_hsync.vout1_hsync */
{ VOUT1_VSYNC , ( M0 | PIN_OUTPUT ) } , /* vout1_vsync.vout1_vsync */
{ VOUT1_D0 , ( M0 | PIN_OUTPUT ) } , /* vout1_d0.vout1_d0 */
{ VOUT1_D1 , ( M0 | PIN_OUTPUT ) } , /* vout1_d1.vout1_d1 */
{ VOUT1_D2 , ( M0 | PIN_OUTPUT ) } , /* vout1_d2.vout1_d2 */
{ VOUT1_D3 , ( M0 | PIN_OUTPUT ) } , /* vout1_d3.vout1_d3 */
{ VOUT1_D4 , ( M0 | PIN_OUTPUT ) } , /* vout1_d4.vout1_d4 */
{ VOUT1_D5 , ( M0 | PIN_OUTPUT ) } , /* vout1_d5.vout1_d5 */
{ VOUT1_D6 , ( M0 | PIN_OUTPUT ) } , /* vout1_d6.vout1_d6 */
{ VOUT1_D7 , ( M0 | PIN_OUTPUT ) } , /* vout1_d7.vout1_d7 */
{ VOUT1_D8 , ( M0 | PIN_OUTPUT ) } , /* vout1_d8.vout1_d8 */
{ VOUT1_D9 , ( M0 | PIN_OUTPUT ) } , /* vout1_d9.vout1_d9 */
{ VOUT1_D10 , ( M0 | PIN_OUTPUT ) } , /* vout1_d10.vout1_d10 */
{ VOUT1_D11 , ( M0 | PIN_OUTPUT ) } , /* vout1_d11.vout1_d11 */
{ VOUT1_D12 , ( M0 | PIN_OUTPUT ) } , /* vout1_d12.vout1_d12 */
{ VOUT1_D13 , ( M0 | PIN_OUTPUT ) } , /* vout1_d13.vout1_d13 */
{ VOUT1_D14 , ( M0 | PIN_OUTPUT ) } , /* vout1_d14.vout1_d14 */
{ VOUT1_D15 , ( M0 | PIN_OUTPUT ) } , /* vout1_d15.vout1_d15 */
{ VOUT1_D16 , ( M0 | PIN_OUTPUT ) } , /* vout1_d16.vout1_d16 */
{ VOUT1_D17 , ( M0 | PIN_OUTPUT ) } , /* vout1_d17.vout1_d17 */
{ VOUT1_D18 , ( M0 | PIN_OUTPUT ) } , /* vout1_d18.vout1_d18 */
{ VOUT1_D19 , ( M0 | PIN_OUTPUT ) } , /* vout1_d19.vout1_d19 */
{ VOUT1_D20 , ( M0 | PIN_OUTPUT ) } , /* vout1_d20.vout1_d20 */
{ VOUT1_D21 , ( M0 | PIN_OUTPUT ) } , /* vout1_d21.vout1_d21 */
{ VOUT1_D22 , ( M0 | PIN_OUTPUT ) } , /* vout1_d22.vout1_d22 */
{ VOUT1_D23 , ( M0 | PIN_OUTPUT ) } , /* vout1_d23.vout1_d23 */
{ MDIO_MCLK , ( M0 | PIN_OUTPUT ) } , /* mdio_mclk.mdio_mclk */
{ MDIO_D , ( M0 | PIN_INPUT ) } , /* mdio_d.mdio_d */
{ MDIO_MCLK , ( M0 | PIN_OUTPUT | SLEWCONTROL ) } , /* mdio_mclk.mdio_mclk */
{ MDIO_D , ( M0 | PIN_INPUT | SLEWCONTROL ) } , /* mdio_d.mdio_d */
{ RMII_MHZ_50_CLK , ( M14 | PIN_INPUT_PULLUP ) } , /* RMII_MHZ_50_CLK.gpio5_17 */
{ UART3_RXD , ( M14 | PIN_INPUT_PULLDOWN ) } , /* uart3_rxd.gpio5_18 */
{ UART3_TXD , ( M14 | PIN_INPUT_PULLDOWN ) } , /* uart3_txd.gpio5_19 */
{ UART3_RXD , ( M14 | PIN_INPUT_SLEW ) } , /* uart3_rxd.gpio5_18 */
{ UART3_TXD , ( M14 | PIN_INPUT_SLEW ) } , /* uart3_txd.gpio5_19 */
{ RGMII0_TXC , ( M0 | PIN_OUTPUT | MANUAL_MODE ) } , /* rgmii0_txc.rgmii0_txc */
{ RGMII0_TXCTL , ( M0 | PIN_OUTPUT | MANUAL_MODE ) } , /* rgmii0_txctl.rgmii0_txctl */
{ RGMII0_TXD3 , ( M0 | PIN_OUTPUT | MANUAL_MODE ) } , /* rgmii0_txd3.rgmii0_txd3 */
@ -159,8 +131,8 @@ const struct pad_conf_entry core_padconf_array_essential_x15[] = {
{ RGMII0_RXD2 , ( M0 | PIN_INPUT | MANUAL_MODE ) } , /* rgmii0_rxd2.rgmii0_rxd2 */
{ RGMII0_RXD1 , ( M0 | PIN_INPUT | MANUAL_MODE ) } , /* rgmii0_rxd1.rgmii0_rxd1 */
{ RGMII0_RXD0 , ( M0 | PIN_INPUT | MANUAL_MODE ) } , /* rgmii0_rxd0.rgmii0_rxd0 */
{ USB1_DRVVBUS , ( M0 | PIN_OUTPUT ) } , /* usb1_drvvbus.usb1_drvvbus */
{ USB2_DRVVBUS , ( M0 | PIN_OUTPUT_PULLDOWN ) } , /* usb2_drvvbus.usb2_drvvbus */
{ USB1_DRVVBUS , ( M0 | PIN_OUTPUT | SLEWCONTROL ) } , /* usb1_drvvbus.usb1_drvvbus */
{ USB2_DRVVBUS , ( M0 | PIN_OUTPUT_PULLDOWN | SLEWCONTROL ) } , /* usb2_drvvbus.usb2_drvvbus */
{ GPIO6_14 , ( M10 | PIN_INPUT_PULLUP ) } , /* gpio6_14.timer1 */
{ GPIO6_15 , ( M10 | PIN_INPUT_PULLUP ) } , /* gpio6_15.timer2 */
{ GPIO6_16 , ( M10 | PIN_INPUT_PULLUP ) } , /* gpio6_16.timer3 */
@ -169,48 +141,36 @@ const struct pad_conf_entry core_padconf_array_essential_x15[] = {
{ XREF_CLK2 , ( M14 | PIN_INPUT_PULLDOWN ) } , /* xref_clk2.gpio6_19 */
{ XREF_CLK3 , ( M9 | PIN_OUTPUT_PULLDOWN ) } , /* xref_clk3.clkout3 */
{ MCASP1_ACLKX , ( M10 | PIN_INPUT_PULLUP ) } , /* mcasp1_aclkx.i2c3_sda */
{ MCASP1_FSX , ( M10 | PIN_INPUT_PULLUP ) } , /* mcasp1_fsx.i2c3_scl */
{ MCASP1_FSX , ( M10 | PIN_INPUT_PULLUP | SLEWCONTROL ) } , /* mcasp1_fsx.i2c3_scl */
{ MCASP1_ACLKR , ( M10 | PIN_INPUT_PULLUP ) } , /* mcasp1_aclkr.i2c4_sda */
{ MCASP1_FSR , ( M10 | PIN_INPUT_PULLUP ) } , /* mcasp1_fsr.i2c4_scl */
{ MCASP1_AXR0 , ( M10 | PIN_INPUT_PULLUP ) } , /* mcasp1_axr0.i2c5_sda */
{ MCASP1_AXR1 , ( M10 | PIN_INPUT_PULLUP ) } , /* mcasp1_axr1.i2c5_scl */
{ MCASP1_AXR0 , ( M10 | PIN_INPUT_PULLUP | SLEWCONTROL ) } , /* mcasp1_axr0.i2c5_sda */
{ MCASP1_AXR1 , ( M10 | PIN_INPUT_PULLUP | SLEWCONTROL ) } , /* mcasp1_axr1.i2c5_scl */
{ MCASP1_AXR2 , ( M14 | PIN_INPUT_PULLDOWN ) } , /* mcasp1_axr2.gpio5_4 */
{ MCASP1_AXR3 , ( M14 | PIN_INPUT_PULLDOWN ) } , /* mcasp1_axr3.gpio5_5 */
{ MCASP1_AXR4 , ( M14 | PIN_INPUT_PULLDOWN ) } , /* mcasp1_axr4.gpio5_6 */
{ MCASP1_AXR5 , ( M14 | PIN_INPUT_PULLDOWN ) } , /* mcasp1_axr5.gpio5_7 */
{ MCASP1_AXR6 , ( M14 | PIN_INPUT_PULLDOWN ) } , /* mcasp1_axr6.gpio5_8 */
{ MCASP1_AXR7 , ( M14 | PIN_INPUT_PULLDOWN ) } , /* mcasp1_axr7.gpio5_9 */
{ MCASP1_AXR8 , ( M14 | PIN_INPUT ) } , /* mcasp1_axr8.gpio5_10 */
{ MCASP1_AXR9 , ( M14 | PIN_INPUT ) } , /* mcasp1_axr9.gpio5_11 */
{ MCASP1_AXR10 , ( M14 | PIN_INPUT ) } , /* mcasp1_axr10.gpio5_12 */
{ MCASP1_AXR11 , ( M14 | PIN_INPUT_PULLUP ) } , /* mcasp1_axr11.gpio4_17 */
{ MCASP1_AXR12 , ( M1 | PIN_INPUT | VIRTUAL_MODE10 ) } , /* mcasp1_axr12.mcasp7_axr0 */
{ MCASP1_AXR13 , ( M1 | PIN_INPUT | VIRTUAL_MODE10 ) } , /* mcasp1_axr13.mcasp7_axr1 */
{ MCASP1_AXR14 , ( M1 | PIN_INPUT | VIRTUAL_MODE10 ) } , /* mcasp1_axr14.mcasp7_aclkx */
{ MCASP1_AXR15 , ( M1 | PIN_INPUT | VIRTUAL_MODE10 ) } , /* mcasp1_axr15.mcasp7_fsx */
{ MCASP2_ACLKX , ( M0 | PIN_INPUT_PULLDOWN ) } , /* mcasp2_aclkx.mcasp2_aclkx */
{ MCASP2_FSX , ( M0 | PIN_INPUT ) } , /* mcasp2_fsx.mcasp2_fsx */
{ MCASP2_ACLKR , ( M0 | PIN_INPUT_PULLDOWN ) } , /* mcasp2_aclkr.mcasp2_aclkr */
{ MCASP2_FSR , ( M0 | PIN_INPUT_PULLDOWN ) } , /* mcasp2_fsr.mcasp2_fsr */
{ MCASP2_AXR0 , ( M0 | PIN_INPUT_PULLDOWN ) } , /* mcasp2_axr0.mcasp2_axr0 */
{ MCASP2_AXR1 , ( M0 | PIN_INPUT_PULLDOWN ) } , /* mcasp2_axr1.mcasp2_axr1 */
{ MCASP2_AXR2 , ( M0 | PIN_INPUT ) } , /* mcasp2_axr2.mcasp2_axr2 */
{ MCASP2_AXR3 , ( M0 | PIN_INPUT ) } , /* mcasp2_axr3.mcasp2_axr3 */
{ MCASP2_AXR4 , ( M0 | PIN_INPUT_PULLDOWN ) } , /* mcasp2_axr4.mcasp2_axr4 */
{ MCASP2_AXR5 , ( M0 | PIN_INPUT_PULLDOWN ) } , /* mcasp2_axr5.mcasp2_axr5 */
{ MCASP2_AXR6 , ( M0 | PIN_INPUT_PULLDOWN ) } , /* mcasp2_axr6.mcasp2_axr6 */
{ MCASP2_AXR7 , ( M0 | PIN_INPUT_PULLDOWN ) } , /* mcasp2_axr7.mcasp2_axr7 */
{ MCASP1_AXR8 , ( M14 | PIN_INPUT | SLEWCONTROL ) } , /* mcasp1_axr8.gpio5_10 */
{ MCASP1_AXR9 , ( M14 | PIN_INPUT | SLEWCONTROL ) } , /* mcasp1_axr9.gpio5_11 */
{ MCASP1_AXR10 , ( M14 | PIN_INPUT | SLEWCONTROL ) } , /* mcasp1_axr10.gpio5_12 */
{ MCASP1_AXR11 , ( M14 | PIN_INPUT_PULLUP | SLEWCONTROL ) } , /* mcasp1_axr11.gpio4_17 */
{ MCASP1_AXR12 , ( M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10 ) } , /* mcasp1_axr12.mcasp7_axr0 */
{ MCASP1_AXR13 , ( M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10 ) } , /* mcasp1_axr13.mcasp7_axr1 */
{ MCASP1_AXR14 , ( M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10 ) } , /* mcasp1_axr14.mcasp7_aclkx */
{ MCASP1_AXR15 , ( M1 | PIN_INPUT_SLEW | VIRTUAL_MODE10 ) } , /* mcasp1_axr15.mcasp7_fsx */
{ MCASP3_ACLKX , ( M0 | PIN_INPUT_PULLDOWN ) } , /* mcasp3_aclkx.mcasp3_aclkx */
{ MCASP3_FSX , ( M0 | PIN_INPUT_PULLDOWN ) } , /* mcasp3_fsx.mcasp3_fsx */
{ MCASP3_AXR0 , ( M0 | PIN_INPUT_PULLDOWN ) } , /* mcasp3_axr0.mcasp3_axr0 */
{ MCASP3_AXR1 , ( M0 | PIN_INPUT_PULLDOWN ) } , /* mcasp3_axr1.mcasp3_axr1 */
{ MCASP3_FSX , ( M0 | PIN_INPUT_SLEW ) } , /* mcasp3_fsx.mcasp3_fsx */
{ MCASP3_AXR0 , ( M0 | PIN_INPUT_SLEW ) } , /* mcasp3_axr0.mcasp3_axr0 */
{ MCASP3_AXR1 , ( M0 | PIN_INPUT_SLEW ) } , /* mcasp3_axr1.mcasp3_axr1 */
{ MCASP4_ACLKX , ( M3 | PIN_INPUT_PULLUP ) } , /* mcasp4_aclkx.uart8_rxd */
{ MCASP4_FSX , ( M3 | PIN_OUTPUT_PULLDOWN ) } , /* mcasp4_fsx.uart8_txd */
{ MCASP4_AXR0 , ( M3 | PIN_INPUT_PULLDOWN ) } , /* mcasp4_axr0.uart8_ctsn */
{ MCASP4_FSX , ( M3 | PIN_OUTPUT ) } , /* mcasp4_fsx.uart8_txd */
{ MCASP4_AXR0 , ( M3 | PIN_INPUT_PULLUP ) } , /* mcasp4_axr0.uart8_ctsn */
{ MCASP4_AXR1 , ( M3 | PIN_OUTPUT_PULLUP ) } , /* mcasp4_axr1.uart8_rtsn */
{ MCASP5_ACLKX , ( M3 | PIN_INPUT_PULLUP ) } , /* mcasp5_aclkx.uart9_rxd */
{ MCASP5_FSX , ( M3 | PIN_OUTPUT_PULLDOWN ) } , /* mcasp5_fsx.uart9_txd */
{ MCASP5_AXR0 , ( M3 | PIN_INPUT_PULLDOWN ) } , /* mcasp5_axr0.uart9_ctsn */
{ MCASP5_FSX , ( M3 | PIN_OUTPUT ) } , /* mcasp5_fsx.uart9_txd */
{ MCASP5_AXR0 , ( M3 | PIN_INPUT_PULLUP ) } , /* mcasp5_axr0.uart9_ctsn */
{ MCASP5_AXR1 , ( M3 | PIN_OUTPUT_PULLUP ) } , /* mcasp5_axr1.uart9_rtsn */
{ MMC1_CLK , ( M0 | PIN_INPUT_PULLUP ) } , /* mmc1_clk.mmc1_clk */
{ MMC1_CMD , ( M0 | PIN_INPUT_PULLUP ) } , /* mmc1_cmd.mmc1_cmd */
@ -218,7 +178,7 @@ const struct pad_conf_entry core_padconf_array_essential_x15[] = {
{ MMC1_DAT1 , ( M0 | PIN_INPUT_PULLUP ) } , /* mmc1_dat1.mmc1_dat1 */
{ MMC1_DAT2 , ( M0 | PIN_INPUT_PULLUP ) } , /* mmc1_dat2.mmc1_dat2 */
{ MMC1_DAT3 , ( M0 | PIN_INPUT_PULLUP ) } , /* mmc1_dat3.mmc1_dat3 */
{ MMC1_SDCD , ( M14 | PIN_INPUT_PULLUP ) } , /* mmc1_sdcd.gpio6_27 */
{ MMC1_SDCD , ( M14 | PIN_INPUT_PULLUP | SLEWCONTROL ) } , /* mmc1_sdcd.gpio6_27 */
{ GPIO6_10 , ( M10 | PIN_OUTPUT_PULLDOWN ) } , /* gpio6_10.ehrpwm2A */
{ GPIO6_11 , ( M0 | PIN_INPUT_PULLUP ) } , /* gpio6_11.gpio6_11 */
{ MMC3_CLK , ( M0 | PIN_INPUT_PULLUP | MANUAL_MODE ) } , /* mmc3_clk.mmc3_clk */
@ -227,31 +187,31 @@ const struct pad_conf_entry core_padconf_array_essential_x15[] = {
{ MMC3_DAT1 , ( M0 | PIN_INPUT_PULLUP | MANUAL_MODE ) } , /* mmc3_dat1.mmc3_dat1 */
{ MMC3_DAT2 , ( M0 | PIN_INPUT_PULLUP | MANUAL_MODE ) } , /* mmc3_dat2.mmc3_dat2 */
{ MMC3_DAT3 , ( M0 | PIN_INPUT_PULLUP | MANUAL_MODE ) } , /* mmc3_dat3.mmc3_dat3 */
{ MMC3_DAT4 , ( M1 | PIN_OUTPUT_PULLDOWN ) } , /* mmc3_dat4.spi4_sclk */
{ MMC3_DAT5 , ( M1 | PIN_INPUT_PULLDOWN ) } , /* mmc3_dat5.spi4_d1 */
{ MMC3_DAT6 , ( M1 | PIN_INPUT_PULLDOWN ) } , /* mmc3_dat6.spi4_d0 */
{ MMC3_DAT7 , ( M1 | PIN_OUTPUT_PULLUP ) } , /* mmc3_dat7.spi4_cs0 */
{ MMC3_DAT4 , ( M0 | PIN_INPUT_PULLUP | MANUAL_MODE ) } , /* mmc3_dat4.mmc3_dat4 */
{ MMC3_DAT5 , ( M0 | PIN_INPUT_PULLUP | MANUAL_MODE ) } , /* mmc3_dat5.mmc3_dat5 */
{ MMC3_DAT6 , ( M0 | PIN_INPUT_PULLUP | MANUAL_MODE ) } , /* mmc3_dat6.mmc3_dat6 */
{ MMC3_DAT7 , ( M0 | PIN_INPUT_PULLUP | MANUAL_MODE ) } , /* mmc3_dat7.mmc3_dat7 */
{ SPI1_SCLK , ( M14 | PIN_INPUT_PULLDOWN ) } , /* spi1_sclk.gpio7_7 */
{ SPI1_D1 , ( M14 | PIN_INPUT_PULLDOWN ) } , /* spi1_d1.gpio7_8 */
{ SPI1_D0 , ( M14 | PIN_INPUT_PULLDOWN ) } , /* spi1_d0.gpio7_9 */
{ SPI1_CS0 , ( M14 | PIN_INPUT ) } , /* spi1_cs0.gpio7_10 */
{ SPI1_CS1 , ( M14 | PIN_INPUT ) } , /* spi1_cs1.gpio7_11 */
{ SPI1_CS2 , ( M14 | PIN_INPUT_PULLDOWN ) } , /* spi1_cs2.gpio7_12 */
{ SPI1_CS3 , ( M6 | PIN_INPUT_PULLUP ) } , /* spi1_cs3.hdmi1_cec */
{ SPI1_CS2 , ( M14 | PIN_INPUT_SLEW ) } , /* spi1_cs2.gpio7_12 */
{ SPI1_CS3 , ( M6 | PIN_INPUT_PULLUP | SLEWCONTROL ) } , /* spi1_cs3.hdmi1_cec */
{ SPI2_SCLK , ( M14 | PIN_INPUT_PULLDOWN ) } , /* spi2_sclk.gpio7_14 */
{ SPI2_D1 , ( M14 | PIN_INPUT_PULLDOWN ) } , /* spi2_d1.gpio7_15 */
{ SPI2_D0 , ( M14 | PIN_INPUT_PULLUP ) } , /* spi2_d0.gpio7_16 */
{ SPI2_CS0 , ( M14 | PIN_INPUT_PULLUP ) } , /* spi2_cs0.gpio7_17 */
{ DCAN1_TX , ( M15 | PULL_UP ) } , /* dcan1_tx.safe for dcan1_tx */
{ DCAN1_RX , ( M15 | PULL_UP ) } , /* dcan1_rx.safe for dcan1_rx */
{ UART1_RXD , ( M0 | PIN_INPUT_PULLUP ) } , /* uart1_rxd.uart1_rxd */
{ UART1_TXD , ( M0 | PIN_OUTPUT_PULLDOWN ) } , /* uart1_txd.uart1_txd */
{ SPI2_D1 , ( M14 | PIN_INPUT_SLEW ) } , /* spi2_d1.gpio7_15 */
{ SPI2_D0 , ( M14 | PIN_INPUT_PULLUP | SLEWCONTROL ) } , /* spi2_d0.gpio7_16 */
{ SPI2_CS0 , ( M14 | PIN_INPUT_PULLUP | SLEWCONTROL ) } , /* spi2_cs0.gpio7_17 */
{ DCAN1_TX , ( M0 | PIN_O UTPUT | S LEWCONTRO L ) } , /* dcan1_tx.dcan1_tx */
{ DCAN1_RX , ( M0 | PIN_INP UT | S LEWCONTRO L ) } , /* dcan1_rx.dcan1_rx */
{ UART1_RXD , ( M0 | PIN_INPUT_PULLUP | SLEWCONTROL ) } , /* uart1_rxd.uart1_rxd */
{ UART1_TXD , ( M0 | PIN_OUTPUT | SLEWCONTROL ) } , /* uart1_txd.uart1_txd */
{ UART1_CTSN , ( M14 | PIN_INPUT_PULLDOWN ) } , /* uart1_ctsn.gpio7_24 */
{ UART1_RTSN , ( M14 | PIN_INPUT ) } , /* uart1_rtsn.gpio7_25 */
{ UART2_RXD , ( M14 | PIN_INPUT_PULLDOWN ) } , /* uart2_rxd.gpio7_26 */
{ UART2_TXD , ( M14 | PIN_INPUT_PULLDOWN ) } , /* uart2_txd.gpio7_27 */
{ UART2_CTSN , ( M2 | PIN_INPUT_PULLUP ) } , /* uart2_ctsn.uart3_rxd */
{ UART2_RTSN , ( M1 | PIN_OUTPUT_PULLDOWN ) } , /* uart2_rtsn.uart3_txd */
{ UART2_RTSN , ( M1 | PIN_OUTPUT ) } , /* uart2_rtsn.uart3_txd */
{ I2C1_SDA , ( M0 | PIN_INPUT_PULLUP ) } , /* i2c1_sda.i2c1_sda */
{ I2C1_SCL , ( M0 | PIN_INPUT_PULLUP ) } , /* i2c1_scl.i2c1_scl */
{ I2C2_SDA , ( M1 | PIN_INPUT_PULLUP ) } , /* i2c2_sda.hdmi1_ddc_scl */
@ -263,7 +223,7 @@ const struct pad_conf_entry core_padconf_array_essential_x15[] = {
{ ON_OFF , ( M0 | PIN_OUTPUT ) } , /* on_off.on_off */
{ RTC_PORZ , ( M0 | PIN_INPUT ) } , /* rtc_porz.rtc_porz */
{ TMS , ( M0 | PIN_INPUT_PULLUP ) } , /* tms.tms */
{ TDI , ( M0 | PIN_INPUT_PULLUP ) } , /* tdi.tdi */
{ TDI , ( M0 | PIN_INPUT_PULLUP | SLEWCONTROL ) } , /* tdi.tdi */
{ TDO , ( M0 | PIN_OUTPUT ) } , /* tdo.tdo */
{ TCLK , ( M0 | PIN_INPUT_PULLDOWN ) } , /* tclk.tclk */
{ TRSTN , ( M0 | PIN_INPUT ) } , /* trstn.trstn */
@ -275,11 +235,67 @@ const struct pad_conf_entry core_padconf_array_essential_x15[] = {
} ;
const struct pad_conf_entry core_padconf_array_delta_x15_sr1_1 [ ] = {
{ MMC1_SDWP , ( M14 | PIN_OUTPUT ) } , /* mmc1_sdwp.gpio6_28 */
{ MMC1_SDWP , ( M14 | PIN_INPUT | SLEWCONTROL ) } , /* mmc1_sdwp.gpio6_28 */
{ VOUT1_CLK , ( M0 | PIN_OUTPUT | SLEWCONTROL ) } , /* vout1_clk.vout1_clk */
{ VOUT1_DE , ( M0 | PIN_OUTPUT | SLEWCONTROL ) } , /* vout1_de.vout1_de */
{ VOUT1_HSYNC , ( M0 | PIN_OUTPUT | SLEWCONTROL ) } , /* vout1_hsync.vout1_hsync */
{ VOUT1_VSYNC , ( M0 | PIN_OUTPUT | SLEWCONTROL ) } , /* vout1_vsync.vout1_vsync */
{ VOUT1_D0 , ( M0 | PIN_OUTPUT | SLEWCONTROL ) } , /* vout1_d0.vout1_d0 */
{ VOUT1_D1 , ( M0 | PIN_OUTPUT | SLEWCONTROL ) } , /* vout1_d1.vout1_d1 */
{ VOUT1_D2 , ( M0 | PIN_OUTPUT | SLEWCONTROL ) } , /* vout1_d2.vout1_d2 */
{ VOUT1_D3 , ( M0 | PIN_OUTPUT | SLEWCONTROL ) } , /* vout1_d3.vout1_d3 */
{ VOUT1_D4 , ( M0 | PIN_OUTPUT | SLEWCONTROL ) } , /* vout1_d4.vout1_d4 */
{ VOUT1_D5 , ( M0 | PIN_OUTPUT | SLEWCONTROL ) } , /* vout1_d5.vout1_d5 */
{ VOUT1_D6 , ( M0 | PIN_OUTPUT | SLEWCONTROL ) } , /* vout1_d6.vout1_d6 */
{ VOUT1_D7 , ( M0 | PIN_OUTPUT | SLEWCONTROL ) } , /* vout1_d7.vout1_d7 */
{ VOUT1_D8 , ( M0 | PIN_OUTPUT | SLEWCONTROL ) } , /* vout1_d8.vout1_d8 */
{ VOUT1_D9 , ( M0 | PIN_OUTPUT | SLEWCONTROL ) } , /* vout1_d9.vout1_d9 */
{ VOUT1_D10 , ( M0 | PIN_OUTPUT | SLEWCONTROL ) } , /* vout1_d10.vout1_d10 */
{ VOUT1_D11 , ( M0 | PIN_OUTPUT | SLEWCONTROL ) } , /* vout1_d11.vout1_d11 */
{ VOUT1_D12 , ( M0 | PIN_OUTPUT | SLEWCONTROL ) } , /* vout1_d12.vout1_d12 */
{ VOUT1_D13 , ( M0 | PIN_OUTPUT | SLEWCONTROL ) } , /* vout1_d13.vout1_d13 */
{ VOUT1_D14 , ( M0 | PIN_OUTPUT | SLEWCONTROL ) } , /* vout1_d14.vout1_d14 */
{ VOUT1_D15 , ( M0 | PIN_OUTPUT | SLEWCONTROL ) } , /* vout1_d15.vout1_d15 */
{ VOUT1_D16 , ( M0 | PIN_OUTPUT | SLEWCONTROL ) } , /* vout1_d16.vout1_d16 */
{ VOUT1_D17 , ( M0 | PIN_OUTPUT | SLEWCONTROL ) } , /* vout1_d17.vout1_d17 */
{ VOUT1_D18 , ( M0 | PIN_OUTPUT | SLEWCONTROL ) } , /* vout1_d18.vout1_d18 */
{ VOUT1_D19 , ( M0 | PIN_OUTPUT | SLEWCONTROL ) } , /* vout1_d19.vout1_d19 */
{ VOUT1_D20 , ( M0 | PIN_OUTPUT | SLEWCONTROL ) } , /* vout1_d20.vout1_d20 */
{ VOUT1_D21 , ( M0 | PIN_OUTPUT | SLEWCONTROL ) } , /* vout1_d21.vout1_d21 */
{ VOUT1_D22 , ( M0 | PIN_OUTPUT | SLEWCONTROL ) } , /* vout1_d22.vout1_d22 */
{ VOUT1_D23 , ( M0 | PIN_OUTPUT | SLEWCONTROL ) } , /* vout1_d23.vout1_d23 */
} ;
const struct pad_conf_entry core_padconf_array_delta_x15_sr2_0 [ ] = {
{ VIN1A_CLK0 , ( M14 | PIN_INPUT ) } , /* vin1a_clk0.gpio2_30 */
{ VOUT1_CLK , ( M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE ) } , /* vout1_clk.vout1_clk */
{ VOUT1_DE , ( M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE ) } , /* vout1_de.vout1_de */
{ VOUT1_HSYNC , ( M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE ) } , /* vout1_hsync.vout1_hsync */
{ VOUT1_VSYNC , ( M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE ) } , /* vout1_vsync.vout1_vsync */
{ VOUT1_D0 , ( M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE ) } , /* vout1_d0.vout1_d0 */
{ VOUT1_D1 , ( M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE ) } , /* vout1_d1.vout1_d1 */
{ VOUT1_D2 , ( M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE ) } , /* vout1_d2.vout1_d2 */
{ VOUT1_D3 , ( M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE ) } , /* vout1_d3.vout1_d3 */
{ VOUT1_D4 , ( M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE ) } , /* vout1_d4.vout1_d4 */
{ VOUT1_D5 , ( M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE ) } , /* vout1_d5.vout1_d5 */
{ VOUT1_D6 , ( M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE ) } , /* vout1_d6.vout1_d6 */
{ VOUT1_D7 , ( M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE ) } , /* vout1_d7.vout1_d7 */
{ VOUT1_D8 , ( M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE ) } , /* vout1_d8.vout1_d8 */
{ VOUT1_D9 , ( M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE ) } , /* vout1_d9.vout1_d9 */
{ VOUT1_D10 , ( M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE ) } , /* vout1_d10.vout1_d10 */
{ VOUT1_D11 , ( M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE ) } , /* vout1_d11.vout1_d11 */
{ VOUT1_D12 , ( M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE ) } , /* vout1_d12.vout1_d12 */
{ VOUT1_D13 , ( M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE ) } , /* vout1_d13.vout1_d13 */
{ VOUT1_D14 , ( M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE ) } , /* vout1_d14.vout1_d14 */
{ VOUT1_D15 , ( M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE ) } , /* vout1_d15.vout1_d15 */
{ VOUT1_D16 , ( M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE ) } , /* vout1_d16.vout1_d16 */
{ VOUT1_D17 , ( M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE ) } , /* vout1_d17.vout1_d17 */
{ VOUT1_D18 , ( M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE ) } , /* vout1_d18.vout1_d18 */
{ VOUT1_D19 , ( M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE ) } , /* vout1_d19.vout1_d19 */
{ VOUT1_D20 , ( M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE ) } , /* vout1_d20.vout1_d20 */
{ VOUT1_D21 , ( M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE ) } , /* vout1_d21.vout1_d21 */
{ VOUT1_D22 , ( M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE ) } , /* vout1_d22.vout1_d22 */
{ VOUT1_D23 , ( M0 | PIN_OUTPUT | SLEWCONTROL | MANUAL_MODE ) } , /* vout1_d23.vout1_d23 */
} ;
const struct pad_conf_entry core_padconf_array_essential_am572x_idk [ ] = {
@ -795,6 +811,36 @@ const struct iodelay_cfg_entry iodelay_cfg_array_x15_sr1_1[] = {
{ 0x0300 , 2389 , 0 } , /* CFG_GPMC_AD7_IN */
{ 0x030C , 2672 , 0 } , /* CFG_GPMC_AD8_IN */
{ 0x0318 , 2334 , 0 } , /* CFG_GPMC_AD9_IN */
{ 0x0378 , 0 , 0 } , /* CFG_GPMC_CS3_IN */
{ 0x0678 , 406 , 0 } , /* CFG_MMC3_CLK_IN */
{ 0x0680 , 659 , 0 } , /* CFG_MMC3_CLK_OUT */
{ 0x0684 , 0 , 0 } , /* CFG_MMC3_CMD_IN */
{ 0x0688 , 0 , 0 } , /* CFG_MMC3_CMD_OEN */
{ 0x068C , 0 , 0 } , /* CFG_MMC3_CMD_OUT */
{ 0x0690 , 130 , 0 } , /* CFG_MMC3_DAT0_IN */
{ 0x0694 , 0 , 0 } , /* CFG_MMC3_DAT0_OEN */
{ 0x0698 , 0 , 0 } , /* CFG_MMC3_DAT0_OUT */
{ 0x069C , 169 , 0 } , /* CFG_MMC3_DAT1_IN */
{ 0x06A0 , 0 , 0 } , /* CFG_MMC3_DAT1_OEN */
{ 0x06A4 , 0 , 0 } , /* CFG_MMC3_DAT1_OUT */
{ 0x06A8 , 0 , 0 } , /* CFG_MMC3_DAT2_IN */
{ 0x06AC , 0 , 0 } , /* CFG_MMC3_DAT2_OEN */
{ 0x06B0 , 0 , 0 } , /* CFG_MMC3_DAT2_OUT */
{ 0x06B4 , 457 , 0 } , /* CFG_MMC3_DAT3_IN */
{ 0x06B8 , 0 , 0 } , /* CFG_MMC3_DAT3_OEN */
{ 0x06BC , 0 , 0 } , /* CFG_MMC3_DAT3_OUT */
{ 0x06C0 , 702 , 0 } , /* CFG_MMC3_DAT4_IN */
{ 0x06C4 , 0 , 0 } , /* CFG_MMC3_DAT4_OEN */
{ 0x06C8 , 0 , 0 } , /* CFG_MMC3_DAT4_OUT */
{ 0x06CC , 738 , 0 } , /* CFG_MMC3_DAT5_IN */
{ 0x06D0 , 0 , 0 } , /* CFG_MMC3_DAT5_OEN */
{ 0x06D4 , 0 , 0 } , /* CFG_MMC3_DAT5_OUT */
{ 0x06D8 , 856 , 0 } , /* CFG_MMC3_DAT6_IN */
{ 0x06DC , 0 , 0 } , /* CFG_MMC3_DAT6_OEN */
{ 0x06E0 , 0 , 0 } , /* CFG_MMC3_DAT6_OUT */
{ 0x06E4 , 610 , 0 } , /* CFG_MMC3_DAT7_IN */
{ 0x06E8 , 0 , 0 } , /* CFG_MMC3_DAT7_OEN */
{ 0x06EC , 0 , 0 } , /* CFG_MMC3_DAT7_OUT */
{ 0x06F0 , 480 , 0 } , /* CFG_RGMII0_RXC_IN */
{ 0x06FC , 111 , 1641 } , /* CFG_RGMII0_RXCTL_IN */
{ 0x0708 , 272 , 1116 } , /* CFG_RGMII0_RXD0_IN */
@ -812,7 +858,7 @@ const struct iodelay_cfg_entry iodelay_cfg_array_x15_sr1_1[] = {
{ 0x0A88 , 876 , 0 } , /* CFG_VIN2A_D14_OUT */
{ 0x0A94 , 312 , 0 } , /* CFG_VIN2A_D15_OUT */
{ 0x0AA0 , 58 , 0 } , /* CFG_VIN2A_D16_OUT */
{ 0x0AAC , 0 , 0 } , /* CFG_VIN2A_D17_OUT */
{ 0x0AAC , 0 , 0 } , /* CFG_VIN2A_D17_OUT */
{ 0x0AB0 , 702 , 0 } , /* CFG_VIN2A_D18_IN */
{ 0x0ABC , 136 , 976 } , /* CFG_VIN2A_D19_IN */
{ 0x0AD4 , 210 , 1357 } , /* CFG_VIN2A_D20_IN */
@ -868,6 +914,18 @@ const struct iodelay_cfg_entry iodelay_cfg_array_x15_sr2_0[] = {
{ 0x06B4 , 474 , 0 } , /* CFG_MMC3_DAT3_IN */
{ 0x06B8 , 0 , 0 } , /* CFG_MMC3_DAT3_OEN */
{ 0x06BC , 0 , 0 } , /* CFG_MMC3_DAT3_OUT */
{ 0x06C0 , 792 , 0 } , /* CFG_MMC3_DAT4_IN */
{ 0x06C4 , 0 , 0 } , /* CFG_MMC3_DAT4_OEN */
{ 0x06C8 , 0 , 0 } , /* CFG_MMC3_DAT4_OUT */
{ 0x06CC , 782 , 0 } , /* CFG_MMC3_DAT5_IN */
{ 0x06D0 , 0 , 0 } , /* CFG_MMC3_DAT5_OEN */
{ 0x06D4 , 0 , 0 } , /* CFG_MMC3_DAT5_OUT */
{ 0x06D8 , 942 , 0 } , /* CFG_MMC3_DAT6_IN */
{ 0x06DC , 0 , 0 } , /* CFG_MMC3_DAT6_OEN */
{ 0x06E0 , 0 , 0 } , /* CFG_MMC3_DAT6_OUT */
{ 0x06E4 , 636 , 0 } , /* CFG_MMC3_DAT7_IN */
{ 0x06E8 , 0 , 0 } , /* CFG_MMC3_DAT7_OEN */
{ 0x06EC , 0 , 0 } , /* CFG_MMC3_DAT7_OUT */
{ 0x06F0 , 260 , 0 } , /* CFG_RGMII0_RXC_IN */
{ 0x06FC , 0 , 1412 } , /* CFG_RGMII0_RXCTL_IN */
{ 0x0708 , 123 , 1047 } , /* CFG_RGMII0_RXD0_IN */
@ -892,6 +950,34 @@ const struct iodelay_cfg_entry iodelay_cfg_array_x15_sr2_0[] = {
{ 0x0AE0 , 192 , 836 } , /* CFG_VIN2A_D21_IN */
{ 0x0AEC , 294 , 669 } , /* CFG_VIN2A_D22_IN */
{ 0x0AF8 , 50 , 700 } , /* CFG_VIN2A_D23_IN */
{ 0x0B9C , 0 , 706 } , /* CFG_VOUT1_CLK_OUT */
{ 0x0BA8 , 2313 , 0 } , /* CFG_VOUT1_D0_OUT */
{ 0x0BB4 , 2199 , 0 } , /* CFG_VOUT1_D10_OUT */
{ 0x0BC0 , 2266 , 0 } , /* CFG_VOUT1_D11_OUT */
{ 0x0BCC , 3159 , 0 } , /* CFG_VOUT1_D12_OUT */
{ 0x0BD8 , 2100 , 0 } , /* CFG_VOUT1_D13_OUT */
{ 0x0BE4 , 2229 , 0 } , /* CFG_VOUT1_D14_OUT */
{ 0x0BF0 , 2202 , 0 } , /* CFG_VOUT1_D15_OUT */
{ 0x0BFC , 2084 , 0 } , /* CFG_VOUT1_D16_OUT */
{ 0x0C08 , 2195 , 0 } , /* CFG_VOUT1_D17_OUT */
{ 0x0C14 , 2342 , 0 } , /* CFG_VOUT1_D18_OUT */
{ 0x0C20 , 2463 , 0 } , /* CFG_VOUT1_D19_OUT */
{ 0x0C2C , 2439 , 0 } , /* CFG_VOUT1_D1_OUT */
{ 0x0C38 , 2304 , 0 } , /* CFG_VOUT1_D20_OUT */
{ 0x0C44 , 2103 , 0 } , /* CFG_VOUT1_D21_OUT */
{ 0x0C50 , 2145 , 0 } , /* CFG_VOUT1_D22_OUT */
{ 0x0C5C , 1932 , 0 } , /* CFG_VOUT1_D23_OUT */
{ 0x0C68 , 2200 , 0 } , /* CFG_VOUT1_D2_OUT */
{ 0x0C74 , 2355 , 0 } , /* CFG_VOUT1_D3_OUT */
{ 0x0C80 , 3215 , 0 } , /* CFG_VOUT1_D4_OUT */
{ 0x0C8C , 2314 , 0 } , /* CFG_VOUT1_D5_OUT */
{ 0x0C98 , 2238 , 0 } , /* CFG_VOUT1_D6_OUT */
{ 0x0CA4 , 2381 , 0 } , /* CFG_VOUT1_D7_OUT */
{ 0x0CB0 , 2138 , 0 } , /* CFG_VOUT1_D8_OUT */
{ 0x0CBC , 2383 , 0 } , /* CFG_VOUT1_D9_OUT */
{ 0x0CC8 , 1984 , 0 } , /* CFG_VOUT1_DE_OUT */
{ 0x0CE0 , 1947 , 0 } , /* CFG_VOUT1_HSYNC_OUT */
{ 0x0CEC , 2739 , 0 } , /* CFG_VOUT1_VSYNC_OUT */
} ;
const struct iodelay_cfg_entry iodelay_cfg_array_am572x_idk [ ] = {