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@ -45,6 +45,10 @@ |
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#define FE_CLK_RST 0x1 |
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#define FE_CLK_ENA 0x8 |
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/* SSP2 Clock Control */ |
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#define SSP2_APBCLK 0x01 |
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#define SSP2_FNCLK 0x02 |
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/* Register Base Addresses */ |
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#define ARMD1_DRAM_BASE 0xB0000000 |
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#define ARMD1_FEC_BASE 0xC0800000 |
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@ -175,5 +179,20 @@ struct armd1apb1_registers { |
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u32 ac97; /*0x084*/ |
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}; |
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/*
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* APB2 Clock Reset/Control Registers |
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* Refer Datasheet Appendix A.11 |
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*/ |
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struct armd1apb2_registers { |
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u32 pad1[0x01C - 0x000]; |
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u32 ssp1_clkrst; /* 0x01C */ |
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u32 ssp2_clkrst; /* 0x020 */ |
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u32 pad2[0x04C - 0x020 - 4]; |
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u32 ssp3_clkrst; /* 0x04C */ |
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u32 pad3[0x058 - 0x04C - 4]; |
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u32 ssp4_clkrst; /* 0x058 */ |
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u32 ssp5_clkrst; /* 0x05C */ |
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}; |
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#endif /* CONFIG_ARMADA100 */ |
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#endif /* _ASM_ARCH_ARMADA100_H */ |
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