Tom Rini
10 years ago
commit
db7a7dee68
@ -0,0 +1,9 @@ |
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# |
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# Copyright (C) 2015 Google, Inc |
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# |
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# SPDX-License-Identifier: GPL-2.0+ |
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# |
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|
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config INTEL_BAYTRAIL |
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bool |
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select HAVE_FSP |
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@ -0,0 +1,10 @@ |
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#
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# Copyright (C) 2015 Google, Inc
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y += early_uart.o
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obj-y += fsp_configs.o
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obj-y += pci.o
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obj-y += valleyview.o
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@ -0,0 +1,77 @@ |
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/*
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* Copyright (C) 2015 Google, Inc |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <errno.h> |
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#include <asm/io.h> |
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#define PCI_DEV_CONFIG(segbus, dev, fn) ( \ |
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(((segbus) & 0xfff) << 20) | \
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(((dev) & 0x1f) << 15) | \
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(((fn) & 0x07) << 12)) |
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/* Platform Controller Unit */ |
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#define LPC_DEV 0x1f |
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#define LPC_FUNC 0 |
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/* Enable UART */ |
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#define UART_CONT 0x80 |
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/* SCORE Pad definitions */ |
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#define UART_RXD_PAD 82 |
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#define UART_TXD_PAD 83 |
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/* Pad base: PAD_CONF0[n]= PAD_BASE + 16 * n */ |
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#define GPSCORE_PAD_BASE (IO_BASE_ADDRESS + IO_BASE_OFFSET_GPSCORE) |
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/* IO Memory */ |
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#define IO_BASE_ADDRESS 0xfed0c000 |
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#define IO_BASE_OFFSET_GPSCORE 0x0000 |
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#define IO_BASE_OFFSET_GPNCORE 0x1000 |
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#define IO_BASE_OFFSET_GPSSUS 0x2000 |
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#define IO_BASE_SIZE 0x4000 |
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static inline unsigned int score_pconf0(int pad_num) |
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{ |
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return GPSCORE_PAD_BASE + pad_num * 16; |
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} |
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static void score_select_func(int pad, int func) |
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{ |
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uint32_t reg; |
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uint32_t pconf0_addr = score_pconf0(pad); |
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reg = readl(pconf0_addr); |
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reg &= ~0x7; |
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reg |= func & 0x7; |
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writel(reg, pconf0_addr); |
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} |
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static void pci_write_config32(int dev, unsigned int where, u32 value) |
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{ |
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unsigned long addr; |
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addr = CONFIG_PCIE_ECAM_BASE | dev | (where & ~3); |
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writel(value, addr); |
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} |
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/* This can be called after memory-mapped PCI is working */ |
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int setup_early_uart(void) |
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{ |
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/* Enable the legacy UART hardware. */ |
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pci_write_config32(PCI_DEV_CONFIG(0, LPC_DEV, LPC_FUNC), UART_CONT, 1); |
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/*
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* Set up the pads to the UART function. This allows the signals to |
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* leave the chip |
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*/ |
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score_select_func(UART_RXD_PAD, 1); |
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score_select_func(UART_TXD_PAD, 1); |
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/* TODO(sjg@chromium.org): Call debug_uart_init() */ |
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return 0; |
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} |
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@ -0,0 +1,156 @@ |
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/*
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* Copyright (C) 2013, Intel Corporation |
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* Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com> |
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* |
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* SPDX-License-Identifier: Intel |
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*/ |
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#include <common.h> |
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#include <asm/arch/fsp/azalia.h> |
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#include <asm/fsp/fsp_support.h> |
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|
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/* ALC262 Verb Table - 10EC0262 */ |
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static const uint32_t verb_table_data13[] = { |
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/* Pin Complex (NID 0x11) */ |
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0x01171cf0, |
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0x01171d11, |
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0x01171e11, |
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0x01171f41, |
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/* Pin Complex (NID 0x12) */ |
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0x01271cf0, |
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0x01271d11, |
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0x01271e11, |
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0x01271f41, |
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/* Pin Complex (NID 0x14) */ |
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0x01471c10, |
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0x01471d40, |
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0x01471e01, |
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0x01471f01, |
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/* Pin Complex (NID 0x15) */ |
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0x01571cf0, |
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0x01571d11, |
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0x01571e11, |
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0x01571f41, |
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/* Pin Complex (NID 0x16) */ |
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0x01671cf0, |
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0x01671d11, |
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0x01671e11, |
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0x01671f41, |
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/* Pin Complex (NID 0x18) */ |
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0x01871c20, |
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0x01871d98, |
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0x01871ea1, |
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0x01871f01, |
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/* Pin Complex (NID 0x19) */ |
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0x01971c21, |
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0x01971d98, |
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0x01971ea1, |
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0x01971f02, |
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/* Pin Complex (NID 0x1A) */ |
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0x01a71c2f, |
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0x01a71d30, |
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0x01a71e81, |
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0x01a71f01, |
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/* Pin Complex */ |
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0x01b71c1f, |
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0x01b71d40, |
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0x01b71e21, |
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0x01b71f02, |
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/* Pin Complex */ |
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0x01c71cf0, |
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0x01c71d11, |
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0x01c71e11, |
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0x01c71f41, |
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/* Pin Complex */ |
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0x01d71c01, |
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0x01d71dc6, |
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0x01d71e14, |
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0x01d71f40, |
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/* Pin Complex */ |
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0x01e71cf0, |
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0x01e71d11, |
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0x01e71e11, |
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0x01e71f41, |
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/* Pin Complex */ |
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0x01f71cf0, |
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0x01f71d11, |
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0x01f71e11, |
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0x01f71f41, |
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}; |
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/*
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* This needs to be in ROM since if we put it in CAR, FSP init loses it when |
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* it drops CAR. |
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* |
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* TODO(sjg@chromium.org): Move to device tree when FSP allows it |
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* |
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* VerbTable: (RealTek ALC262) |
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* Revision ID = 0xFF, support all steps |
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* Codec Verb Table For AZALIA |
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* Codec Address: CAd value (0/1/2) |
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* Codec Vendor: 0x10EC0262 |
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*/ |
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static const struct pch_azalia_verb_table azalia_verb_table[] = { |
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{ |
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{ |
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0x10ec0262, |
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0x0000, |
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0xff, |
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0x01, |
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0x000b, |
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0x0002, |
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}, |
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verb_table_data13 |
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} |
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}; |
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const struct pch_azalia_config azalia_config = { |
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.pme_enable = 1, |
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.docking_supported = 1, |
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.docking_attached = 0, |
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.hdmi_codec_enable = 1, |
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.azalia_v_ci_enable = 1, |
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.rsvdbits = 0, |
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.azalia_verb_table_num = 1, |
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.azalia_verb_table = azalia_verb_table, |
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.reset_wait_timer_us = 300 |
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}; |
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void update_fsp_upd(struct upd_region *fsp_upd) |
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{ |
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struct memory_down_data *mem; |
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/*
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* Configure everything here to avoid the poor hard-pressed user |
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* needing to run Intel's binary configuration tool. It may also allow |
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* us to support the 1GB single core variant easily. |
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* |
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* TODO(sjg@chromium.org): Move to device tree |
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*/ |
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fsp_upd->mrc_init_tseg_size = 8; |
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fsp_upd->mrc_init_mmio_size = 0x800; |
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fsp_upd->emmc_boot_mode = 0xff; |
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fsp_upd->enable_sdio = 1; |
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fsp_upd->enable_sdcard = 1; |
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fsp_upd->enable_hsuart0 = 1; |
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fsp_upd->azalia_config_ptr = (uint32_t)&azalia_config; |
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fsp_upd->enable_i2_c0 = 0; |
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fsp_upd->enable_i2_c2 = 0; |
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fsp_upd->enable_i2_c3 = 0; |
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fsp_upd->enable_i2_c4 = 0; |
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fsp_upd->enable_xhci = 0; |
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fsp_upd->igd_render_standby = 1; |
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mem = &fsp_upd->memory_params; |
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mem->enable_memory_down = 1; |
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mem->dram_speed = 1; |
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mem->dimm_width = 1; |
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mem->dimm_density = 2; |
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mem->dimm_tcl = 0xb; |
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mem->dimm_trpt_rcd = 0xb; |
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mem->dimm_twr = 0xc; |
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mem->dimm_twtr = 6; |
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mem->dimm_trrd = 6; |
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mem->dimm_trtp = 6; |
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mem->dimm_tfaw = 0x14; |
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} |
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@ -0,0 +1,46 @@ |
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/*
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* Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <pci.h> |
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#include <asm/pci.h> |
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#include <asm/fsp/fsp_support.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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void board_pci_setup_hose(struct pci_controller *hose) |
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{ |
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hose->first_busno = 0; |
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hose->last_busno = 0; |
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/* PCI memory space */ |
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pci_set_region(hose->regions + 0, |
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CONFIG_PCI_MEM_BUS, |
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CONFIG_PCI_MEM_PHYS, |
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CONFIG_PCI_MEM_SIZE, |
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PCI_REGION_MEM); |
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/* PCI IO space */ |
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pci_set_region(hose->regions + 1, |
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CONFIG_PCI_IO_BUS, |
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CONFIG_PCI_IO_PHYS, |
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CONFIG_PCI_IO_SIZE, |
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PCI_REGION_IO); |
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pci_set_region(hose->regions + 2, |
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CONFIG_PCI_PREF_BUS, |
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CONFIG_PCI_PREF_PHYS, |
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CONFIG_PCI_PREF_SIZE, |
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PCI_REGION_PREFETCH); |
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pci_set_region(hose->regions + 3, |
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0, |
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0, |
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gd->ram_size, |
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PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); |
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hose->region_count = 4; |
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} |
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@ -0,0 +1,38 @@ |
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/*
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* Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <mmc.h> |
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#include <pci_ids.h> |
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#include <asm/post.h> |
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static struct pci_device_id mmc_supported[] = { |
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SDIO }, |
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SDCARD }, |
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}; |
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int cpu_mmc_init(bd_t *bis) |
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{ |
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printf("mmc init\n"); |
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return pci_mmc_init("ValleyView SDHCI", mmc_supported, |
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ARRAY_SIZE(mmc_supported)); |
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} |
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int arch_cpu_init(void) |
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{ |
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int ret; |
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post_code(POST_CPU_INIT); |
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#ifdef CONFIG_SYS_X86_TSC_TIMER |
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timer_set_base(rdtsc()); |
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#endif |
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ret = x86_cpu_init_f(); |
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if (ret) |
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return ret; |
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return 0; |
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} |
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@ -0,0 +1,126 @@ |
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# |
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# Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> |
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# |
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# SPDX-License-Identifier: GPL-2.0+ |
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# |
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config INTEL_QUARK |
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bool |
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select HAVE_RMU |
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select TSC_CALIBRATION_BYPASS |
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if INTEL_QUARK |
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config HAVE_RMU |
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bool "Add a Remote Management Unit (RMU) binary" |
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help |
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Select this option to add a Remote Management Unit (RMU) binary |
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to the resulting U-Boot image. It is a data block (up to 64K) of |
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machine-specific code which must be put in the flash for the RMU |
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within the Quark SoC processor to access when powered up before |
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system BIOS is executed. |
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|
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config RMU_FILE |
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string "Remote Management Unit (RMU) binary filename" |
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depends on HAVE_RMU |
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default "rmu.bin" |
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help |
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The filename of the file to use as Remote Management Unit (RMU) |
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binary in the board directory. |
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|
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config RMU_ADDR |
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hex "Remote Management Unit (RMU) binary location" |
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depends on HAVE_RMU |
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default 0xfff00000 |
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help |
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The location of the RMU binary is determined by a strap. It must be |
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put in flash at a location matching the strap-determined base address. |
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|
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The default base address of 0xfff00000 indicates that the binary must |
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be located at offset 0 from the beginning of a 1MB flash device. |
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config HAVE_CMC |
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bool |
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default HAVE_RMU |
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config CMC_FILE |
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string |
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depends on HAVE_CMC |
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default RMU_FILE |
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config CMC_ADDR |
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hex |
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depends on HAVE_CMC |
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default RMU_ADDR |
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config ESRAM_BASE |
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hex |
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default 0x80000000 |
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help |
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Embedded SRAM (eSRAM) memory-mapped base address. |
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|
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config PCIE_ECAM_BASE |
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hex |
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default 0xe0000000 |
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config RCBA_BASE |
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hex |
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default 0xfed1c000 |
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help |
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Root Complex register block memory-mapped base address. |
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|
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config ACPI_PM1_BASE |
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hex |
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default 0x1000 |
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help |
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ACPI Power Managment 1 (PM1) i/o-mapped base address. |
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This device is defined in ACPI specification, with 16 bytes in size. |
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|
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config ACPI_PBLK_BASE |
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hex |
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default 0x1010 |
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help |
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ACPI Processor Block (PBLK) i/o-mapped base address. |
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This device is defined in ACPI specification, with 16 bytes in size. |
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|
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config SPI_DMA_BASE |
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hex |
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default 0x1020 |
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help |
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SPI DMA i/o-mapped base address. |
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|
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config GPIO_BASE |
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hex |
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default 0x1080 |
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help |
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GPIO i/o-mapped base address. |
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|
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config ACPI_GPE0_BASE |
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hex |
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default 0x1100 |
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help |
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ACPI General Purpose Event 0 (GPE0) i/o-mapped base address. |
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This device is defined in ACPI specification, with 64 bytes in size. |
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|
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config WDT_BASE |
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hex |
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default 0x1140 |
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help |
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Watchdog timer i/o-mapped base address. |
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|
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config SYS_CAR_ADDR |
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hex |
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default ESRAM_BASE |
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|
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config SYS_CAR_SIZE |
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hex |
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default 0x8000 |
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help |
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Space in bytes in eSRAM used as Cache-As-ARM (CAR). |
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Note this size must not exceed eSRAM's total size. |
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|
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config TSC_FREQ_IN_MHZ |
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int |
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default 400 |
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endif |
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@ -0,0 +1,9 @@ |
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#
|
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# Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
|
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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|
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obj-y += car.o dram.o msg_port.o quark.o
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obj-y += mrc.o mrc_util.o hte.o smc.o
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obj-$(CONFIG_PCI) += pci.o
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@ -0,0 +1,105 @@ |
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/* |
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* Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
|
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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|
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#include <config.h> |
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#include <asm/pci.h> |
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#include <asm/post.h> |
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#include <asm/arch/quark.h> |
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#include <asm/arch/msg_port.h> |
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|
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.globl car_init
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car_init: |
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post_code(POST_CAR_START) |
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|
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/* |
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* Quark SoC contains an embedded 512KiB SRAM (eSRAM) that is |
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* initialized by hardware. eSRAM is the ideal place to be used |
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* for Cache-As-RAM (CAR) before system memory is available. |
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* |
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* Relocate this eSRAM to a suitable location in the physical |
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* memory map and enable it. |
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*/ |
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|
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/* Host Memory Bound Register P03h:R08h */ |
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mov $((MSG_PORT_HOST_BRIDGE << 16) | (HM_BOUND << 8)), %eax |
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mov $(DRAM_BASE + DRAM_MAX_SIZE + ESRAM_SIZE), %edx |
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lea 1f, %esp |
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jmp msg_port_write |
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1: |
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|
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/* eSRAM Block Page Control Register P05h:R82h */ |
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mov $((MSG_PORT_MEM_MGR << 16) | (ESRAM_BLK_CTRL << 8)), %eax |
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mov $(ESRAM_BLOCK_MODE | (CONFIG_ESRAM_BASE >> 24)), %edx |
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lea 2f, %esp |
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jmp msg_port_write |
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2: |
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|
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post_code(POST_CAR_CPU_CACHE) |
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jmp car_init_ret |
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|
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msg_port_read: |
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/* |
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* Parameter: |
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* eax[23:16] - Message Port ID |
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* eax[15:08] - Register Address |
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* |
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* Return Value: |
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* eax - Message Port Register value |
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* |
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* Return Address: esp |
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*/ |
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|
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or $((MSG_OP_READ << 24) | MSG_BYTE_ENABLE), %eax |
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mov %eax, %ebx |
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|
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/* Write MCR B0:D0:F0:RD0 */ |
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mov $(PCI_CFG_EN | MSG_CTRL_REG), %eax |
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mov $PCI_REG_ADDR, %dx |
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out %eax, %dx |
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mov $PCI_REG_DATA, %dx |
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mov %ebx, %eax |
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out %eax, %dx |
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|
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/* Read MDR B0:D0:F0:RD4 */ |
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mov $(PCI_CFG_EN | MSG_DATA_REG), %eax |
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mov $PCI_REG_ADDR, %dx |
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out %eax, %dx |
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mov $PCI_REG_DATA, %dx |
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in %dx, %eax |
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|
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jmp *%esp |
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|
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msg_port_write: |
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/* |
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* Parameter: |
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* eax[23:16] - Message Port ID |
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* eax[15:08] - Register Address |
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* edx - Message Port Register value to write |
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* |
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* Return Address: esp |
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*/ |
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|
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or $((MSG_OP_WRITE << 24) | MSG_BYTE_ENABLE), %eax |
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mov %eax, %esi |
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mov %edx, %edi |
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|
||||
/* Write MDR B0:D0:F0:RD4 */ |
||||
mov $(PCI_CFG_EN | MSG_DATA_REG), %eax |
||||
mov $PCI_REG_ADDR, %dx |
||||
out %eax, %dx |
||||
mov $PCI_REG_DATA, %dx |
||||
mov %edi, %eax |
||||
out %eax, %dx |
||||
|
||||
/* Write MCR B0:D0:F0:RD0 */ |
||||
mov $(PCI_CFG_EN | MSG_CTRL_REG), %eax |
||||
mov $PCI_REG_ADDR, %dx |
||||
out %eax, %dx |
||||
mov $PCI_REG_DATA, %dx |
||||
mov %esi, %eax |
||||
out %eax, %dx |
||||
|
||||
jmp *%esp |
||||
@ -0,0 +1,134 @@ |
||||
/*
|
||||
* Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <errno.h> |
||||
#include <fdtdec.h> |
||||
#include <asm/post.h> |
||||
#include <asm/arch/mrc.h> |
||||
#include <asm/arch/quark.h> |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
static int mrc_configure_params(struct mrc_params *mrc_params) |
||||
{ |
||||
const void *blob = gd->fdt_blob; |
||||
int node; |
||||
int mrc_flags; |
||||
|
||||
node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_QRK_MRC); |
||||
if (node < 0) { |
||||
debug("%s: Cannot find MRC node\n", __func__); |
||||
return -EINVAL; |
||||
} |
||||
|
||||
/*
|
||||
* TODO: |
||||
* |
||||
* We need support fast boot (MRC cache) in the future. |
||||
* |
||||
* Set boot mode to cold boot for now |
||||
*/ |
||||
mrc_params->boot_mode = BM_COLD; |
||||
|
||||
/*
|
||||
* TODO: |
||||
* |
||||
* We need determine ECC by pin strap state |
||||
* |
||||
* Disable ECC by default for now |
||||
*/ |
||||
mrc_params->ecc_enables = 0; |
||||
|
||||
mrc_flags = fdtdec_get_int(blob, node, "flags", 0); |
||||
if (mrc_flags & MRC_FLAG_SCRAMBLE_EN) |
||||
mrc_params->scrambling_enables = 1; |
||||
else |
||||
mrc_params->scrambling_enables = 0; |
||||
|
||||
mrc_params->dram_width = fdtdec_get_int(blob, node, "dram-width", 0); |
||||
mrc_params->ddr_speed = fdtdec_get_int(blob, node, "dram-speed", 0); |
||||
mrc_params->ddr_type = fdtdec_get_int(blob, node, "dram-type", 0); |
||||
|
||||
mrc_params->rank_enables = fdtdec_get_int(blob, node, "rank-mask", 0); |
||||
mrc_params->channel_enables = fdtdec_get_int(blob, node, |
||||
"chan-mask", 0); |
||||
mrc_params->channel_width = fdtdec_get_int(blob, node, |
||||
"chan-width", 0); |
||||
mrc_params->address_mode = fdtdec_get_int(blob, node, "addr-mode", 0); |
||||
|
||||
mrc_params->refresh_rate = fdtdec_get_int(blob, node, |
||||
"refresh-rate", 0); |
||||
mrc_params->sr_temp_range = fdtdec_get_int(blob, node, |
||||
"sr-temp-range", 0); |
||||
mrc_params->ron_value = fdtdec_get_int(blob, node, |
||||
"ron-value", 0); |
||||
mrc_params->rtt_nom_value = fdtdec_get_int(blob, node, |
||||
"rtt-nom-value", 0); |
||||
mrc_params->rd_odt_value = fdtdec_get_int(blob, node, |
||||
"rd-odt-value", 0); |
||||
|
||||
mrc_params->params.density = fdtdec_get_int(blob, node, |
||||
"dram-density", 0); |
||||
mrc_params->params.cl = fdtdec_get_int(blob, node, "dram-cl", 0); |
||||
mrc_params->params.ras = fdtdec_get_int(blob, node, "dram-ras", 0); |
||||
mrc_params->params.wtr = fdtdec_get_int(blob, node, "dram-wtr", 0); |
||||
mrc_params->params.rrd = fdtdec_get_int(blob, node, "dram-rrd", 0); |
||||
mrc_params->params.faw = fdtdec_get_int(blob, node, "dram-faw", 0); |
||||
|
||||
debug("MRC dram_width %d\n", mrc_params->dram_width); |
||||
debug("MRC rank_enables %d\n", mrc_params->rank_enables); |
||||
debug("MRC ddr_speed %d\n", mrc_params->ddr_speed); |
||||
debug("MRC flags: %s\n", |
||||
(mrc_params->scrambling_enables) ? "SCRAMBLE_EN" : ""); |
||||
|
||||
debug("MRC density=%d tCL=%d tRAS=%d tWTR=%d tRRD=%d tFAW=%d\n", |
||||
mrc_params->params.density, mrc_params->params.cl, |
||||
mrc_params->params.ras, mrc_params->params.wtr, |
||||
mrc_params->params.rrd, mrc_params->params.faw); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int dram_init(void) |
||||
{ |
||||
struct mrc_params mrc_params; |
||||
int ret; |
||||
|
||||
memset(&mrc_params, 0, sizeof(struct mrc_params)); |
||||
ret = mrc_configure_params(&mrc_params); |
||||
if (ret) |
||||
return ret; |
||||
|
||||
/* Set up the DRAM by calling the memory reference code */ |
||||
mrc_init(&mrc_params); |
||||
if (mrc_params.status) |
||||
return -EIO; |
||||
|
||||
gd->ram_size = mrc_params.mem_size; |
||||
post_code(POST_DRAM); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
void dram_init_banksize(void) |
||||
{ |
||||
gd->bd->bi_dram[0].start = 0; |
||||
gd->bd->bi_dram[0].size = gd->ram_size; |
||||
} |
||||
|
||||
/*
|
||||
* This function looks for the highest region of memory lower than 4GB which |
||||
* has enough space for U-Boot where U-Boot is aligned on a page boundary. |
||||
* It overrides the default implementation found elsewhere which simply |
||||
* picks the end of ram, wherever that may be. The location of the stack, |
||||
* the relocation address, and how far U-Boot is moved by relocation are |
||||
* set in the global data structure. |
||||
*/ |
||||
ulong board_get_usable_ram_top(ulong total_size) |
||||
{ |
||||
return gd->ram_size; |
||||
} |
||||
@ -0,0 +1,396 @@ |
||||
/*
|
||||
* Copyright (C) 2013, Intel Corporation |
||||
* Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> |
||||
* |
||||
* Ported from Intel released Quark UEFI BIOS |
||||
* QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei |
||||
* |
||||
* SPDX-License-Identifier: Intel |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/arch/mrc.h> |
||||
#include <asm/arch/msg_port.h> |
||||
#include "mrc_util.h" |
||||
#include "hte.h" |
||||
|
||||
/**
|
||||
* Enable HTE to detect all possible errors for the given training parameters |
||||
* (per-bit or full byte lane). |
||||
*/ |
||||
static void hte_enable_all_errors(void) |
||||
{ |
||||
msg_port_write(HTE, 0x000200A2, 0xFFFFFFFF); |
||||
msg_port_write(HTE, 0x000200A3, 0x000000FF); |
||||
msg_port_write(HTE, 0x000200A4, 0x00000000); |
||||
} |
||||
|
||||
/**
|
||||
* Go and read the HTE register in order to find any error |
||||
* |
||||
* @return: The errors detected in the HTE status register |
||||
*/ |
||||
static u32 hte_check_errors(void) |
||||
{ |
||||
return msg_port_read(HTE, 0x000200A7); |
||||
} |
||||
|
||||
/**
|
||||
* Wait until HTE finishes |
||||
*/ |
||||
static void hte_wait_for_complete(void) |
||||
{ |
||||
u32 tmp; |
||||
|
||||
ENTERFN(); |
||||
|
||||
do {} while ((msg_port_read(HTE, 0x00020012) & BIT30) != 0); |
||||
|
||||
tmp = msg_port_read(HTE, 0x00020011); |
||||
tmp |= BIT9; |
||||
tmp &= ~(BIT12 | BIT13); |
||||
msg_port_write(HTE, 0x00020011, tmp); |
||||
|
||||
LEAVEFN(); |
||||
} |
||||
|
||||
/**
|
||||
* Clear registers related with errors in the HTE |
||||
*/ |
||||
static void hte_clear_error_regs(void) |
||||
{ |
||||
u32 tmp; |
||||
|
||||
/*
|
||||
* Clear all HTE errors and enable error checking |
||||
* for burst and chunk. |
||||
*/ |
||||
tmp = msg_port_read(HTE, 0x000200A1); |
||||
tmp |= BIT8; |
||||
msg_port_write(HTE, 0x000200A1, tmp); |
||||
} |
||||
|
||||
/**
|
||||
* Execute a basic single-cache-line memory write/read/verify test using simple |
||||
* constant pattern, different for READ_TRAIN and WRITE_TRAIN modes. |
||||
* |
||||
* See hte_basic_write_read() which is the external visible wrapper. |
||||
* |
||||
* @mrc_params: host structure for all MRC global data |
||||
* @addr: memory adress being tested (must hit specific channel/rank) |
||||
* @first_run: if set then the HTE registers are configured, otherwise it is |
||||
* assumed configuration is done and we just re-run the test |
||||
* @mode: READ_TRAIN or WRITE_TRAIN (the difference is in the pattern) |
||||
* |
||||
* @return: byte lane failure on each bit (for Quark only bit0 and bit1) |
||||
*/ |
||||
static u16 hte_basic_data_cmp(struct mrc_params *mrc_params, u32 addr, |
||||
u8 first_run, u8 mode) |
||||
{ |
||||
u32 pattern; |
||||
u32 offset; |
||||
|
||||
if (first_run) { |
||||
msg_port_write(HTE, 0x00020020, 0x01B10021); |
||||
msg_port_write(HTE, 0x00020021, 0x06000000); |
||||
msg_port_write(HTE, 0x00020022, addr >> 6); |
||||
msg_port_write(HTE, 0x00020062, 0x00800015); |
||||
msg_port_write(HTE, 0x00020063, 0xAAAAAAAA); |
||||
msg_port_write(HTE, 0x00020064, 0xCCCCCCCC); |
||||
msg_port_write(HTE, 0x00020065, 0xF0F0F0F0); |
||||
msg_port_write(HTE, 0x00020061, 0x00030008); |
||||
|
||||
if (mode == WRITE_TRAIN) |
||||
pattern = 0xC33C0000; |
||||
else /* READ_TRAIN */ |
||||
pattern = 0xAA5555AA; |
||||
|
||||
for (offset = 0x80; offset <= 0x8F; offset++) |
||||
msg_port_write(HTE, offset, pattern); |
||||
} |
||||
|
||||
msg_port_write(HTE, 0x000200A1, 0xFFFF1000); |
||||
msg_port_write(HTE, 0x00020011, 0x00011000); |
||||
msg_port_write(HTE, 0x00020011, 0x00011100); |
||||
|
||||
hte_wait_for_complete(); |
||||
|
||||
/*
|
||||
* Return bits 15:8 of HTE_CH0_ERR_XSTAT to check for |
||||
* any bytelane errors. |
||||
*/ |
||||
return (hte_check_errors() >> 8) & 0xFF; |
||||
} |
||||
|
||||
/**
|
||||
* Examine a single-cache-line memory with write/read/verify test using multiple |
||||
* data patterns (victim-aggressor algorithm). |
||||
* |
||||
* See hte_write_stress_bit_lanes() which is the external visible wrapper. |
||||
* |
||||
* @mrc_params: host structure for all MRC global data |
||||
* @addr: memory adress being tested (must hit specific channel/rank) |
||||
* @loop_cnt: number of test iterations |
||||
* @seed_victim: victim data pattern seed |
||||
* @seed_aggressor: aggressor data pattern seed |
||||
* @victim_bit: should be 0 as auto-rotate feature is in use |
||||
* @first_run: if set then the HTE registers are configured, otherwise it is |
||||
* assumed configuration is done and we just re-run the test |
||||
* |
||||
* @return: byte lane failure on each bit (for Quark only bit0 and bit1) |
||||
*/ |
||||
static u16 hte_rw_data_cmp(struct mrc_params *mrc_params, u32 addr, |
||||
u8 loop_cnt, u32 seed_victim, u32 seed_aggressor, |
||||
u8 victim_bit, u8 first_run) |
||||
{ |
||||
u32 offset; |
||||
u32 tmp; |
||||
|
||||
if (first_run) { |
||||
msg_port_write(HTE, 0x00020020, 0x00910024); |
||||
msg_port_write(HTE, 0x00020023, 0x00810024); |
||||
msg_port_write(HTE, 0x00020021, 0x06070000); |
||||
msg_port_write(HTE, 0x00020024, 0x06070000); |
||||
msg_port_write(HTE, 0x00020022, addr >> 6); |
||||
msg_port_write(HTE, 0x00020025, addr >> 6); |
||||
msg_port_write(HTE, 0x00020062, 0x0000002A); |
||||
msg_port_write(HTE, 0x00020063, seed_victim); |
||||
msg_port_write(HTE, 0x00020064, seed_aggressor); |
||||
msg_port_write(HTE, 0x00020065, seed_victim); |
||||
|
||||
/*
|
||||
* Write the pattern buffers to select the victim bit |
||||
* |
||||
* Start with bit0 |
||||
*/ |
||||
for (offset = 0x80; offset <= 0x8F; offset++) { |
||||
if ((offset % 8) == victim_bit) |
||||
msg_port_write(HTE, offset, 0x55555555); |
||||
else |
||||
msg_port_write(HTE, offset, 0xCCCCCCCC); |
||||
} |
||||
|
||||
msg_port_write(HTE, 0x00020061, 0x00000000); |
||||
msg_port_write(HTE, 0x00020066, 0x03440000); |
||||
msg_port_write(HTE, 0x000200A1, 0xFFFF1000); |
||||
} |
||||
|
||||
tmp = 0x10001000 | (loop_cnt << 16); |
||||
msg_port_write(HTE, 0x00020011, tmp); |
||||
msg_port_write(HTE, 0x00020011, tmp | BIT8); |
||||
|
||||
hte_wait_for_complete(); |
||||
|
||||
/*
|
||||
* Return bits 15:8 of HTE_CH0_ERR_XSTAT to check for |
||||
* any bytelane errors. |
||||
*/ |
||||
return (hte_check_errors() >> 8) & 0xFF; |
||||
} |
||||
|
||||
/**
|
||||
* Use HW HTE engine to initialize or test all memory attached to a given DUNIT. |
||||
* If flag is MRC_MEM_INIT, this routine writes 0s to all memory locations to |
||||
* initialize ECC. If flag is MRC_MEM_TEST, this routine will send an 5AA55AA5 |
||||
* pattern to all memory locations on the RankMask and then read it back. |
||||
* Then it sends an A55AA55A pattern to all memory locations on the RankMask |
||||
* and reads it back. |
||||
* |
||||
* @mrc_params: host structure for all MRC global data |
||||
* @flag: MRC_MEM_INIT or MRC_MEM_TEST |
||||
* |
||||
* @return: errors register showing HTE failures. Also prints out which rank |
||||
* failed the HTE test if failure occurs. For rank detection to work, |
||||
* the address map must be left in its default state. If MRC changes |
||||
* the address map, this function must be modified to change it back |
||||
* to default at the beginning, then restore it at the end. |
||||
*/ |
||||
u32 hte_mem_init(struct mrc_params *mrc_params, u8 flag) |
||||
{ |
||||
u32 offset; |
||||
int test_num; |
||||
int i; |
||||
|
||||
/*
|
||||
* Clear out the error registers at the start of each memory |
||||
* init or memory test run. |
||||
*/ |
||||
hte_clear_error_regs(); |
||||
|
||||
msg_port_write(HTE, 0x00020062, 0x00000015); |
||||
|
||||
for (offset = 0x80; offset <= 0x8F; offset++) |
||||
msg_port_write(HTE, offset, ((offset & 1) ? 0xA55A : 0x5AA5)); |
||||
|
||||
msg_port_write(HTE, 0x00020021, 0x00000000); |
||||
msg_port_write(HTE, 0x00020022, (mrc_params->mem_size >> 6) - 1); |
||||
msg_port_write(HTE, 0x00020063, 0xAAAAAAAA); |
||||
msg_port_write(HTE, 0x00020064, 0xCCCCCCCC); |
||||
msg_port_write(HTE, 0x00020065, 0xF0F0F0F0); |
||||
msg_port_write(HTE, 0x00020066, 0x03000000); |
||||
|
||||
switch (flag) { |
||||
case MRC_MEM_INIT: |
||||
/*
|
||||
* Only 1 write pass through memory is needed |
||||
* to initialize ECC |
||||
*/ |
||||
test_num = 1; |
||||
break; |
||||
case MRC_MEM_TEST: |
||||
/* Write/read then write/read with inverted pattern */ |
||||
test_num = 4; |
||||
break; |
||||
default: |
||||
DPF(D_INFO, "Unknown parameter for flag: %d\n", flag); |
||||
return 0xFFFFFFFF; |
||||
} |
||||
|
||||
DPF(D_INFO, "hte_mem_init"); |
||||
|
||||
for (i = 0; i < test_num; i++) { |
||||
DPF(D_INFO, "."); |
||||
|
||||
if (i == 0) { |
||||
msg_port_write(HTE, 0x00020061, 0x00000000); |
||||
msg_port_write(HTE, 0x00020020, 0x00110010); |
||||
} else if (i == 1) { |
||||
msg_port_write(HTE, 0x00020061, 0x00000000); |
||||
msg_port_write(HTE, 0x00020020, 0x00010010); |
||||
} else if (i == 2) { |
||||
msg_port_write(HTE, 0x00020061, 0x00010100); |
||||
msg_port_write(HTE, 0x00020020, 0x00110010); |
||||
} else { |
||||
msg_port_write(HTE, 0x00020061, 0x00010100); |
||||
msg_port_write(HTE, 0x00020020, 0x00010010); |
||||
} |
||||
|
||||
msg_port_write(HTE, 0x00020011, 0x00111000); |
||||
msg_port_write(HTE, 0x00020011, 0x00111100); |
||||
|
||||
hte_wait_for_complete(); |
||||
|
||||
/* If this is a READ pass, check for errors at the end */ |
||||
if ((i % 2) == 1) { |
||||
/* Return immediately if error */ |
||||
if (hte_check_errors()) |
||||
break; |
||||
} |
||||
} |
||||
|
||||
DPF(D_INFO, "done\n"); |
||||
|
||||
return hte_check_errors(); |
||||
} |
||||
|
||||
/**
|
||||
* Execute a basic single-cache-line memory write/read/verify test using simple |
||||
* constant pattern, different for READ_TRAIN and WRITE_TRAIN modes. |
||||
* |
||||
* @mrc_params: host structure for all MRC global data |
||||
* @addr: memory adress being tested (must hit specific channel/rank) |
||||
* @first_run: if set then the HTE registers are configured, otherwise it is |
||||
* assumed configuration is done and we just re-run the test |
||||
* @mode: READ_TRAIN or WRITE_TRAIN (the difference is in the pattern) |
||||
* |
||||
* @return: byte lane failure on each bit (for Quark only bit0 and bit1) |
||||
*/ |
||||
u16 hte_basic_write_read(struct mrc_params *mrc_params, u32 addr, |
||||
u8 first_run, u8 mode) |
||||
{ |
||||
u16 errors; |
||||
|
||||
ENTERFN(); |
||||
|
||||
/* Enable all error reporting in preparation for HTE test */ |
||||
hte_enable_all_errors(); |
||||
hte_clear_error_regs(); |
||||
|
||||
errors = hte_basic_data_cmp(mrc_params, addr, first_run, mode); |
||||
|
||||
LEAVEFN(); |
||||
|
||||
return errors; |
||||
} |
||||
|
||||
/**
|
||||
* Examine a single-cache-line memory with write/read/verify test using multiple |
||||
* data patterns (victim-aggressor algorithm). |
||||
* |
||||
* @mrc_params: host structure for all MRC global data |
||||
* @addr: memory adress being tested (must hit specific channel/rank) |
||||
* @first_run: if set then the HTE registers are configured, otherwise it is |
||||
* assumed configuration is done and we just re-run the test |
||||
* |
||||
* @return: byte lane failure on each bit (for Quark only bit0 and bit1) |
||||
*/ |
||||
u16 hte_write_stress_bit_lanes(struct mrc_params *mrc_params, |
||||
u32 addr, u8 first_run) |
||||
{ |
||||
u16 errors; |
||||
u8 victim_bit = 0; |
||||
|
||||
ENTERFN(); |
||||
|
||||
/* Enable all error reporting in preparation for HTE test */ |
||||
hte_enable_all_errors(); |
||||
hte_clear_error_regs(); |
||||
|
||||
/*
|
||||
* Loop through each bit in the bytelane. |
||||
* |
||||
* Each pass creates a victim bit while keeping all other bits the same |
||||
* as aggressors. AVN HTE adds an auto-rotate feature which allows us |
||||
* to program the entire victim/aggressor sequence in 1 step. |
||||
* |
||||
* The victim bit rotates on each pass so no need to have software |
||||
* implement a victim bit loop like on VLV. |
||||
*/ |
||||
errors = hte_rw_data_cmp(mrc_params, addr, HTE_LOOP_CNT, |
||||
HTE_LFSR_VICTIM_SEED, HTE_LFSR_AGRESSOR_SEED, |
||||
victim_bit, first_run); |
||||
|
||||
LEAVEFN(); |
||||
|
||||
return errors; |
||||
} |
||||
|
||||
/**
|
||||
* Execute a basic single-cache-line memory write or read. |
||||
* This is just for receive enable / fine write-levelling purpose. |
||||
* |
||||
* @addr: memory adress being tested (must hit specific channel/rank) |
||||
* @first_run: if set then the HTE registers are configured, otherwise it is |
||||
* assumed configuration is done and we just re-run the test |
||||
* @is_write: when non-zero memory write operation executed, otherwise read |
||||
*/ |
||||
void hte_mem_op(u32 addr, u8 first_run, u8 is_write) |
||||
{ |
||||
u32 offset; |
||||
u32 tmp; |
||||
|
||||
hte_enable_all_errors(); |
||||
hte_clear_error_regs(); |
||||
|
||||
if (first_run) { |
||||
tmp = is_write ? 0x01110021 : 0x01010021; |
||||
msg_port_write(HTE, 0x00020020, tmp); |
||||
|
||||
msg_port_write(HTE, 0x00020021, 0x06000000); |
||||
msg_port_write(HTE, 0x00020022, addr >> 6); |
||||
msg_port_write(HTE, 0x00020062, 0x00800015); |
||||
msg_port_write(HTE, 0x00020063, 0xAAAAAAAA); |
||||
msg_port_write(HTE, 0x00020064, 0xCCCCCCCC); |
||||
msg_port_write(HTE, 0x00020065, 0xF0F0F0F0); |
||||
msg_port_write(HTE, 0x00020061, 0x00030008); |
||||
|
||||
for (offset = 0x80; offset <= 0x8F; offset++) |
||||
msg_port_write(HTE, offset, 0xC33C0000); |
||||
} |
||||
|
||||
msg_port_write(HTE, 0x000200A1, 0xFFFF1000); |
||||
msg_port_write(HTE, 0x00020011, 0x00011000); |
||||
msg_port_write(HTE, 0x00020011, 0x00011100); |
||||
|
||||
hte_wait_for_complete(); |
||||
} |
||||
@ -0,0 +1,44 @@ |
||||
/*
|
||||
* Copyright (C) 2013, Intel Corporation |
||||
* Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> |
||||
* |
||||
* Ported from Intel released Quark UEFI BIOS |
||||
* QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei |
||||
* |
||||
* SPDX-License-Identifier: Intel |
||||
*/ |
||||
|
||||
#ifndef _HTE_H_ |
||||
#define _HTE_H_ |
||||
|
||||
enum { |
||||
MRC_MEM_INIT, |
||||
MRC_MEM_TEST |
||||
}; |
||||
|
||||
enum { |
||||
READ_TRAIN, |
||||
WRITE_TRAIN |
||||
}; |
||||
|
||||
/*
|
||||
* EXP_LOOP_CNT field of HTE_CMD_CTL |
||||
* |
||||
* This CANNOT be less than 4! |
||||
*/ |
||||
#define HTE_LOOP_CNT 5 |
||||
|
||||
/* random seed for victim */ |
||||
#define HTE_LFSR_VICTIM_SEED 0xF294BA21 |
||||
|
||||
/* random seed for aggressor */ |
||||
#define HTE_LFSR_AGRESSOR_SEED 0xEBA7492D |
||||
|
||||
u32 hte_mem_init(struct mrc_params *mrc_params, u8 flag); |
||||
u16 hte_basic_write_read(struct mrc_params *mrc_params, u32 addr, |
||||
u8 first_run, u8 mode); |
||||
u16 hte_write_stress_bit_lanes(struct mrc_params *mrc_params, |
||||
u32 addr, u8 first_run); |
||||
void hte_mem_op(u32 addr, u8 first_run, u8 is_write); |
||||
|
||||
#endif /* _HTE_H_ */ |
||||
@ -0,0 +1,204 @@ |
||||
/*
|
||||
* Copyright (C) 2013, Intel Corporation |
||||
* Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> |
||||
* |
||||
* Ported from Intel released Quark UEFI BIOS |
||||
* QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei |
||||
* |
||||
* SPDX-License-Identifier: Intel |
||||
*/ |
||||
|
||||
/*
|
||||
* This is the main Quark Memory Reference Code (MRC) |
||||
* |
||||
* These functions are generic and should work for any Quark-based board. |
||||
* |
||||
* MRC requires two data structures to be passed in which are initialized by |
||||
* mrc_adjust_params(). |
||||
* |
||||
* The basic flow is as follows: |
||||
* 01) Check for supported DDR speed configuration |
||||
* 02) Set up Memory Manager buffer as pass-through (POR) |
||||
* 03) Set Channel Interleaving Mode and Channel Stride to the most aggressive |
||||
* setting possible |
||||
* 04) Set up the Memory Controller logic |
||||
* 05) Set up the DDR_PHY logic |
||||
* 06) Initialise the DRAMs (JEDEC) |
||||
* 07) Perform the Receive Enable Calibration algorithm |
||||
* 08) Perform the Write Leveling algorithm |
||||
* 09) Perform the Read Training algorithm (includes internal Vref) |
||||
* 10) Perform the Write Training algorithm |
||||
* 11) Set Channel Interleaving Mode and Channel Stride to the desired settings |
||||
* |
||||
* DRAM unit configuration based on Valleyview MRC. |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/arch/mrc.h> |
||||
#include <asm/arch/msg_port.h> |
||||
#include "mrc_util.h" |
||||
#include "smc.h" |
||||
|
||||
static const struct mem_init init[] = { |
||||
{ 0x0101, BM_COLD | BM_FAST | BM_WARM | BM_S3, clear_self_refresh }, |
||||
{ 0x0200, BM_COLD | BM_FAST | BM_WARM | BM_S3, prog_ddr_timing_control }, |
||||
{ 0x0103, BM_COLD | BM_FAST , prog_decode_before_jedec }, |
||||
{ 0x0104, BM_COLD | BM_FAST , perform_ddr_reset }, |
||||
{ 0x0300, BM_COLD | BM_FAST | BM_S3, ddrphy_init }, |
||||
{ 0x0400, BM_COLD | BM_FAST , perform_jedec_init }, |
||||
{ 0x0105, BM_COLD | BM_FAST , set_ddr_init_complete }, |
||||
{ 0x0106, BM_FAST | BM_WARM | BM_S3, restore_timings }, |
||||
{ 0x0106, BM_COLD , default_timings }, |
||||
{ 0x0500, BM_COLD , rcvn_cal }, |
||||
{ 0x0600, BM_COLD , wr_level }, |
||||
{ 0x0120, BM_COLD , prog_page_ctrl }, |
||||
{ 0x0700, BM_COLD , rd_train }, |
||||
{ 0x0800, BM_COLD , wr_train }, |
||||
{ 0x010b, BM_COLD , store_timings }, |
||||
{ 0x010c, BM_COLD | BM_FAST | BM_WARM | BM_S3, enable_scrambling }, |
||||
{ 0x010d, BM_COLD | BM_FAST | BM_WARM | BM_S3, prog_ddr_control }, |
||||
{ 0x010e, BM_COLD | BM_FAST | BM_WARM | BM_S3, prog_dra_drb }, |
||||
{ 0x010f, BM_WARM | BM_S3, perform_wake }, |
||||
{ 0x0110, BM_COLD | BM_FAST | BM_WARM | BM_S3, change_refresh_period }, |
||||
{ 0x0111, BM_COLD | BM_FAST | BM_WARM | BM_S3, set_auto_refresh }, |
||||
{ 0x0112, BM_COLD | BM_FAST | BM_WARM | BM_S3, ecc_enable }, |
||||
{ 0x0113, BM_COLD | BM_FAST , memory_test }, |
||||
{ 0x0114, BM_COLD | BM_FAST | BM_WARM | BM_S3, lock_registers } |
||||
}; |
||||
|
||||
/* Adjust configuration parameters before initialization sequence */ |
||||
static void mrc_adjust_params(struct mrc_params *mrc_params) |
||||
{ |
||||
const struct dram_params *dram_params; |
||||
uint8_t dram_width; |
||||
uint32_t rank_enables; |
||||
uint32_t channel_width; |
||||
|
||||
ENTERFN(); |
||||
|
||||
/* initially expect success */ |
||||
mrc_params->status = MRC_SUCCESS; |
||||
|
||||
dram_width = mrc_params->dram_width; |
||||
rank_enables = mrc_params->rank_enables; |
||||
channel_width = mrc_params->channel_width; |
||||
|
||||
/*
|
||||
* Setup board layout (must be reviewed as is selecting static timings) |
||||
* 0 == R0 (DDR3 x16), 1 == R1 (DDR3 x16), |
||||
* 2 == DV (DDR3 x8), 3 == SV (DDR3 x8). |
||||
*/ |
||||
if (dram_width == X8) |
||||
mrc_params->board_id = 2; /* select x8 layout */ |
||||
else |
||||
mrc_params->board_id = 0; /* select x16 layout */ |
||||
|
||||
/* initially no memory */ |
||||
mrc_params->mem_size = 0; |
||||
|
||||
/* begin of channel settings */ |
||||
dram_params = &mrc_params->params; |
||||
|
||||
/*
|
||||
* Determine column bits: |
||||
* |
||||
* Column: 11 for 8Gbx8, else 10 |
||||
*/ |
||||
mrc_params->column_bits[0] = |
||||
((dram_params[0].density == 4) && |
||||
(dram_width == X8)) ? (11) : (10); |
||||
|
||||
/*
|
||||
* Determine row bits: |
||||
* |
||||
* 512Mbx16=12 512Mbx8=13 |
||||
* 1Gbx16=13 1Gbx8=14 |
||||
* 2Gbx16=14 2Gbx8=15 |
||||
* 4Gbx16=15 4Gbx8=16 |
||||
* 8Gbx16=16 8Gbx8=16 |
||||
*/ |
||||
mrc_params->row_bits[0] = 12 + (dram_params[0].density) + |
||||
(((dram_params[0].density < 4) && |
||||
(dram_width == X8)) ? (1) : (0)); |
||||
|
||||
/*
|
||||
* Determine per-channel memory size: |
||||
* |
||||
* (For 2 RANKs, multiply by 2) |
||||
* (For 16 bit data bus, divide by 2) |
||||
* |
||||
* DENSITY WIDTH MEM_AVAILABLE |
||||
* 512Mb x16 0x008000000 ( 128MB) |
||||
* 512Mb x8 0x010000000 ( 256MB) |
||||
* 1Gb x16 0x010000000 ( 256MB) |
||||
* 1Gb x8 0x020000000 ( 512MB) |
||||
* 2Gb x16 0x020000000 ( 512MB) |
||||
* 2Gb x8 0x040000000 (1024MB) |
||||
* 4Gb x16 0x040000000 (1024MB) |
||||
* 4Gb x8 0x080000000 (2048MB) |
||||
*/ |
||||
mrc_params->channel_size[0] = (1 << dram_params[0].density); |
||||
mrc_params->channel_size[0] *= (dram_width == X8) ? 2 : 1; |
||||
mrc_params->channel_size[0] *= (rank_enables == 0x3) ? 2 : 1; |
||||
mrc_params->channel_size[0] *= (channel_width == X16) ? 1 : 2; |
||||
|
||||
/* Determine memory size (convert number of 64MB/512Mb units) */ |
||||
mrc_params->mem_size += mrc_params->channel_size[0] << 26; |
||||
|
||||
LEAVEFN(); |
||||
} |
||||
|
||||
static void mrc_mem_init(struct mrc_params *mrc_params) |
||||
{ |
||||
int i; |
||||
|
||||
ENTERFN(); |
||||
|
||||
/* MRC started */ |
||||
mrc_post_code(0x01, 0x00); |
||||
|
||||
if (mrc_params->boot_mode != BM_COLD) { |
||||
if (mrc_params->ddr_speed != mrc_params->timings.ddr_speed) { |
||||
/* full training required as frequency changed */ |
||||
mrc_params->boot_mode = BM_COLD; |
||||
} |
||||
} |
||||
|
||||
for (i = 0; i < ARRAY_SIZE(init); i++) { |
||||
uint64_t my_tsc; |
||||
|
||||
if (mrc_params->boot_mode & init[i].boot_path) { |
||||
uint8_t major = init[i].post_code >> 8 & 0xff; |
||||
uint8_t minor = init[i].post_code >> 0 & 0xff; |
||||
mrc_post_code(major, minor); |
||||
|
||||
my_tsc = rdtsc(); |
||||
init[i].init_fn(mrc_params); |
||||
DPF(D_TIME, "Execution time %llx", rdtsc() - my_tsc); |
||||
} |
||||
} |
||||
|
||||
/* display the timings */ |
||||
print_timings(mrc_params); |
||||
|
||||
/* MRC complete */ |
||||
mrc_post_code(0x01, 0xff); |
||||
|
||||
LEAVEFN(); |
||||
} |
||||
|
||||
void mrc_init(struct mrc_params *mrc_params) |
||||
{ |
||||
ENTERFN(); |
||||
|
||||
DPF(D_INFO, "MRC Version %04x %s %s\n", MRC_VERSION, |
||||
__DATE__, __TIME__); |
||||
|
||||
/* Set up the data structures used by mrc_mem_init() */ |
||||
mrc_adjust_params(mrc_params); |
||||
|
||||
/* Initialize system memory */ |
||||
mrc_mem_init(mrc_params); |
||||
|
||||
LEAVEFN(); |
||||
} |
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,153 @@ |
||||
/*
|
||||
* Copyright (C) 2013, Intel Corporation |
||||
* Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> |
||||
* |
||||
* Ported from Intel released Quark UEFI BIOS |
||||
* QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei |
||||
* |
||||
* SPDX-License-Identifier: Intel |
||||
*/ |
||||
|
||||
#ifndef _MRC_UTIL_H_ |
||||
#define _MRC_UTIL_H_ |
||||
|
||||
/* Turn on this macro to enable MRC debugging output */ |
||||
#undef MRC_DEBUG |
||||
|
||||
/* MRC Debug Support */ |
||||
#define DPF debug_cond |
||||
|
||||
/* debug print type */ |
||||
|
||||
#ifdef MRC_DEBUG |
||||
#define D_ERROR 0x0001 |
||||
#define D_INFO 0x0002 |
||||
#define D_REGRD 0x0004 |
||||
#define D_REGWR 0x0008 |
||||
#define D_FCALL 0x0010 |
||||
#define D_TRN 0x0020 |
||||
#define D_TIME 0x0040 |
||||
#else |
||||
#define D_ERROR 0 |
||||
#define D_INFO 0 |
||||
#define D_REGRD 0 |
||||
#define D_REGWR 0 |
||||
#define D_FCALL 0 |
||||
#define D_TRN 0 |
||||
#define D_TIME 0 |
||||
#endif |
||||
|
||||
#define ENTERFN(...) debug_cond(D_FCALL, "<%s>\n", __func__) |
||||
#define LEAVEFN(...) debug_cond(D_FCALL, "</%s>\n", __func__) |
||||
#define REPORTFN(...) debug_cond(D_FCALL, "<%s/>\n", __func__) |
||||
|
||||
/* Generic Register Bits */ |
||||
#define BIT0 0x00000001 |
||||
#define BIT1 0x00000002 |
||||
#define BIT2 0x00000004 |
||||
#define BIT3 0x00000008 |
||||
#define BIT4 0x00000010 |
||||
#define BIT5 0x00000020 |
||||
#define BIT6 0x00000040 |
||||
#define BIT7 0x00000080 |
||||
#define BIT8 0x00000100 |
||||
#define BIT9 0x00000200 |
||||
#define BIT10 0x00000400 |
||||
#define BIT11 0x00000800 |
||||
#define BIT12 0x00001000 |
||||
#define BIT13 0x00002000 |
||||
#define BIT14 0x00004000 |
||||
#define BIT15 0x00008000 |
||||
#define BIT16 0x00010000 |
||||
#define BIT17 0x00020000 |
||||
#define BIT18 0x00040000 |
||||
#define BIT19 0x00080000 |
||||
#define BIT20 0x00100000 |
||||
#define BIT21 0x00200000 |
||||
#define BIT22 0x00400000 |
||||
#define BIT23 0x00800000 |
||||
#define BIT24 0x01000000 |
||||
#define BIT25 0x02000000 |
||||
#define BIT26 0x04000000 |
||||
#define BIT27 0x08000000 |
||||
#define BIT28 0x10000000 |
||||
#define BIT29 0x20000000 |
||||
#define BIT30 0x40000000 |
||||
#define BIT31 0x80000000 |
||||
|
||||
/* Message Bus Port */ |
||||
#define MEM_CTLR 0x01 |
||||
#define HOST_BRIDGE 0x03 |
||||
#define MEM_MGR 0x05 |
||||
#define HTE 0x11 |
||||
#define DDRPHY 0x12 |
||||
|
||||
/* number of sample points */ |
||||
#define SAMPLE_CNT 3 |
||||
/* number of PIs to increment per sample */ |
||||
#define SAMPLE_DLY 26 |
||||
|
||||
enum { |
||||
/* indicates to decrease delays when looking for edge */ |
||||
BACKWARD, |
||||
/* indicates to increase delays when looking for edge */ |
||||
FORWARD |
||||
}; |
||||
|
||||
enum { |
||||
RCVN, |
||||
WDQS, |
||||
WDQX, |
||||
RDQS, |
||||
VREF, |
||||
WCMD, |
||||
WCTL, |
||||
WCLK, |
||||
MAX_ALGOS, |
||||
}; |
||||
|
||||
void mrc_write_mask(u32 unit, u32 addr, u32 data, u32 mask); |
||||
void mrc_alt_write_mask(u32 unit, u32 addr, u32 data, u32 mask); |
||||
void mrc_post_code(uint8_t major, uint8_t minor); |
||||
void delay_n(uint32_t ns); |
||||
void delay_u(uint32_t ms); |
||||
void select_mem_mgr(void); |
||||
void select_hte(void); |
||||
void dram_init_command(uint32_t data); |
||||
void dram_wake_command(void); |
||||
void training_message(uint8_t channel, uint8_t rank, uint8_t byte_lane); |
||||
|
||||
void set_rcvn(uint8_t channel, uint8_t rank, |
||||
uint8_t byte_lane, uint32_t pi_count); |
||||
uint32_t get_rcvn(uint8_t channel, uint8_t rank, uint8_t byte_lane); |
||||
void set_rdqs(uint8_t channel, uint8_t rank, |
||||
uint8_t byte_lane, uint32_t pi_count); |
||||
uint32_t get_rdqs(uint8_t channel, uint8_t rank, uint8_t byte_lane); |
||||
void set_wdqs(uint8_t channel, uint8_t rank, |
||||
uint8_t byte_lane, uint32_t pi_count); |
||||
uint32_t get_wdqs(uint8_t channel, uint8_t rank, uint8_t byte_lane); |
||||
void set_wdq(uint8_t channel, uint8_t rank, |
||||
uint8_t byte_lane, uint32_t pi_count); |
||||
uint32_t get_wdq(uint8_t channel, uint8_t rank, uint8_t byte_lane); |
||||
void set_wcmd(uint8_t channel, uint32_t pi_count); |
||||
uint32_t get_wcmd(uint8_t channel); |
||||
void set_wclk(uint8_t channel, uint8_t rank, uint32_t pi_count); |
||||
uint32_t get_wclk(uint8_t channel, uint8_t rank); |
||||
void set_wctl(uint8_t channel, uint8_t rank, uint32_t pi_count); |
||||
uint32_t get_wctl(uint8_t channel, uint8_t rank); |
||||
void set_vref(uint8_t channel, uint8_t byte_lane, uint32_t setting); |
||||
uint32_t get_vref(uint8_t channel, uint8_t byte_lane); |
||||
|
||||
uint32_t get_addr(uint8_t channel, uint8_t rank); |
||||
uint32_t sample_dqs(struct mrc_params *mrc_params, uint8_t channel, |
||||
uint8_t rank, bool rcvn); |
||||
void find_rising_edge(struct mrc_params *mrc_params, uint32_t delay[], |
||||
uint8_t channel, uint8_t rank, bool rcvn); |
||||
uint32_t byte_lane_mask(struct mrc_params *mrc_params); |
||||
uint32_t check_rw_coarse(struct mrc_params *mrc_params, uint32_t address); |
||||
uint32_t check_bls_ex(struct mrc_params *mrc_params, uint32_t address); |
||||
void lfsr32(uint32_t *lfsr_ptr); |
||||
void clear_pointers(void); |
||||
void print_timings(struct mrc_params *mrc_params); |
||||
|
||||
#endif /* _MRC_UTIL_H_ */ |
||||
@ -0,0 +1,77 @@ |
||||
/*
|
||||
* Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <pci.h> |
||||
#include <asm/arch/device.h> |
||||
#include <asm/arch/msg_port.h> |
||||
|
||||
void msg_port_setup(int op, int port, int reg) |
||||
{ |
||||
pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_REG, |
||||
(((op) << 24) | ((port) << 16) | |
||||
(((reg) << 8) & 0xff00) | MSG_BYTE_ENABLE)); |
||||
} |
||||
|
||||
u32 msg_port_read(u8 port, u32 reg) |
||||
{ |
||||
u32 value; |
||||
|
||||
pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG, |
||||
reg & 0xffffff00); |
||||
msg_port_setup(MSG_OP_READ, port, reg); |
||||
pci_read_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, &value); |
||||
|
||||
return value; |
||||
} |
||||
|
||||
void msg_port_write(u8 port, u32 reg, u32 value) |
||||
{ |
||||
pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, value); |
||||
pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG, |
||||
reg & 0xffffff00); |
||||
msg_port_setup(MSG_OP_WRITE, port, reg); |
||||
} |
||||
|
||||
u32 msg_port_alt_read(u8 port, u32 reg) |
||||
{ |
||||
u32 value; |
||||
|
||||
pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG, |
||||
reg & 0xffffff00); |
||||
msg_port_setup(MSG_OP_ALT_READ, port, reg); |
||||
pci_read_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, &value); |
||||
|
||||
return value; |
||||
} |
||||
|
||||
void msg_port_alt_write(u8 port, u32 reg, u32 value) |
||||
{ |
||||
pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, value); |
||||
pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG, |
||||
reg & 0xffffff00); |
||||
msg_port_setup(MSG_OP_ALT_WRITE, port, reg); |
||||
} |
||||
|
||||
u32 msg_port_io_read(u8 port, u32 reg) |
||||
{ |
||||
u32 value; |
||||
|
||||
pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG, |
||||
reg & 0xffffff00); |
||||
msg_port_setup(MSG_OP_IO_READ, port, reg); |
||||
pci_read_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, &value); |
||||
|
||||
return value; |
||||
} |
||||
|
||||
void msg_port_io_write(u8 port, u32 reg, u32 value) |
||||
{ |
||||
pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, value); |
||||
pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG, |
||||
reg & 0xffffff00); |
||||
msg_port_setup(MSG_OP_IO_WRITE, port, reg); |
||||
} |
||||
@ -0,0 +1,70 @@ |
||||
/*
|
||||
* Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <pci.h> |
||||
#include <asm/pci.h> |
||||
#include <asm/arch/device.h> |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
void board_pci_setup_hose(struct pci_controller *hose) |
||||
{ |
||||
hose->first_busno = 0; |
||||
hose->last_busno = 0; |
||||
|
||||
/* PCI memory space */ |
||||
pci_set_region(hose->regions + 0, |
||||
CONFIG_PCI_MEM_BUS, |
||||
CONFIG_PCI_MEM_PHYS, |
||||
CONFIG_PCI_MEM_SIZE, |
||||
PCI_REGION_MEM); |
||||
|
||||
/* PCI IO space */ |
||||
pci_set_region(hose->regions + 1, |
||||
CONFIG_PCI_IO_BUS, |
||||
CONFIG_PCI_IO_PHYS, |
||||
CONFIG_PCI_IO_SIZE, |
||||
PCI_REGION_IO); |
||||
|
||||
pci_set_region(hose->regions + 2, |
||||
CONFIG_PCI_PREF_BUS, |
||||
CONFIG_PCI_PREF_PHYS, |
||||
CONFIG_PCI_PREF_SIZE, |
||||
PCI_REGION_PREFETCH); |
||||
|
||||
pci_set_region(hose->regions + 3, |
||||
0, |
||||
0, |
||||
gd->ram_size, |
||||
PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); |
||||
|
||||
hose->region_count = 4; |
||||
} |
||||
|
||||
int board_pci_post_scan(struct pci_controller *hose) |
||||
{ |
||||
return 0; |
||||
} |
||||
|
||||
int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev) |
||||
{ |
||||
/*
|
||||
* TODO: |
||||
* |
||||
* For some unknown reason, the PCI enumeration process hangs |
||||
* when it scans to the PCIe root port 0 (D23:F0) & 1 (D23:F1). |
||||
* |
||||
* For now we just skip these two devices, and this needs to |
||||
* be revisited later. |
||||
*/ |
||||
if (dev == QUARK_HOST_BRIDGE || |
||||
dev == QUARK_PCIE0 || dev == QUARK_PCIE1) { |
||||
return 1; |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
@ -0,0 +1,118 @@ |
||||
/*
|
||||
* Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <mmc.h> |
||||
#include <asm/io.h> |
||||
#include <asm/pci.h> |
||||
#include <asm/post.h> |
||||
#include <asm/processor.h> |
||||
#include <asm/arch/device.h> |
||||
#include <asm/arch/msg_port.h> |
||||
#include <asm/arch/quark.h> |
||||
|
||||
static struct pci_device_id mmc_supported[] = { |
||||
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_SDIO }, |
||||
}; |
||||
|
||||
/*
|
||||
* TODO: |
||||
* |
||||
* This whole routine should be removed until we fully convert the ICH SPI |
||||
* driver to DM and make use of DT to pass the bios control register offset |
||||
*/ |
||||
static void unprotect_spi_flash(void) |
||||
{ |
||||
u32 bc; |
||||
|
||||
bc = pci_read_config32(QUARK_LEGACY_BRIDGE, 0xd8); |
||||
bc |= 0x1; /* unprotect the flash */ |
||||
pci_write_config32(QUARK_LEGACY_BRIDGE, 0xd8, bc); |
||||
} |
||||
|
||||
static void quark_setup_bars(void) |
||||
{ |
||||
/* GPIO - D31:F0:R44h */ |
||||
pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_GBA, |
||||
CONFIG_GPIO_BASE | IO_BAR_EN); |
||||
|
||||
/* ACPI PM1 Block - D31:F0:R48h */ |
||||
pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_PM1BLK, |
||||
CONFIG_ACPI_PM1_BASE | IO_BAR_EN); |
||||
|
||||
/* GPE0 - D31:F0:R4Ch */ |
||||
pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_GPE0BLK, |
||||
CONFIG_ACPI_GPE0_BASE | IO_BAR_EN); |
||||
|
||||
/* WDT - D31:F0:R84h */ |
||||
pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_WDTBA, |
||||
CONFIG_WDT_BASE | IO_BAR_EN); |
||||
|
||||
/* RCBA - D31:F0:RF0h */ |
||||
pci_write_config_dword(QUARK_LEGACY_BRIDGE, LB_RCBA, |
||||
CONFIG_RCBA_BASE | MEM_BAR_EN); |
||||
|
||||
/* ACPI P Block - Msg Port 04:R70h */ |
||||
msg_port_write(MSG_PORT_RMU, PBLK_BA, |
||||
CONFIG_ACPI_PBLK_BASE | IO_BAR_EN); |
||||
|
||||
/* SPI DMA - Msg Port 04:R7Ah */ |
||||
msg_port_write(MSG_PORT_RMU, SPI_DMA_BA, |
||||
CONFIG_SPI_DMA_BASE | IO_BAR_EN); |
||||
|
||||
/* PCIe ECAM */ |
||||
msg_port_write(MSG_PORT_MEM_ARBITER, AEC_CTRL, |
||||
CONFIG_PCIE_ECAM_BASE | MEM_BAR_EN); |
||||
msg_port_write(MSG_PORT_HOST_BRIDGE, HEC_REG, |
||||
CONFIG_PCIE_ECAM_BASE | MEM_BAR_EN); |
||||
} |
||||
|
||||
int arch_cpu_init(void) |
||||
{ |
||||
struct pci_controller *hose; |
||||
int ret; |
||||
|
||||
post_code(POST_CPU_INIT); |
||||
#ifdef CONFIG_SYS_X86_TSC_TIMER |
||||
timer_set_base(rdtsc()); |
||||
#endif |
||||
|
||||
ret = x86_cpu_init_f(); |
||||
if (ret) |
||||
return ret; |
||||
|
||||
ret = pci_early_init_hose(&hose); |
||||
if (ret) |
||||
return ret; |
||||
|
||||
/*
|
||||
* Quark SoC has some non-standard BARs (excluding PCI standard BARs) |
||||
* which need be initialized with suggested values |
||||
*/ |
||||
quark_setup_bars(); |
||||
|
||||
unprotect_spi_flash(); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int print_cpuinfo(void) |
||||
{ |
||||
post_code(POST_CPU_INFO); |
||||
return default_print_cpuinfo(); |
||||
} |
||||
|
||||
void reset_cpu(ulong addr) |
||||
{ |
||||
/* cold reset */ |
||||
outb(0x08, PORT_RESET); |
||||
} |
||||
|
||||
int cpu_mmc_init(bd_t *bis) |
||||
{ |
||||
return pci_mmc_init("Quark SDHCI", mmc_supported, |
||||
ARRAY_SIZE(mmc_supported)); |
||||
} |
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,446 @@ |
||||
/*
|
||||
* Copyright (C) 2013, Intel Corporation |
||||
* Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> |
||||
* |
||||
* Ported from Intel released Quark UEFI BIOS |
||||
* QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei |
||||
* |
||||
* SPDX-License-Identifier: Intel |
||||
*/ |
||||
|
||||
#ifndef _SMC_H_ |
||||
#define _SMC_H_ |
||||
|
||||
/* System Memory Controller Register Defines */ |
||||
|
||||
/* Memory Controller Message Bus Registers Offsets */ |
||||
#define DRP 0x00 |
||||
#define DTR0 0x01 |
||||
#define DTR1 0x02 |
||||
#define DTR2 0x03 |
||||
#define DTR3 0x04 |
||||
#define DTR4 0x05 |
||||
#define DPMC0 0x06 |
||||
#define DPMC1 0x07 |
||||
#define DRFC 0x08 |
||||
#define DSCH 0x09 |
||||
#define DCAL 0x0A |
||||
#define DRMC 0x0B |
||||
#define PMSTS 0x0C |
||||
#define DCO 0x0F |
||||
#define DSTAT 0x20 |
||||
#define SSKPD0 0x4A |
||||
#define SSKPD1 0x4B |
||||
#define DECCCTRL 0x60 |
||||
#define DECCSTAT 0x61 |
||||
#define DECCSBECNT 0x62 |
||||
#define DECCSBECA 0x68 |
||||
#define DECCSBECS 0x69 |
||||
#define DECCDBECA 0x6A |
||||
#define DECCDBECS 0x6B |
||||
#define DFUSESTAT 0x70 |
||||
#define SCRMSEED 0x80 |
||||
#define SCRMLO 0x81 |
||||
#define SCRMHI 0x82 |
||||
|
||||
/* DRAM init command */ |
||||
#define DCMD_MRS1(rnk, dat) (0 | ((rnk) << 22) | (1 << 3) | ((dat) << 6)) |
||||
#define DCMD_REF(rnk) (1 | ((rnk) << 22)) |
||||
#define DCMD_PRE(rnk) (2 | ((rnk) << 22)) |
||||
#define DCMD_PREA(rnk) (2 | ((rnk) << 22) | (BIT10 << 6)) |
||||
#define DCMD_ACT(rnk, row) (3 | ((rnk) << 22) | ((row) << 6)) |
||||
#define DCMD_WR(rnk, col) (4 | ((rnk) << 22) | ((col) << 6)) |
||||
#define DCMD_RD(rnk, col) (5 | ((rnk) << 22) | ((col) << 6)) |
||||
#define DCMD_ZQCS(rnk) (6 | ((rnk) << 22)) |
||||
#define DCMD_ZQCL(rnk) (6 | ((rnk) << 22) | (BIT10 << 6)) |
||||
#define DCMD_NOP(rnk) (7 | ((rnk) << 22)) |
||||
|
||||
#define DDR3_EMRS1_DIC_40 (0) |
||||
#define DDR3_EMRS1_DIC_34 (1) |
||||
|
||||
#define DDR3_EMRS1_RTTNOM_0 (0) |
||||
#define DDR3_EMRS1_RTTNOM_60 (0x04) |
||||
#define DDR3_EMRS1_RTTNOM_120 (0x40) |
||||
#define DDR3_EMRS1_RTTNOM_40 (0x44) |
||||
#define DDR3_EMRS1_RTTNOM_20 (0x200) |
||||
#define DDR3_EMRS1_RTTNOM_30 (0x204) |
||||
|
||||
#define DDR3_EMRS2_RTTWR_60 (1 << 9) |
||||
#define DDR3_EMRS2_RTTWR_120 (1 << 10) |
||||
|
||||
/* BEGIN DDRIO Registers */ |
||||
|
||||
/* DDR IOs & COMPs */ |
||||
#define DDRIODQ_BL_OFFSET 0x0800 |
||||
#define DDRIODQ_CH_OFFSET ((NUM_BYTE_LANES / 2) * DDRIODQ_BL_OFFSET) |
||||
#define DDRIOCCC_CH_OFFSET 0x0800 |
||||
#define DDRCOMP_CH_OFFSET 0x0100 |
||||
|
||||
/* CH0-BL01-DQ */ |
||||
#define DQOBSCKEBBCTL 0x0000 |
||||
#define DQDLLTXCTL 0x0004 |
||||
#define DQDLLRXCTL 0x0008 |
||||
#define DQMDLLCTL 0x000C |
||||
#define B0RXIOBUFCTL 0x0010 |
||||
#define B0VREFCTL 0x0014 |
||||
#define B0RXOFFSET1 0x0018 |
||||
#define B0RXOFFSET0 0x001C |
||||
#define B1RXIOBUFCTL 0x0020 |
||||
#define B1VREFCTL 0x0024 |
||||
#define B1RXOFFSET1 0x0028 |
||||
#define B1RXOFFSET0 0x002C |
||||
#define DQDFTCTL 0x0030 |
||||
#define DQTRAINSTS 0x0034 |
||||
#define B1DLLPICODER0 0x0038 |
||||
#define B0DLLPICODER0 0x003C |
||||
#define B1DLLPICODER1 0x0040 |
||||
#define B0DLLPICODER1 0x0044 |
||||
#define B1DLLPICODER2 0x0048 |
||||
#define B0DLLPICODER2 0x004C |
||||
#define B1DLLPICODER3 0x0050 |
||||
#define B0DLLPICODER3 0x0054 |
||||
#define B1RXDQSPICODE 0x0058 |
||||
#define B0RXDQSPICODE 0x005C |
||||
#define B1RXDQPICODER32 0x0060 |
||||
#define B1RXDQPICODER10 0x0064 |
||||
#define B0RXDQPICODER32 0x0068 |
||||
#define B0RXDQPICODER10 0x006C |
||||
#define B01PTRCTL0 0x0070 |
||||
#define B01PTRCTL1 0x0074 |
||||
#define B01DBCTL0 0x0078 |
||||
#define B01DBCTL1 0x007C |
||||
#define B0LATCTL0 0x0080 |
||||
#define B1LATCTL0 0x0084 |
||||
#define B01LATCTL1 0x0088 |
||||
#define B0ONDURCTL 0x008C |
||||
#define B1ONDURCTL 0x0090 |
||||
#define B0OVRCTL 0x0094 |
||||
#define B1OVRCTL 0x0098 |
||||
#define DQCTL 0x009C |
||||
#define B0RK2RKCHGPTRCTRL 0x00A0 |
||||
#define B1RK2RKCHGPTRCTRL 0x00A4 |
||||
#define DQRK2RKCTL 0x00A8 |
||||
#define DQRK2RKPTRCTL 0x00AC |
||||
#define B0RK2RKLAT 0x00B0 |
||||
#define B1RK2RKLAT 0x00B4 |
||||
#define DQCLKALIGNREG0 0x00B8 |
||||
#define DQCLKALIGNREG1 0x00BC |
||||
#define DQCLKALIGNREG2 0x00C0 |
||||
#define DQCLKALIGNSTS0 0x00C4 |
||||
#define DQCLKALIGNSTS1 0x00C8 |
||||
#define DQCLKGATE 0x00CC |
||||
#define B0COMPSLV1 0x00D0 |
||||
#define B1COMPSLV1 0x00D4 |
||||
#define B0COMPSLV2 0x00D8 |
||||
#define B1COMPSLV2 0x00DC |
||||
#define B0COMPSLV3 0x00E0 |
||||
#define B1COMPSLV3 0x00E4 |
||||
#define DQVISALANECR0TOP 0x00E8 |
||||
#define DQVISALANECR1TOP 0x00EC |
||||
#define DQVISACONTROLCRTOP 0x00F0 |
||||
#define DQVISALANECR0BL 0x00F4 |
||||
#define DQVISALANECR1BL 0x00F8 |
||||
#define DQVISACONTROLCRBL 0x00FC |
||||
#define DQTIMINGCTRL 0x010C |
||||
|
||||
/* CH0-ECC */ |
||||
#define ECCDLLTXCTL 0x2004 |
||||
#define ECCDLLRXCTL 0x2008 |
||||
#define ECCMDLLCTL 0x200C |
||||
#define ECCB1DLLPICODER0 0x2038 |
||||
#define ECCB1DLLPICODER1 0x2040 |
||||
#define ECCB1DLLPICODER2 0x2048 |
||||
#define ECCB1DLLPICODER3 0x2050 |
||||
#define ECCB01DBCTL0 0x2078 |
||||
#define ECCB01DBCTL1 0x207C |
||||
#define ECCCLKALIGNREG0 0x20B8 |
||||
#define ECCCLKALIGNREG1 0x20BC |
||||
#define ECCCLKALIGNREG2 0x20C0 |
||||
|
||||
/* CH0-CMD */ |
||||
#define CMDOBSCKEBBCTL 0x4800 |
||||
#define CMDDLLTXCTL 0x4808 |
||||
#define CMDDLLRXCTL 0x480C |
||||
#define CMDMDLLCTL 0x4810 |
||||
#define CMDRCOMPODT 0x4814 |
||||
#define CMDDLLPICODER0 0x4820 |
||||
#define CMDDLLPICODER1 0x4824 |
||||
#define CMDCFGREG0 0x4840 |
||||
#define CMDPTRREG 0x4844 |
||||
#define CMDCLKALIGNREG0 0x4850 |
||||
#define CMDCLKALIGNREG1 0x4854 |
||||
#define CMDCLKALIGNREG2 0x4858 |
||||
#define CMDPMCONFIG0 0x485C |
||||
#define CMDPMDLYREG0 0x4860 |
||||
#define CMDPMDLYREG1 0x4864 |
||||
#define CMDPMDLYREG2 0x4868 |
||||
#define CMDPMDLYREG3 0x486C |
||||
#define CMDPMDLYREG4 0x4870 |
||||
#define CMDCLKALIGNSTS0 0x4874 |
||||
#define CMDCLKALIGNSTS1 0x4878 |
||||
#define CMDPMSTS0 0x487C |
||||
#define CMDPMSTS1 0x4880 |
||||
#define CMDCOMPSLV 0x4884 |
||||
#define CMDBONUS0 0x488C |
||||
#define CMDBONUS1 0x4890 |
||||
#define CMDVISALANECR0 0x4894 |
||||
#define CMDVISALANECR1 0x4898 |
||||
#define CMDVISACONTROLCR 0x489C |
||||
#define CMDCLKGATE 0x48A0 |
||||
#define CMDTIMINGCTRL 0x48A4 |
||||
|
||||
/* CH0-CLK-CTL */ |
||||
#define CCOBSCKEBBCTL 0x5800 |
||||
#define CCRCOMPIO 0x5804 |
||||
#define CCDLLTXCTL 0x5808 |
||||
#define CCDLLRXCTL 0x580C |
||||
#define CCMDLLCTL 0x5810 |
||||
#define CCRCOMPODT 0x5814 |
||||
#define CCDLLPICODER0 0x5820 |
||||
#define CCDLLPICODER1 0x5824 |
||||
#define CCDDR3RESETCTL 0x5830 |
||||
#define CCCFGREG0 0x5838 |
||||
#define CCCFGREG1 0x5840 |
||||
#define CCPTRREG 0x5844 |
||||
#define CCCLKALIGNREG0 0x5850 |
||||
#define CCCLKALIGNREG1 0x5854 |
||||
#define CCCLKALIGNREG2 0x5858 |
||||
#define CCPMCONFIG0 0x585C |
||||
#define CCPMDLYREG0 0x5860 |
||||
#define CCPMDLYREG1 0x5864 |
||||
#define CCPMDLYREG2 0x5868 |
||||
#define CCPMDLYREG3 0x586C |
||||
#define CCPMDLYREG4 0x5870 |
||||
#define CCCLKALIGNSTS0 0x5874 |
||||
#define CCCLKALIGNSTS1 0x5878 |
||||
#define CCPMSTS0 0x587C |
||||
#define CCPMSTS1 0x5880 |
||||
#define CCCOMPSLV1 0x5884 |
||||
#define CCCOMPSLV2 0x5888 |
||||
#define CCCOMPSLV3 0x588C |
||||
#define CCBONUS0 0x5894 |
||||
#define CCBONUS1 0x5898 |
||||
#define CCVISALANECR0 0x589C |
||||
#define CCVISALANECR1 0x58A0 |
||||
#define CCVISACONTROLCR 0x58A4 |
||||
#define CCCLKGATE 0x58A8 |
||||
#define CCTIMINGCTL 0x58AC |
||||
|
||||
/* COMP */ |
||||
#define CMPCTRL 0x6800 |
||||
#define SOFTRSTCNTL 0x6804 |
||||
#define MSCNTR 0x6808 |
||||
#define NMSCNTRL 0x680C |
||||
#define LATCH1CTL 0x6814 |
||||
#define COMPVISALANECR0 0x681C |
||||
#define COMPVISALANECR1 0x6820 |
||||
#define COMPVISACONTROLCR 0x6824 |
||||
#define COMPBONUS0 0x6830 |
||||
#define TCOCNTCTRL 0x683C |
||||
#define DQANAODTPUCTL 0x6840 |
||||
#define DQANAODTPDCTL 0x6844 |
||||
#define DQANADRVPUCTL 0x6848 |
||||
#define DQANADRVPDCTL 0x684C |
||||
#define DQANADLYPUCTL 0x6850 |
||||
#define DQANADLYPDCTL 0x6854 |
||||
#define DQANATCOPUCTL 0x6858 |
||||
#define DQANATCOPDCTL 0x685C |
||||
#define CMDANADRVPUCTL 0x6868 |
||||
#define CMDANADRVPDCTL 0x686C |
||||
#define CMDANADLYPUCTL 0x6870 |
||||
#define CMDANADLYPDCTL 0x6874 |
||||
#define CLKANAODTPUCTL 0x6880 |
||||
#define CLKANAODTPDCTL 0x6884 |
||||
#define CLKANADRVPUCTL 0x6888 |
||||
#define CLKANADRVPDCTL 0x688C |
||||
#define CLKANADLYPUCTL 0x6890 |
||||
#define CLKANADLYPDCTL 0x6894 |
||||
#define CLKANATCOPUCTL 0x6898 |
||||
#define CLKANATCOPDCTL 0x689C |
||||
#define DQSANAODTPUCTL 0x68A0 |
||||
#define DQSANAODTPDCTL 0x68A4 |
||||
#define DQSANADRVPUCTL 0x68A8 |
||||
#define DQSANADRVPDCTL 0x68AC |
||||
#define DQSANADLYPUCTL 0x68B0 |
||||
#define DQSANADLYPDCTL 0x68B4 |
||||
#define DQSANATCOPUCTL 0x68B8 |
||||
#define DQSANATCOPDCTL 0x68BC |
||||
#define CTLANADRVPUCTL 0x68C8 |
||||
#define CTLANADRVPDCTL 0x68CC |
||||
#define CTLANADLYPUCTL 0x68D0 |
||||
#define CTLANADLYPDCTL 0x68D4 |
||||
#define CHNLBUFSTATIC 0x68F0 |
||||
#define COMPOBSCNTRL 0x68F4 |
||||
#define COMPBUFFDBG0 0x68F8 |
||||
#define COMPBUFFDBG1 0x68FC |
||||
#define CFGMISCCH0 0x6900 |
||||
#define COMPEN0CH0 0x6904 |
||||
#define COMPEN1CH0 0x6908 |
||||
#define COMPEN2CH0 0x690C |
||||
#define STATLEGEN0CH0 0x6910 |
||||
#define STATLEGEN1CH0 0x6914 |
||||
#define DQVREFCH0 0x6918 |
||||
#define CMDVREFCH0 0x691C |
||||
#define CLKVREFCH0 0x6920 |
||||
#define DQSVREFCH0 0x6924 |
||||
#define CTLVREFCH0 0x6928 |
||||
#define TCOVREFCH0 0x692C |
||||
#define DLYSELCH0 0x6930 |
||||
#define TCODRAMBUFODTCH0 0x6934 |
||||
#define CCBUFODTCH0 0x6938 |
||||
#define RXOFFSETCH0 0x693C |
||||
#define DQODTPUCTLCH0 0x6940 |
||||
#define DQODTPDCTLCH0 0x6944 |
||||
#define DQDRVPUCTLCH0 0x6948 |
||||
#define DQDRVPDCTLCH0 0x694C |
||||
#define DQDLYPUCTLCH0 0x6950 |
||||
#define DQDLYPDCTLCH0 0x6954 |
||||
#define DQTCOPUCTLCH0 0x6958 |
||||
#define DQTCOPDCTLCH0 0x695C |
||||
#define CMDDRVPUCTLCH0 0x6968 |
||||
#define CMDDRVPDCTLCH0 0x696C |
||||
#define CMDDLYPUCTLCH0 0x6970 |
||||
#define CMDDLYPDCTLCH0 0x6974 |
||||
#define CLKODTPUCTLCH0 0x6980 |
||||
#define CLKODTPDCTLCH0 0x6984 |
||||
#define CLKDRVPUCTLCH0 0x6988 |
||||
#define CLKDRVPDCTLCH0 0x698C |
||||
#define CLKDLYPUCTLCH0 0x6990 |
||||
#define CLKDLYPDCTLCH0 0x6994 |
||||
#define CLKTCOPUCTLCH0 0x6998 |
||||
#define CLKTCOPDCTLCH0 0x699C |
||||
#define DQSODTPUCTLCH0 0x69A0 |
||||
#define DQSODTPDCTLCH0 0x69A4 |
||||
#define DQSDRVPUCTLCH0 0x69A8 |
||||
#define DQSDRVPDCTLCH0 0x69AC |
||||
#define DQSDLYPUCTLCH0 0x69B0 |
||||
#define DQSDLYPDCTLCH0 0x69B4 |
||||
#define DQSTCOPUCTLCH0 0x69B8 |
||||
#define DQSTCOPDCTLCH0 0x69BC |
||||
#define CTLDRVPUCTLCH0 0x69C8 |
||||
#define CTLDRVPDCTLCH0 0x69CC |
||||
#define CTLDLYPUCTLCH0 0x69D0 |
||||
#define CTLDLYPDCTLCH0 0x69D4 |
||||
#define FNLUPDTCTLCH0 0x69F0 |
||||
|
||||
/* PLL */ |
||||
#define MPLLCTRL0 0x7800 |
||||
#define MPLLCTRL1 0x7808 |
||||
#define MPLLCSR0 0x7810 |
||||
#define MPLLCSR1 0x7814 |
||||
#define MPLLCSR2 0x7820 |
||||
#define MPLLDFT 0x7828 |
||||
#define MPLLMON0CTL 0x7830 |
||||
#define MPLLMON1CTL 0x7838 |
||||
#define MPLLMON2CTL 0x783C |
||||
#define SFRTRIM 0x7850 |
||||
#define MPLLDFTOUT0 0x7858 |
||||
#define MPLLDFTOUT1 0x785C |
||||
#define MASTERRSTN 0x7880 |
||||
#define PLLLOCKDEL 0x7884 |
||||
#define SFRDEL 0x7888 |
||||
#define CRUVISALANECR0 0x78F0 |
||||
#define CRUVISALANECR1 0x78F4 |
||||
#define CRUVISACONTROLCR 0x78F8 |
||||
#define IOSFVISALANECR0 0x78FC |
||||
#define IOSFVISALANECR1 0x7900 |
||||
#define IOSFVISACONTROLCR 0x7904 |
||||
|
||||
/* END DDRIO Registers */ |
||||
|
||||
/* DRAM Specific Message Bus OpCodes */ |
||||
#define MSG_OP_DRAM_INIT 0x68 |
||||
#define MSG_OP_DRAM_WAKE 0xCA |
||||
|
||||
#define SAMPLE_SIZE 6 |
||||
|
||||
/* must be less than this number to enable early deadband */ |
||||
#define EARLY_DB 0x12 |
||||
/* must be greater than this number to enable late deadband */ |
||||
#define LATE_DB 0x34 |
||||
|
||||
#define CHX_REGS (11 * 4) |
||||
#define FULL_CLK 128 |
||||
#define HALF_CLK 64 |
||||
#define QRTR_CLK 32 |
||||
|
||||
#define MCEIL(num, den) ((uint8_t)((num + den - 1) / den)) |
||||
#define MMAX(a, b) ((a) > (b) ? (a) : (b)) |
||||
#define DEAD_LOOP() for (;;); |
||||
|
||||
#define MIN_RDQS_EYE 10 /* in PI Codes */ |
||||
#define MIN_VREF_EYE 10 /* in VREF Codes */ |
||||
/* how many RDQS codes to jump while margining */ |
||||
#define RDQS_STEP 1 |
||||
/* how many VREF codes to jump while margining */ |
||||
#define VREF_STEP 1 |
||||
/* offset into "vref_codes[]" for minimum allowed VREF setting */ |
||||
#define VREF_MIN 0x00 |
||||
/* offset into "vref_codes[]" for maximum allowed VREF setting */ |
||||
#define VREF_MAX 0x3F |
||||
#define RDQS_MIN 0x00 /* minimum RDQS delay value */ |
||||
#define RDQS_MAX 0x3F /* maximum RDQS delay value */ |
||||
|
||||
/* how many WDQ codes to jump while margining */ |
||||
#define WDQ_STEP 1 |
||||
|
||||
enum { |
||||
B, /* BOTTOM VREF */ |
||||
T /* TOP VREF */ |
||||
}; |
||||
|
||||
enum { |
||||
L, /* LEFT RDQS */ |
||||
R /* RIGHT RDQS */ |
||||
}; |
||||
|
||||
/* Memory Options */ |
||||
|
||||
/* enable STATIC timing settings for RCVN (BACKUP_MODE) */ |
||||
#undef BACKUP_RCVN |
||||
/* enable STATIC timing settings for WDQS (BACKUP_MODE) */ |
||||
#undef BACKUP_WDQS |
||||
/* enable STATIC timing settings for RDQS (BACKUP_MODE) */ |
||||
#undef BACKUP_RDQS |
||||
/* enable STATIC timing settings for WDQ (BACKUP_MODE) */ |
||||
#undef BACKUP_WDQ |
||||
/* enable *COMP overrides (BACKUP_MODE) */ |
||||
#undef BACKUP_COMPS |
||||
/* enable the RD_TRAIN eye check */ |
||||
#undef RX_EYE_CHECK |
||||
|
||||
/* enable Host to Memory Clock Alignment */ |
||||
#define HMC_TEST |
||||
/* enable multi-rank support via rank2rank sharing */ |
||||
#define R2R_SHARING |
||||
/* disable signals not used in 16bit mode of DDRIO */ |
||||
#define FORCE_16BIT_DDRIO |
||||
|
||||
#define PLATFORM_ID 1 |
||||
|
||||
void clear_self_refresh(struct mrc_params *mrc_params); |
||||
void prog_ddr_timing_control(struct mrc_params *mrc_params); |
||||
void prog_decode_before_jedec(struct mrc_params *mrc_params); |
||||
void perform_ddr_reset(struct mrc_params *mrc_params); |
||||
void ddrphy_init(struct mrc_params *mrc_params); |
||||
void perform_jedec_init(struct mrc_params *mrc_params); |
||||
void set_ddr_init_complete(struct mrc_params *mrc_params); |
||||
void restore_timings(struct mrc_params *mrc_params); |
||||
void default_timings(struct mrc_params *mrc_params); |
||||
void rcvn_cal(struct mrc_params *mrc_params); |
||||
void wr_level(struct mrc_params *mrc_params); |
||||
void prog_page_ctrl(struct mrc_params *mrc_params); |
||||
void rd_train(struct mrc_params *mrc_params); |
||||
void wr_train(struct mrc_params *mrc_params); |
||||
void store_timings(struct mrc_params *mrc_params); |
||||
void enable_scrambling(struct mrc_params *mrc_params); |
||||
void prog_ddr_control(struct mrc_params *mrc_params); |
||||
void prog_dra_drb(struct mrc_params *mrc_params); |
||||
void perform_wake(struct mrc_params *mrc_params); |
||||
void change_refresh_period(struct mrc_params *mrc_params); |
||||
void set_auto_refresh(struct mrc_params *mrc_params); |
||||
void ecc_enable(struct mrc_params *mrc_params); |
||||
void memory_test(struct mrc_params *mrc_params); |
||||
void lock_registers(struct mrc_params *mrc_params); |
||||
|
||||
#endif /* _SMC_H_ */ |
||||
@ -0,0 +1,95 @@ |
||||
/* |
||||
* Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
/dts-v1/; |
||||
|
||||
#include <dt-bindings/mrc/quark.h> |
||||
|
||||
/include/ "skeleton.dtsi" |
||||
|
||||
/ { |
||||
model = "Intel Galileo"; |
||||
compatible = "intel,galileo", "intel,quark"; |
||||
|
||||
config { |
||||
silent_console = <0>; |
||||
}; |
||||
|
||||
chosen { |
||||
stdout-path = &pciuart0; |
||||
}; |
||||
|
||||
mrc { |
||||
compatible = "intel,quark-mrc"; |
||||
flags = <MRC_FLAG_SCRAMBLE_EN>; |
||||
dram-width = <DRAM_WIDTH_X8>; |
||||
dram-speed = <DRAM_FREQ_800>; |
||||
dram-type = <DRAM_TYPE_DDR3>; |
||||
rank-mask = <DRAM_RANK(0)>; |
||||
chan-mask = <DRAM_CHANNEL(0)>; |
||||
chan-width = <DRAM_CHANNEL_WIDTH_X16>; |
||||
addr-mode = <DRAM_ADDR_MODE0>; |
||||
refresh-rate = <DRAM_REFRESH_RATE_785US>; |
||||
sr-temp-range = <DRAM_SRT_RANGE_NORMAL>; |
||||
ron-value = <DRAM_RON_34OHM>; |
||||
rtt-nom-value = <DRAM_RTT_NOM_120OHM>; |
||||
rd-odt-value = <DRAM_RD_ODT_OFF>; |
||||
dram-density = <DRAM_DENSITY_1G>; |
||||
dram-cl = <6>; |
||||
dram-ras = <0x0000927c>; |
||||
dram-wtr = <0x00002710>; |
||||
dram-rrd = <0x00002710>; |
||||
dram-faw = <0x00009c40>; |
||||
}; |
||||
|
||||
pci { |
||||
#address-cells = <3>; |
||||
#size-cells = <2>; |
||||
compatible = "intel,pci"; |
||||
device_type = "pci"; |
||||
|
||||
pciuart0: uart@14,5 { |
||||
compatible = "pci8086,0936.00", |
||||
"pci8086,0936", |
||||
"pciclass,070002", |
||||
"pciclass,0700", |
||||
"x86-uart"; |
||||
reg = <0x0000a500 0x0 0x0 0x0 0x0 |
||||
0x0200a510 0x0 0x0 0x0 0x0>; |
||||
reg-shift = <2>; |
||||
clock-frequency = <44236800>; |
||||
current-speed = <115200>; |
||||
}; |
||||
}; |
||||
|
||||
gpioa { |
||||
compatible = "intel,ich6-gpio"; |
||||
u-boot,dm-pre-reloc; |
||||
reg = <0 0x20>; |
||||
bank-name = "A"; |
||||
}; |
||||
|
||||
gpiob { |
||||
compatible = "intel,ich6-gpio"; |
||||
u-boot,dm-pre-reloc; |
||||
reg = <0x20 0x20>; |
||||
bank-name = "B"; |
||||
}; |
||||
|
||||
spi { |
||||
#address-cells = <1>; |
||||
#size-cells = <0>; |
||||
compatible = "intel,ich-spi"; |
||||
spi-flash@0 { |
||||
#size-cells = <1>; |
||||
#address-cells = <1>; |
||||
reg = <0>; |
||||
compatible = "winbond,w25q64", "spi-flash"; |
||||
memory-map = <0xff800000 0x00800000>; |
||||
}; |
||||
}; |
||||
|
||||
}; |
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,45 @@ |
||||
/* |
||||
* Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
/dts-v1/; |
||||
|
||||
/include/ "skeleton.dtsi" |
||||
/include/ "serial.dtsi" |
||||
|
||||
/ { |
||||
model = "Intel Minnowboard Max"; |
||||
compatible = "intel,minnowmax", "intel,baytrail"; |
||||
|
||||
aliases { |
||||
serial0 = &serial; |
||||
}; |
||||
|
||||
config { |
||||
silent_console = <0>; |
||||
}; |
||||
|
||||
chosen { |
||||
stdout-path = "/serial"; |
||||
}; |
||||
|
||||
spi { |
||||
#address-cells = <1>; |
||||
#size-cells = <0>; |
||||
compatible = "intel,ich"; |
||||
spi-flash@0 { |
||||
reg = <0>; |
||||
compatible = "sst,25vf016b", "spi-flash"; |
||||
memory-map = <0xff800000 0x00800000>; |
||||
}; |
||||
}; |
||||
|
||||
microcode { |
||||
update@0 { |
||||
#include "microcode/m0130673322.dtsi" |
||||
}; |
||||
}; |
||||
|
||||
}; |
||||
@ -0,0 +1,39 @@ |
||||
/*
|
||||
* Copyright (C) 2013, Intel Corporation |
||||
* Copyright (C) 2015 Google, Inc |
||||
* |
||||
* SPDX-License-Identifier: Intel |
||||
*/ |
||||
|
||||
#ifndef _FSP_AZALIA_H_ |
||||
#define _FSP_AZALIA_H_ |
||||
|
||||
struct __packed pch_azalia_verb_table_header { |
||||
uint32_t vendor_device_id; |
||||
uint16_t sub_system_id; |
||||
uint8_t revision_id; /* 0xff applies to all steppings */ |
||||
uint8_t front_panel_support; |
||||
uint16_t number_of_rear_jacks; |
||||
uint16_t number_of_front_jacks; |
||||
}; |
||||
|
||||
struct __packed pch_azalia_verb_table { |
||||
struct pch_azalia_verb_table_header verb_table_header; |
||||
const uint32_t *verb_table_data; |
||||
}; |
||||
|
||||
struct __packed pch_azalia_config { |
||||
uint8_t pme_enable:1; |
||||
uint8_t docking_supported:1; |
||||
uint8_t docking_attached:1; |
||||
uint8_t hdmi_codec_enable:1; |
||||
uint8_t azalia_v_ci_enable:1; |
||||
uint8_t rsvdbits:3; |
||||
/* number of verb tables provided by platform */ |
||||
uint8_t azalia_verb_table_num; |
||||
const struct pch_azalia_verb_table *azalia_verb_table; |
||||
/* delay timer after azalia reset */ |
||||
uint16_t reset_wait_timer_us; |
||||
}; |
||||
|
||||
#endif |
||||
@ -0,0 +1,95 @@ |
||||
/*
|
||||
* Copyright (C) 2013, Intel Corporation |
||||
* Copyright (C) 2015 Google, Inc |
||||
* |
||||
* SPDX-License-Identifier: Intel |
||||
*/ |
||||
|
||||
#ifndef __FSP_VPD_H |
||||
#define __FSP_VPD_H |
||||
|
||||
struct memory_down_data { |
||||
uint8_t enable_memory_down; |
||||
uint8_t dram_speed; |
||||
uint8_t dram_type; |
||||
uint8_t dimm_0_enable; |
||||
uint8_t dimm_1_enable; |
||||
uint8_t dimm_width; |
||||
uint8_t dimm_density; |
||||
uint8_t dimm_bus_width; |
||||
uint8_t dimm_sides; /* Ranks Per dimm_ */ |
||||
uint8_t dimm_tcl; /* tCL */ |
||||
/* tRP and tRCD in DRAM clk - 5:12.5ns, 6:15ns, etc. */ |
||||
uint8_t dimm_trpt_rcd; |
||||
uint8_t dimm_twr; /* tWR in DRAM clk */ |
||||
uint8_t dimm_twtr; /* tWTR in DRAM clk */ |
||||
uint8_t dimm_trrd; /* tRRD in DRAM clk */ |
||||
uint8_t dimm_trtp; /* tRTP in DRAM clk */ |
||||
uint8_t dimm_tfaw; /* tFAW in DRAM clk */ |
||||
}; |
||||
|
||||
struct __packed upd_region { |
||||
uint64_t signature; /* Offset 0x0000 */ |
||||
uint8_t reserved0[24]; /* Offset 0x0008 */ |
||||
uint16_t mrc_init_tseg_size; /* Offset 0x0020 */ |
||||
uint16_t mrc_init_mmio_size; /* Offset 0x0022 */ |
||||
uint8_t mrc_init_spd_addr1; /* Offset 0x0024 */ |
||||
uint8_t mrc_init_spd_addr2; /* Offset 0x0025 */ |
||||
uint8_t emmc_boot_mode; /* Offset 0x0026 */ |
||||
uint8_t enable_sdio; /* Offset 0x0027 */ |
||||
uint8_t enable_sdcard; /* Offset 0x0028 */ |
||||
uint8_t enable_hsuart0; /* Offset 0x0029 */ |
||||
uint8_t enable_hsuart1; /* Offset 0x002a */ |
||||
uint8_t enable_spi; /* Offset 0x002b */ |
||||
uint8_t reserved1; /* Offset 0x002c */ |
||||
uint8_t enable_sata; /* Offset 0x002d */ |
||||
uint8_t sata_mode; /* Offset 0x002e */ |
||||
uint8_t enable_azalia; /* Offset 0x002f */ |
||||
uint32_t azalia_config_ptr; /* Offset 0x0030 */ |
||||
uint8_t enable_xhci; /* Offset 0x0034 */ |
||||
uint8_t enable_lpe; /* Offset 0x0035 */ |
||||
uint8_t lpss_sio_enable_pci_mode; /* Offset 0x0036 */ |
||||
uint8_t enable_dma0; /* Offset 0x0037 */ |
||||
uint8_t enable_dma1; /* Offset 0x0038 */ |
||||
uint8_t enable_i2_c0; /* Offset 0x0039 */ |
||||
uint8_t enable_i2_c1; /* Offset 0x003a */ |
||||
uint8_t enable_i2_c2; /* Offset 0x003b */ |
||||
uint8_t enable_i2_c3; /* Offset 0x003c */ |
||||
uint8_t enable_i2_c4; /* Offset 0x003d */ |
||||
uint8_t enable_i2_c5; /* Offset 0x003e */ |
||||
uint8_t enable_i2_c6; /* Offset 0x003f */ |
||||
uint8_t enable_pwm0; /* Offset 0x0040 */ |
||||
uint8_t enable_pwm1; /* Offset 0x0041 */ |
||||
uint8_t enable_hsi; /* Offset 0x0042 */ |
||||
uint8_t igd_dvmt50_pre_alloc; /* Offset 0x0043 */ |
||||
uint8_t aperture_size; /* Offset 0x0044 */ |
||||
uint8_t gtt_size; /* Offset 0x0045 */ |
||||
uint32_t serial_debug_port_address; /* Offset 0x0046 */ |
||||
uint8_t serial_debug_port_type; /* Offset 0x004a */ |
||||
uint8_t mrc_debug_msg; /* Offset 0x004b */ |
||||
uint8_t isp_enable; /* Offset 0x004c */ |
||||
uint8_t scc_enable_pci_mode; /* Offset 0x004d */ |
||||
uint8_t igd_render_standby; /* Offset 0x004e */ |
||||
uint8_t txe_uma_enable; /* Offset 0x004f */ |
||||
uint8_t os_selection; /* Offset 0x0050 */ |
||||
uint8_t emmc45_ddr50_enabled; /* Offset 0x0051 */ |
||||
uint8_t emmc45_hs200_enabled; /* Offset 0x0052 */ |
||||
uint8_t emmc45_retune_timer_value; /* Offset 0x0053 */ |
||||
uint8_t unused_upd_space1[156]; /* Offset 0x0054 */ |
||||
struct memory_down_data memory_params; /* Offset 0x00f0 */ |
||||
uint16_t terminator; /* Offset 0x0100 */ |
||||
}; |
||||
|
||||
#define VPD_IMAGE_ID 0x3157454956594C56 /* 'VLYVIEW1' */ |
||||
#define VPD_IMAGE_REV 0x00000303 |
||||
|
||||
struct __packed vpd_region { |
||||
uint64_t sign; /* Offset 0x0000 */ |
||||
uint32_t img_rev; /* Offset 0x0008 */ |
||||
uint32_t upd_offset; /* Offset 0x000c */ |
||||
uint8_t unused[16]; /* Offset 0x0010 */ |
||||
uint32_t fsp_res_memlen; /* Offset 0x0020 */ |
||||
uint8_t platform_type; /* Offset 0x0024 */ |
||||
uint8_t enable_secure_boot; /* Offset 0x0025 */ |
||||
}; |
||||
#endif |
||||
@ -0,0 +1,13 @@ |
||||
/*
|
||||
* Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef _X86_ARCH_GPIO_H_ |
||||
#define _X86_ARCH_GPIO_H_ |
||||
|
||||
/* Where in config space is the register that points to the GPIO registers? */ |
||||
#define PCI_CFG_GPIOBASE 0x44 |
||||
|
||||
#endif /* _X86_ARCH_GPIO_H_ */ |
||||
@ -0,0 +1,28 @@ |
||||
/*
|
||||
* Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef _QUARK_DEVICE_H_ |
||||
#define _QUARK_DEVICE_H_ |
||||
|
||||
#include <pci.h> |
||||
|
||||
#define QUARK_HOST_BRIDGE PCI_BDF(0, 0, 0) |
||||
#define QUARK_MMC_SDIO PCI_BDF(0, 20, 0) |
||||
#define QUARK_UART0 PCI_BDF(0, 20, 1) |
||||
#define QUARK_USB_DEVICE PCI_BDF(0, 20, 2) |
||||
#define QUARK_USB_EHCI PCI_BDF(0, 20, 3) |
||||
#define QUARK_USB_OHCI PCI_BDF(0, 20, 4) |
||||
#define QUARK_UART1 PCI_BDF(0, 20, 5) |
||||
#define QUARK_EMAC0 PCI_BDF(0, 20, 6) |
||||
#define QUARK_EMAC1 PCI_BDF(0, 20, 7) |
||||
#define QUARK_SPI0 PCI_BDF(0, 21, 0) |
||||
#define QUARK_SPI1 PCI_BDF(0, 21, 1) |
||||
#define QUARK_I2C_GPIO PCI_BDF(0, 21, 2) |
||||
#define QUARK_PCIE0 PCI_BDF(0, 23, 0) |
||||
#define QUARK_PCIE1 PCI_BDF(0, 23, 1) |
||||
#define QUARK_LEGACY_BRIDGE PCI_BDF(0, 31, 0) |
||||
|
||||
#endif /* _QUARK_DEVICE_H_ */ |
||||
@ -0,0 +1,13 @@ |
||||
/*
|
||||
* Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef _X86_ARCH_GPIO_H_ |
||||
#define _X86_ARCH_GPIO_H_ |
||||
|
||||
/* Where in config space is the register that points to the GPIO registers? */ |
||||
#define PCI_CFG_GPIOBASE 0x44 |
||||
|
||||
#endif /* _X86_ARCH_GPIO_H_ */ |
||||
@ -0,0 +1,187 @@ |
||||
/*
|
||||
* Copyright (C) 2013, Intel Corporation |
||||
* Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> |
||||
* |
||||
* Ported from Intel released Quark UEFI BIOS |
||||
* QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei |
||||
* |
||||
* SPDX-License-Identifier: Intel |
||||
*/ |
||||
|
||||
#ifndef _MRC_H_ |
||||
#define _MRC_H_ |
||||
|
||||
#define MRC_VERSION 0x0111 |
||||
|
||||
/* architectural definitions */ |
||||
#define NUM_CHANNELS 1 /* number of channels */ |
||||
#define NUM_RANKS 2 /* number of ranks per channel */ |
||||
#define NUM_BYTE_LANES 4 /* number of byte lanes per channel */ |
||||
|
||||
/* software limitations */ |
||||
#define MAX_CHANNELS 1 |
||||
#define MAX_RANKS 2 |
||||
#define MAX_BYTE_LANES 4 |
||||
|
||||
#define MAX_SOCKETS 1 |
||||
#define MAX_SIDES 1 |
||||
#define MAX_ROWS (MAX_SIDES * MAX_SOCKETS) |
||||
|
||||
/* Specify DRAM and channel width */ |
||||
enum { |
||||
X8, /* DRAM width */ |
||||
X16, /* DRAM width & Channel Width */ |
||||
X32 /* Channel Width */ |
||||
}; |
||||
|
||||
/* Specify DRAM speed */ |
||||
enum { |
||||
DDRFREQ_800, |
||||
DDRFREQ_1066 |
||||
}; |
||||
|
||||
/* Specify DRAM type */ |
||||
enum { |
||||
DDR3, |
||||
DDR3L |
||||
}; |
||||
|
||||
/*
|
||||
* density: 0=512Mb, 1=Gb, 2=2Gb, 3=4Gb |
||||
* cl: DRAM CAS Latency in clocks |
||||
* ras: ACT to PRE command period |
||||
* wtr: Delay from start of internal write transaction to internal read command |
||||
* rrd: ACT to ACT command period (JESD79 specific to page size 1K/2K) |
||||
* faw: Four activate window (JESD79 specific to page size 1K/2K) |
||||
* |
||||
* ras/wtr/rrd/faw timings are in picoseconds |
||||
* |
||||
* Refer to JEDEC spec (or DRAM datasheet) when changing these values. |
||||
*/ |
||||
struct dram_params { |
||||
uint8_t density; |
||||
uint8_t cl; |
||||
uint32_t ras; |
||||
uint32_t wtr; |
||||
uint32_t rrd; |
||||
uint32_t faw; |
||||
}; |
||||
|
||||
/*
|
||||
* Delay configuration for individual signals |
||||
* Vref setting |
||||
* Scrambler seed |
||||
*/ |
||||
struct mrc_timings { |
||||
uint32_t rcvn[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES]; |
||||
uint32_t rdqs[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES]; |
||||
uint32_t wdqs[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES]; |
||||
uint32_t wdq[NUM_CHANNELS][NUM_RANKS][NUM_BYTE_LANES]; |
||||
uint32_t vref[NUM_CHANNELS][NUM_BYTE_LANES]; |
||||
uint32_t wctl[NUM_CHANNELS][NUM_RANKS]; |
||||
uint32_t wcmd[NUM_CHANNELS]; |
||||
uint32_t scrambler_seed; |
||||
/* need to save for the case of frequency change */ |
||||
uint8_t ddr_speed; |
||||
}; |
||||
|
||||
/* Boot mode defined as bit mask (1<<n) */ |
||||
enum { |
||||
BM_UNKNOWN, |
||||
BM_COLD = 1, /* full training */ |
||||
BM_FAST = 2, /* restore timing parameters */ |
||||
BM_S3 = 4, /* resume from S3 */ |
||||
BM_WARM = 8 |
||||
}; |
||||
|
||||
/* MRC execution status */ |
||||
#define MRC_SUCCESS 0 /* initialization ok */ |
||||
#define MRC_E_MEMTEST 1 /* memtest failed */ |
||||
|
||||
/*
|
||||
* Memory Reference Code parameters |
||||
* |
||||
* It includes 3 parts: |
||||
* - input parameters like boot mode and DRAM parameters |
||||
* - context parameters for MRC internal state |
||||
* - output parameters like initialization result and memory size |
||||
*/ |
||||
struct mrc_params { |
||||
/* Input parameters */ |
||||
uint32_t boot_mode; /* BM_COLD, BM_FAST, BM_WARM, BM_S3 */ |
||||
/* DRAM parameters */ |
||||
uint8_t dram_width; /* x8, x16 */ |
||||
uint8_t ddr_speed; /* DDRFREQ_800, DDRFREQ_1066 */ |
||||
uint8_t ddr_type; /* DDR3, DDR3L */ |
||||
uint8_t ecc_enables; /* 0, 1 (memory size reduced to 7/8) */ |
||||
uint8_t scrambling_enables; /* 0, 1 */ |
||||
/* 1, 3 (1'st rank has to be populated if 2'nd rank present) */ |
||||
uint32_t rank_enables; |
||||
uint32_t channel_enables; /* 1 only */ |
||||
uint32_t channel_width; /* x16 only */ |
||||
/* 0, 1, 2 (mode 2 forced if ecc enabled) */ |
||||
uint32_t address_mode; |
||||
/* REFRESH_RATE: 1=1.95us, 2=3.9us, 3=7.8us, others=RESERVED */ |
||||
uint8_t refresh_rate; |
||||
/* SR_TEMP_RANGE: 0=normal, 1=extended, others=RESERVED */ |
||||
uint8_t sr_temp_range; |
||||
/*
|
||||
* RON_VALUE: 0=34ohm, 1=40ohm, others=RESERVED |
||||
* (select MRS1.DIC driver impedance control) |
||||
*/ |
||||
uint8_t ron_value; |
||||
/* RTT_NOM_VALUE: 0=40ohm, 1=60ohm, 2=120ohm, others=RESERVED */ |
||||
uint8_t rtt_nom_value; |
||||
/* RD_ODT_VALUE: 0=off, 1=60ohm, 2=120ohm, 3=180ohm, others=RESERVED */ |
||||
uint8_t rd_odt_value; |
||||
struct dram_params params; |
||||
/* Internally used context parameters */ |
||||
uint32_t board_id; /* board layout (use x8 or x16 memory) */ |
||||
uint32_t hte_setup; /* when set hte reconfiguration requested */ |
||||
uint32_t menu_after_mrc; |
||||
uint32_t power_down_disable; |
||||
uint32_t tune_rcvn; |
||||
uint32_t channel_size[NUM_CHANNELS]; |
||||
uint32_t column_bits[NUM_CHANNELS]; |
||||
uint32_t row_bits[NUM_CHANNELS]; |
||||
uint32_t mrs1; /* register content saved during training */ |
||||
uint8_t first_run; |
||||
/* Output parameters */ |
||||
/* initialization result (non zero specifies error code) */ |
||||
uint32_t status; |
||||
/* total memory size in bytes (excludes ECC banks) */ |
||||
uint32_t mem_size; |
||||
/* training results (also used on input) */ |
||||
struct mrc_timings timings; |
||||
}; |
||||
|
||||
/*
|
||||
* MRC memory initialization structure |
||||
* |
||||
* post_code: a 16-bit post code of a specific initialization routine |
||||
* boot_path: bitwise or of BM_COLD, BM_FAST, BM_WARM and BM_S3 |
||||
* init_fn: real memory initialization routine |
||||
*/ |
||||
struct mem_init { |
||||
uint16_t post_code; |
||||
uint16_t boot_path; |
||||
void (*init_fn)(struct mrc_params *mrc_params); |
||||
}; |
||||
|
||||
/* MRC platform data flags */ |
||||
#define MRC_FLAG_ECC_EN 0x00000001 |
||||
#define MRC_FLAG_SCRAMBLE_EN 0x00000002 |
||||
#define MRC_FLAG_MEMTEST_EN 0x00000004 |
||||
/* 0b DDR "fly-by" topology else 1b DDR "tree" topology */ |
||||
#define MRC_FLAG_TOP_TREE_EN 0x00000008 |
||||
/* If set ODR signal is asserted to DRAM devices on writes */ |
||||
#define MRC_FLAG_WR_ODT_EN 0x00000010 |
||||
|
||||
/**
|
||||
* mrc_init - Memory Reference Code initialization entry routine |
||||
* |
||||
* @mrc_params: parameters for MRC |
||||
*/ |
||||
void mrc_init(struct mrc_params *mrc_params); |
||||
|
||||
#endif /* _MRC_H_ */ |
||||
@ -0,0 +1,106 @@ |
||||
/*
|
||||
* Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef _QUARK_MSG_PORT_H_ |
||||
#define _QUARK_MSG_PORT_H_ |
||||
|
||||
/*
|
||||
* In the Quark SoC, some chipset commands are accomplished by utilizing |
||||
* the internal message network within the host bridge (D0:F0). Accesses |
||||
* to this network are accomplished by populating the message control |
||||
* register (MCR), Message Control Register eXtension (MCRX) and the |
||||
* message data register (MDR). |
||||
*/ |
||||
#define MSG_CTRL_REG 0xd0 /* Message Control Register */ |
||||
#define MSG_DATA_REG 0xd4 /* Message Data Register */ |
||||
#define MSG_CTRL_EXT_REG 0xd8 /* Message Control Register EXT */ |
||||
|
||||
/* Normal Read/Write OpCodes */ |
||||
#define MSG_OP_READ 0x10 |
||||
#define MSG_OP_WRITE 0x11 |
||||
|
||||
/* Alternative Read/Write OpCodes */ |
||||
#define MSG_OP_ALT_READ 0x06 |
||||
#define MSG_OP_ALT_WRITE 0x07 |
||||
|
||||
/* IO Read/Write OpCodes */ |
||||
#define MSG_OP_IO_READ 0x02 |
||||
#define MSG_OP_IO_WRITE 0x03 |
||||
|
||||
/* All byte enables */ |
||||
#define MSG_BYTE_ENABLE 0xf0 |
||||
|
||||
#ifndef __ASSEMBLY__ |
||||
|
||||
/**
|
||||
* msg_port_setup - set up the message port control register |
||||
* |
||||
* @op: message bus access opcode |
||||
* @port: port number on the message bus |
||||
* @reg: register number within a port |
||||
*/ |
||||
void msg_port_setup(int op, int port, int reg); |
||||
|
||||
/**
|
||||
* msg_port_read - read a message port register using normal opcode |
||||
* |
||||
* @port: port number on the message bus |
||||
* @reg: register number within a port |
||||
* |
||||
* @return: message port register value |
||||
*/ |
||||
u32 msg_port_read(u8 port, u32 reg); |
||||
|
||||
/**
|
||||
* msg_port_write - write a message port register using normal opcode |
||||
* |
||||
* @port: port number on the message bus |
||||
* @reg: register number within a port |
||||
* @value: register value to write |
||||
*/ |
||||
void msg_port_write(u8 port, u32 reg, u32 value); |
||||
|
||||
/**
|
||||
* msg_port_alt_read - read a message port register using alternative opcode |
||||
* |
||||
* @port: port number on the message bus |
||||
* @reg: register number within a port |
||||
* |
||||
* @return: message port register value |
||||
*/ |
||||
u32 msg_port_alt_read(u8 port, u32 reg); |
||||
|
||||
/**
|
||||
* msg_port_alt_write - write a message port register using alternative opcode |
||||
* |
||||
* @port: port number on the message bus |
||||
* @reg: register number within a port |
||||
* @value: register value to write |
||||
*/ |
||||
void msg_port_alt_write(u8 port, u32 reg, u32 value); |
||||
|
||||
/**
|
||||
* msg_port_io_read - read a message port register using I/O opcode |
||||
* |
||||
* @port: port number on the message bus |
||||
* @reg: register number within a port |
||||
* |
||||
* @return: message port register value |
||||
*/ |
||||
u32 msg_port_io_read(u8 port, u32 reg); |
||||
|
||||
/**
|
||||
* msg_port_io_write - write a message port register using I/O opcode |
||||
* |
||||
* @port: port number on the message bus |
||||
* @reg: register number within a port |
||||
* @value: register value to write |
||||
*/ |
||||
void msg_port_io_write(u8 port, u32 reg, u32 value); |
||||
|
||||
#endif /* __ASSEMBLY__ */ |
||||
|
||||
#endif /* _QUARK_MSG_PORT_H_ */ |
||||
@ -0,0 +1,72 @@ |
||||
/*
|
||||
* Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef _QUARK_H_ |
||||
#define _QUARK_H_ |
||||
|
||||
/* Message Bus Ports */ |
||||
#define MSG_PORT_MEM_ARBITER 0x00 |
||||
#define MSG_PORT_HOST_BRIDGE 0x03 |
||||
#define MSG_PORT_RMU 0x04 |
||||
#define MSG_PORT_MEM_MGR 0x05 |
||||
#define MSG_PORT_SOC_UNIT 0x31 |
||||
|
||||
/* Port 0x00: Memory Arbiter Message Port Registers */ |
||||
|
||||
/* Enhanced Configuration Space */ |
||||
#define AEC_CTRL 0x00 |
||||
|
||||
/* Port 0x03: Host Bridge Message Port Registers */ |
||||
|
||||
/* Host Memory I/O Boundary */ |
||||
#define HM_BOUND 0x08 |
||||
|
||||
/* Extended Configuration Space */ |
||||
#define HEC_REG 0x09 |
||||
|
||||
/* Port 0x04: Remote Management Unit Message Port Registers */ |
||||
|
||||
/* ACPI PBLK Base Address Register */ |
||||
#define PBLK_BA 0x70 |
||||
|
||||
/* SPI DMA Base Address Register */ |
||||
#define SPI_DMA_BA 0x7a |
||||
|
||||
/* Port 0x05: Memory Manager Message Port Registers */ |
||||
|
||||
/* eSRAM Block Page Control */ |
||||
#define ESRAM_BLK_CTRL 0x82 |
||||
#define ESRAM_BLOCK_MODE 0x10000000 |
||||
|
||||
/* DRAM */ |
||||
#define DRAM_BASE 0x00000000 |
||||
#define DRAM_MAX_SIZE 0x80000000 |
||||
|
||||
/* eSRAM */ |
||||
#define ESRAM_SIZE 0x80000 |
||||
|
||||
/* Memory BAR Enable */ |
||||
#define MEM_BAR_EN 0x00000001 |
||||
|
||||
/* I/O BAR Enable */ |
||||
#define IO_BAR_EN 0x80000000 |
||||
|
||||
/* 64KiB of RMU binary in flash */ |
||||
#define RMU_BINARY_SIZE 0x10000 |
||||
|
||||
/* Legacy Bridge PCI Configuration Registers */ |
||||
#define LB_GBA 0x44 |
||||
#define LB_PM1BLK 0x48 |
||||
#define LB_GPE0BLK 0x4c |
||||
#define LB_ACTL 0x58 |
||||
#define LB_PABCDRC 0x60 |
||||
#define LB_PEFGHRC 0x64 |
||||
#define LB_WDTBA 0x84 |
||||
#define LB_BCE 0xd4 |
||||
#define LB_BC 0xd8 |
||||
#define LB_RCBA 0xf0 |
||||
|
||||
#endif /* _QUARK_H_ */ |
||||
@ -0,0 +1,10 @@ |
||||
#
|
||||
# Copyright (C) 2015 Google, Inc
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
obj-y += fsp_car.o
|
||||
obj-y += fsp_common.o
|
||||
obj-y += fsp_dram.o
|
||||
obj-y += fsp_support.o
|
||||
@ -0,0 +1,55 @@ |
||||
/*
|
||||
* Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <errno.h> |
||||
#include <asm/io.h> |
||||
#include <asm/post.h> |
||||
#include <asm/processor.h> |
||||
#include <asm/fsp/fsp_support.h> |
||||
|
||||
int print_cpuinfo(void) |
||||
{ |
||||
post_code(POST_CPU_INFO); |
||||
return default_print_cpuinfo(); |
||||
} |
||||
|
||||
void reset_cpu(ulong addr) |
||||
{ |
||||
/* cold reset */ |
||||
outb(0x06, PORT_RESET); |
||||
} |
||||
|
||||
|
||||
int board_pci_post_scan(struct pci_controller *hose) |
||||
{ |
||||
u32 status; |
||||
|
||||
/* call into FspNotify */ |
||||
debug("Calling into FSP (notify phase INIT_PHASE_PCI): "); |
||||
status = fsp_notify(NULL, INIT_PHASE_PCI); |
||||
if (status != FSP_SUCCESS) |
||||
debug("fail, error code %x\n", status); |
||||
else |
||||
debug("OK\n"); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
void board_final_cleanup(void) |
||||
{ |
||||
u32 status; |
||||
|
||||
/* call into FspNotify */ |
||||
debug("Calling into FSP (notify phase INIT_PHASE_BOOT): "); |
||||
status = fsp_notify(NULL, INIT_PHASE_BOOT); |
||||
if (status != FSP_SUCCESS) |
||||
debug("fail, error code %x\n", status); |
||||
else |
||||
debug("OK\n"); |
||||
|
||||
return; |
||||
} |
||||
@ -0,0 +1,21 @@ |
||||
if TARGET_GALILEO |
||||
|
||||
config SYS_BOARD |
||||
default "galileo" |
||||
|
||||
config SYS_VENDOR |
||||
default "intel" |
||||
|
||||
config SYS_SOC |
||||
default "quark" |
||||
|
||||
config SYS_CONFIG_NAME |
||||
default "galileo" |
||||
|
||||
config BOARD_SPECIFIC_OPTIONS # dummy |
||||
def_bool y |
||||
select X86_RESET_VECTOR |
||||
select INTEL_QUARK |
||||
select BOARD_ROMSIZE_KB_1024 |
||||
|
||||
endif |
||||
@ -0,0 +1,6 @@ |
||||
INTEL GALILEO BOARD |
||||
M: Bin Meng <bmeng.cn@gmail.com> |
||||
S: Maintained |
||||
F: board/intel/galileo/ |
||||
F: include/configs/galileo.h |
||||
F: configs/galileo_defconfig |
||||
@ -0,0 +1,7 @@ |
||||
#
|
||||
# Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
obj-y += galileo.o start.o
|
||||
@ -0,0 +1,19 @@ |
||||
/*
|
||||
* Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
int board_early_init_f(void) |
||||
{ |
||||
return 0; |
||||
} |
||||
|
||||
void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio) |
||||
{ |
||||
return; |
||||
} |
||||
@ -0,0 +1,9 @@ |
||||
/* |
||||
* Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
|
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
.globl early_board_init
|
||||
early_board_init: |
||||
jmp early_board_init_ret |
||||
@ -0,0 +1,24 @@ |
||||
if TARGET_MINNOWMAX |
||||
|
||||
config SYS_BOARD |
||||
default "minnowmax" |
||||
|
||||
config SYS_VENDOR |
||||
default "intel" |
||||
|
||||
config SYS_SOC |
||||
default "baytrail" |
||||
|
||||
config SYS_CONFIG_NAME |
||||
default "minnowmax" |
||||
|
||||
config BOARD_SPECIFIC_OPTIONS # dummy |
||||
def_bool y |
||||
select X86_RESET_VECTOR |
||||
select INTEL_BAYTRAIL |
||||
select BOARD_ROMSIZE_KB_8192 |
||||
|
||||
config PCIE_ECAM_BASE |
||||
default 0xe0000000 |
||||
|
||||
endif |
||||
@ -0,0 +1,6 @@ |
||||
CircuitCo Minnowboard Max |
||||
M: Simon Glass <sjg@chromium.org> |
||||
S: Maintained |
||||
F: board/intel/minnowmax |
||||
F: include/configs/minnowmax.h |
||||
F: configs/minnowmax_defconfig |
||||
@ -0,0 +1,7 @@ |
||||
#
|
||||
# Copyright (C) 2015, Google, Inc
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
obj-y += minnowmax.o start.o
|
||||
@ -0,0 +1,32 @@ |
||||
/*
|
||||
* Copyright (C) 2015, Google, Inc |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/ibmpc.h> |
||||
#include <asm/pnp_def.h> |
||||
#include <netdev.h> |
||||
#include <smsc_lpc47m.h> |
||||
|
||||
#define SERIAL_DEV PNP_DEV(0x2e, 4) |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
int board_early_init_f(void) |
||||
{ |
||||
lpc47m_enable_serial(SERIAL_DEV, UART0_BASE); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio) |
||||
{ |
||||
return; |
||||
} |
||||
|
||||
int board_eth_init(bd_t *bis) |
||||
{ |
||||
return pci_eth_init(bis); |
||||
} |
||||
@ -0,0 +1,9 @@ |
||||
/* |
||||
* Copyright (C) 2015, Google, Inc |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
.globl early_board_init
|
||||
early_board_init: |
||||
jmp early_board_init_ret |
||||
@ -0,0 +1,6 @@ |
||||
CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xfff10000" |
||||
CONFIG_X86=y |
||||
CONFIG_TARGET_GALILEO=y |
||||
CONFIG_OF_CONTROL=y |
||||
CONFIG_OF_SEPARATE=y |
||||
CONFIG_DEFAULT_DEVICE_TREE="galileo" |
||||
@ -0,0 +1,13 @@ |
||||
CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xfff00000" |
||||
CONFIG_X86=y |
||||
CONFIG_TARGET_MINNOWMAX=y |
||||
CONFIG_OF_CONTROL=y |
||||
CONFIG_OF_SEPARATE=y |
||||
CONFIG_DEFAULT_DEVICE_TREE="minnowmax" |
||||
CONFIG_VIDEO_X86=y |
||||
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y |
||||
CONFIG_FRAMEBUFFER_VESA_MODE_11A=y |
||||
CONFIG_DEBUG_UART_NS16550=y |
||||
CONFIG_DEBUG_UART=y |
||||
CONFIG_MMCONF_BASE_ADDRESS=0xe0000000 |
||||
CONFIG_HAVE_INTEL_ME=y |
||||
@ -0,0 +1,42 @@ |
||||
/*
|
||||
* Copyright (C) 2015, Google, Inc |
||||
* Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <errno.h> |
||||
#include <malloc.h> |
||||
#include <sdhci.h> |
||||
#include <asm/pci.h> |
||||
|
||||
int pci_mmc_init(const char *name, struct pci_device_id *mmc_supported, |
||||
int num_ids) |
||||
{ |
||||
struct sdhci_host *mmc_host; |
||||
pci_dev_t devbusfn; |
||||
u32 iobase; |
||||
int ret; |
||||
int i; |
||||
|
||||
for (i = 0; i < num_ids; i++) { |
||||
devbusfn = pci_find_devices(mmc_supported, i); |
||||
if (devbusfn == -1) |
||||
return -ENODEV; |
||||
|
||||
mmc_host = malloc(sizeof(struct sdhci_host)); |
||||
if (!mmc_host) |
||||
return -ENOMEM; |
||||
|
||||
mmc_host->name = (char *)name; |
||||
pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, &iobase); |
||||
mmc_host->ioaddr = (void *)iobase; |
||||
mmc_host->quirks = 0; |
||||
ret = add_sdhci(mmc_host, 0, 0); |
||||
if (ret) |
||||
return ret; |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
@ -0,0 +1,60 @@ |
||||
/*
|
||||
* Copyright (c) 2015, Google, Inc |
||||
* Written by Simon Glass <sjg@chromium.org> |
||||
* All rights reserved. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0 |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <errno.h> |
||||
#include <pci.h> |
||||
#include <usb.h> |
||||
|
||||
#include "xhci.h" |
||||
|
||||
/*
|
||||
* Create the appropriate control structures to manage a new XHCI host |
||||
* controller. |
||||
*/ |
||||
int xhci_hcd_init(int index, struct xhci_hccr **ret_hccr, |
||||
struct xhci_hcor **ret_hcor) |
||||
{ |
||||
struct xhci_hccr *hccr; |
||||
struct xhci_hcor *hcor; |
||||
pci_dev_t pdev; |
||||
uint32_t cmd; |
||||
int len; |
||||
|
||||
pdev = pci_find_class(PCI_CLASS_SERIAL_USB_XHCI, index); |
||||
if (pdev < 0) { |
||||
printf("XHCI host controller not found\n"); |
||||
return -1; |
||||
} |
||||
|
||||
hccr = (struct xhci_hccr *)pci_map_bar(pdev, |
||||
PCI_BASE_ADDRESS_0, PCI_REGION_MEM); |
||||
len = HC_LENGTH(xhci_readl(&hccr->cr_capbase)); |
||||
hcor = (struct xhci_hcor *)((uint32_t)hccr + len); |
||||
|
||||
debug("XHCI-PCI init hccr 0x%x and hcor 0x%x hc_length %d\n", |
||||
(uint32_t)hccr, (uint32_t)hcor, len); |
||||
|
||||
*ret_hccr = hccr; |
||||
*ret_hcor = hcor; |
||||
|
||||
/* enable busmaster */ |
||||
pci_read_config_dword(pdev, PCI_COMMAND, &cmd); |
||||
cmd |= PCI_COMMAND_MASTER; |
||||
pci_write_config_dword(pdev, PCI_COMMAND, cmd); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
/*
|
||||
* Destroy the appropriate control structures corresponding * to the XHCI host |
||||
* controller |
||||
*/ |
||||
void xhci_hcd_stop(int index) |
||||
{ |
||||
} |
||||
@ -0,0 +1,60 @@ |
||||
/*
|
||||
* Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
/*
|
||||
* board/config.h - configuration options, board specific |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
#include <configs/x86-common.h> |
||||
|
||||
#define CONFIG_SYS_MONITOR_LEN (1 << 20) |
||||
#define CONFIG_BOARD_EARLY_INIT_F |
||||
|
||||
#define CONFIG_NR_DRAM_BANKS 1 |
||||
|
||||
#define CONFIG_X86_SERIAL |
||||
|
||||
/* ns16550 UART is memory-mapped in Quark SoC */ |
||||
#undef CONFIG_SYS_NS16550_PORT_MAPPED |
||||
|
||||
#define CONFIG_PCI_MEM_BUS 0x90000000 |
||||
#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS |
||||
#define CONFIG_PCI_MEM_SIZE 0x20000000 |
||||
|
||||
#define CONFIG_PCI_PREF_BUS 0xb0000000 |
||||
#define CONFIG_PCI_PREF_PHYS CONFIG_PCI_PREF_BUS |
||||
#define CONFIG_PCI_PREF_SIZE 0x20000000 |
||||
|
||||
#define CONFIG_PCI_IO_BUS 0x2000 |
||||
#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS |
||||
#define CONFIG_PCI_IO_SIZE 0xe000 |
||||
|
||||
#define CONFIG_SYS_EARLY_PCI_INIT |
||||
#define CONFIG_PCI_PNP |
||||
|
||||
#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial\0" \ |
||||
"stdout=serial\0" \
|
||||
"stderr=serial\0" |
||||
|
||||
/* SATA is not supported in Quark SoC */ |
||||
#undef CONFIG_SCSI_AHCI |
||||
#undef CONFIG_CMD_SCSI |
||||
|
||||
/* Video is not supported in Quark SoC */ |
||||
#undef CONFIG_VIDEO |
||||
#undef CONFIG_CFB_CONSOLE |
||||
|
||||
/* SD/MMC support */ |
||||
#define CONFIG_MMC |
||||
#define CONFIG_SDHCI |
||||
#define CONFIG_GENERIC_MMC |
||||
#define CONFIG_MMC_SDMA |
||||
#define CONFIG_CMD_MMC |
||||
|
||||
#endif /* __CONFIG_H */ |
||||
@ -0,0 +1,72 @@ |
||||
/*
|
||||
* Copyright (C) 2015 Google, Inc |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
/*
|
||||
* board/config.h - configuration options, board specific |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
#include <configs/x86-common.h> |
||||
|
||||
#define CONFIG_SYS_MONITOR_LEN (1 << 20) |
||||
#define CONFIG_BOARD_EARLY_INIT_F |
||||
|
||||
#define CONFIG_NR_DRAM_BANKS 1 |
||||
|
||||
#define CONFIG_X86_SERIAL |
||||
#define CONFIG_SMSC_LPC47M |
||||
|
||||
#define CONFIG_PCI_MEM_BUS 0xd0000000 |
||||
#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS |
||||
#define CONFIG_PCI_MEM_SIZE 0x10000000 |
||||
|
||||
#define CONFIG_PCI_PREF_BUS 0xc0000000 |
||||
#define CONFIG_PCI_PREF_PHYS CONFIG_PCI_PREF_BUS |
||||
#define CONFIG_PCI_PREF_SIZE 0x10000000 |
||||
|
||||
#define CONFIG_PCI_IO_BUS 0x2000 |
||||
#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS |
||||
#define CONFIG_PCI_IO_SIZE 0xe000 |
||||
|
||||
#define CONFIG_SYS_EARLY_PCI_INIT |
||||
#define CONFIG_PCI_PNP |
||||
#define CONFIG_RTL8169 |
||||
#define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,vga,serial\0" \ |
||||
"stdout=vga,serial\0" \
|
||||
"stderr=vga,serial\0" |
||||
|
||||
#define CONFIG_SCSI_DEV_LIST \ |
||||
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA} |
||||
#define CONFIG_SPI_FLASH_SST |
||||
|
||||
#define CONFIG_MMC |
||||
#define CONFIG_SDHCI |
||||
#define CONFIG_GENERIC_MMC |
||||
#define CONFIG_MMC_SDMA |
||||
#define CONFIG_CMD_MMC |
||||
|
||||
#undef CONFIG_USB_MAX_CONTROLLER_COUNT |
||||
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 |
||||
|
||||
#define CONFIG_X86_OPTION_ROM_FILE vga.bin |
||||
#define CONFIG_X86_OPTION_ROM_ADDR 0xfff90000 |
||||
|
||||
#ifndef CONFIG_SYS_COREBOOT |
||||
#define CONFIG_VIDEO_VESA |
||||
#endif |
||||
#define VIDEO_IO_OFFSET 0 |
||||
#define CONFIG_X86EMU_RAW_IO |
||||
#define CONFIG_VGA_AS_SINGLE_DEVICE |
||||
|
||||
#define CONFIG_FIT_SIGNATURE |
||||
#define CONFIG_RSA |
||||
|
||||
/* Avoid a warning in the Realtek Ethernet driver */ |
||||
#define CONFIG_SYS_CACHELINE_SIZE 16 |
||||
|
||||
#endif /* __CONFIG_H */ |
||||
@ -0,0 +1,83 @@ |
||||
/*
|
||||
* Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
* |
||||
* Intel Quark MRC bindings include several properties |
||||
* as part of an Intel Quark MRC node. In most cases, |
||||
* the value of these properties uses the standard values |
||||
* defined in this header. |
||||
*/ |
||||
|
||||
#ifndef _DT_BINDINGS_QRK_MRC_H_ |
||||
#define _DT_BINDINGS_QRK_MRC_H_ |
||||
|
||||
/* MRC platform data flags */ |
||||
#define MRC_FLAG_ECC_EN 0x00000001 |
||||
#define MRC_FLAG_SCRAMBLE_EN 0x00000002 |
||||
#define MRC_FLAG_MEMTEST_EN 0x00000004 |
||||
/* 0b DDR "fly-by" topology else 1b DDR "tree" topology */ |
||||
#define MRC_FLAG_TOP_TREE_EN 0x00000008 |
||||
/* If set ODR signal is asserted to DRAM devices on writes */ |
||||
#define MRC_FLAG_WR_ODT_EN 0x00000010 |
||||
|
||||
/* DRAM width */ |
||||
#define DRAM_WIDTH_X8 0 |
||||
#define DRAM_WIDTH_X16 1 |
||||
#define DRAM_WIDTH_X32 2 |
||||
|
||||
/* DRAM speed */ |
||||
#define DRAM_FREQ_800 0 |
||||
#define DRAM_FREQ_1066 1 |
||||
|
||||
/* DRAM type */ |
||||
#define DRAM_TYPE_DDR3 0 |
||||
#define DRAM_TYPE_DDR3L 1 |
||||
|
||||
/* DRAM rank mask */ |
||||
#define DRAM_RANK(n) (1 << (n)) |
||||
|
||||
/* DRAM channel mask */ |
||||
#define DRAM_CHANNEL(n) (1 << (n)) |
||||
|
||||
/* DRAM channel width */ |
||||
#define DRAM_CHANNEL_WIDTH_X8 0 |
||||
#define DRAM_CHANNEL_WIDTH_X16 1 |
||||
#define DRAM_CHANNEL_WIDTH_X32 2 |
||||
|
||||
/* DRAM address mode */ |
||||
#define DRAM_ADDR_MODE0 0 |
||||
#define DRAM_ADDR_MODE1 1 |
||||
#define DRAM_ADDR_MODE2 2 |
||||
|
||||
/* DRAM refresh rate */ |
||||
#define DRAM_REFRESH_RATE_195US 1 |
||||
#define DRAM_REFRESH_RATE_39US 2 |
||||
#define DRAM_REFRESH_RATE_785US 3 |
||||
|
||||
/* DRAM SR temprature range */ |
||||
#define DRAM_SRT_RANGE_NORMAL 0 |
||||
#define DRAM_SRT_RANGE_EXTENDED 1 |
||||
|
||||
/* DRAM ron value */ |
||||
#define DRAM_RON_34OHM 0 |
||||
#define DRAM_RON_40OHM 1 |
||||
|
||||
/* DRAM rtt nom value */ |
||||
#define DRAM_RTT_NOM_40OHM 0 |
||||
#define DRAM_RTT_NOM_60OHM 1 |
||||
#define DRAM_RTT_NOM_120OHM 2 |
||||
|
||||
/* DRAM rd odt value */ |
||||
#define DRAM_RD_ODT_OFF 0 |
||||
#define DRAM_RD_ODT_60OHM 1 |
||||
#define DRAM_RD_ODT_120OHM 2 |
||||
#define DRAM_RD_ODT_180OHM 3 |
||||
|
||||
/* DRAM density */ |
||||
#define DRAM_DENSITY_512M 0 |
||||
#define DRAM_DENSITY_1G 1 |
||||
#define DRAM_DENSITY_2G 2 |
||||
#define DRAM_DENSITY_4G 3 |
||||
|
||||
#endif /* _DT_BINDINGS_QRK_MRC_H_ */ |
||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in new issue