sunxi: H3: Add support for the host usb-phys

Add support for phy 1-3.

Signed-off-by: Jelle van der Waa <jelle@vdwaa.nl>
[hdegoede@redhat.com: use setclrbits_le32 instead of read-modify-write]
Signed-off-by: Hans de Goede <hdegoede@redhat.com>

arch/arm/cpu/armv7/sunxi/usb_phy.c

@@ -31,6 +31,9 @@
 #define SUNXI_EHCI_AHB_INCRX_ALIGN_EN	(1 << 8)
 #define SUNXI_EHCI_ULPI_BYPASS_EN	(1 << 0)
 
+#define REG_PHY_UNK_H3			0x420
+#define REG_PMU_UNK_H3			0x810
+
 static struct sunxi_usb_phy {
 	int usb_rst_mask;
 	int gpio_vbus;
@@ -39,19 +42,30 @@ static struct sunxi_usb_phy {
 	int id;
 	int init_count;
 	int power_on_count;
+	int base;
 } sunxi_usb_phy[] = {
 	{
 		.usb_rst_mask = CCM_USB_CTRL_PHY0_RST | CCM_USB_CTRL_PHY0_CLK,
 		.id = 0,
+		.base = SUNXI_USB0_BASE,
 	},
 	{
 		.usb_rst_mask = CCM_USB_CTRL_PHY1_RST | CCM_USB_CTRL_PHY1_CLK,
 		.id = 1,
+		.base = SUNXI_USB1_BASE,
 	},
 #if CONFIG_SUNXI_USB_PHYS >= 3
 	{
 		.usb_rst_mask = CCM_USB_CTRL_PHY2_RST | CCM_USB_CTRL_PHY2_CLK,
 		.id = 2,
+		.base = SUNXI_USB2_BASE,
+	},
+#endif
+#if CONFIG_SUNXI_USB_PHYS >= 4
+	{
+		.usb_rst_mask = CCM_USB_CTRL_PHY3_RST | CCM_USB_CTRL_PHY3_CLK,
+		.id = 3,
+		.base = SUNXI_USB3_BASE,
 	}
 #endif
 };
@@ -114,6 +128,15 @@ static void usb_phy_write(struct sunxi_usb_phy *phy, int addr,
 	}
 }
 
+#if defined CONFIG_MACH_SUN8I_H3
+static void sunxi_usb_phy_config(struct sunxi_usb_phy *phy)
+{
+	if (phy->id == 0)
+		clrbits_le32(SUNXI_USBPHY_BASE + REG_PHY_UNK_H3, 0x01);
+
+	clrbits_le32(phy->base + REG_PMU_UNK_H3, 0x02);
+}
+#else
 static void sunxi_usb_phy_config(struct sunxi_usb_phy *phy)
 {
 	/* The following comments are machine
@@ -136,16 +159,14 @@ static void sunxi_usb_phy_config(struct sunxi_usb_phy *phy)
 
 	return;
 }
+#endif
 
-static void sunxi_usb_phy_passby(int index, int enable)
+static void sunxi_usb_phy_passby(struct sunxi_usb_phy *phy, int enable)
 {
 	unsigned long bits = 0;
 	void *addr;
 
-	if (index == 1)
-		addr = (void *)SUNXI_USB1_BASE + SUNXI_USB_PMU_IRQ_ENABLE;
-	else
-		addr = (void *)SUNXI_USB2_BASE + SUNXI_USB_PMU_IRQ_ENABLE;
+	addr = (void *)phy->base + SUNXI_USB_PMU_IRQ_ENABLE;
 
 	bits = SUNXI_EHCI_AHB_ICHR8_EN |
 		SUNXI_EHCI_AHB_INCR4_BURST_EN |
@@ -181,7 +202,7 @@ void sunxi_usb_phy_init(int index)
 	sunxi_usb_phy_config(phy);
 
 	if (phy->id != 0)
-		sunxi_usb_phy_passby(index, SUNXI_USB_PASSBY_EN);
+		sunxi_usb_phy_passby(phy, SUNXI_USB_PASSBY_EN);
 }
 
 void sunxi_usb_phy_exit(int index)
@@ -194,7 +215,7 @@ void sunxi_usb_phy_exit(int index)
 		return;
 
 	if (phy->id != 0)
-		sunxi_usb_phy_passby(index, !SUNXI_USB_PASSBY_EN);
+		sunxi_usb_phy_passby(phy, !SUNXI_USB_PASSBY_EN);
 
 	clrbits_le32(&ccm->usb_clk_cfg, phy->usb_rst_mask);
 }

arch/arm/include/asm/arch-sunxi/clock_sun6i.h

@@ -229,8 +229,18 @@ struct sunxi_ccm_reg {
 /* ahb_gate0 offsets */
 #define AHB_GATE_OFFSET_USB_OHCI1	30
 #define AHB_GATE_OFFSET_USB_OHCI0	29
+#ifdef CONFIG_MACH_SUN8I_H3
+/*
+ * These are EHCI1 - EHCI3 in the datasheet (EHCI0 is for the OTG) we call
+ * them 0 - 2 like they were called on older SoCs.
+ */
+#define AHB_GATE_OFFSET_USB_EHCI2	27
+#define AHB_GATE_OFFSET_USB_EHCI1	26
+#define AHB_GATE_OFFSET_USB_EHCI0	25
+#else
 #define AHB_GATE_OFFSET_USB_EHCI1	27
 #define AHB_GATE_OFFSET_USB_EHCI0	26
+#endif
 #define AHB_GATE_OFFSET_USB0		24
 #define AHB_GATE_OFFSET_MCTL		14
 #define AHB_GATE_OFFSET_GMAC		17
@@ -263,13 +273,25 @@ struct sunxi_ccm_reg {
 #define CCM_USB_CTRL_PHY0_RST (0x1 << 0)
 #define CCM_USB_CTRL_PHY1_RST (0x1 << 1)
 #define CCM_USB_CTRL_PHY2_RST (0x1 << 2)
+#define CCM_USB_CTRL_PHY3_RST (0x1 << 3)
 /* There is no global phy clk gate on sun6i, define as 0 */
 #define CCM_USB_CTRL_PHYGATE 0
 #define CCM_USB_CTRL_PHY0_CLK (0x1 << 8)
 #define CCM_USB_CTRL_PHY1_CLK (0x1 << 9)
 #define CCM_USB_CTRL_PHY2_CLK (0x1 << 10)
+#define CCM_USB_CTRL_PHY3_CLK (0x1 << 11)
+#ifdef CONFIG_MACH_SUN8I_H3
+/*
+ * These are OHCI1 - OHCI3 in the datasheet (OHCI0 is for the OTG) we call
+ * them 0 - 2 like they were called on older SoCs.
+ */
+#define CCM_USB_CTRL_OHCI0_CLK (0x1 << 17)
+#define CCM_USB_CTRL_OHCI1_CLK (0x1 << 18)
+#define CCM_USB_CTRL_OHCI2_CLK (0x1 << 19)
+#else
 #define CCM_USB_CTRL_OHCI0_CLK (0x1 << 16)
 #define CCM_USB_CTRL_OHCI1_CLK (0x1 << 17)
+#endif
 
 #define CCM_GMAC_CTRL_TX_CLK_SRC_MII	0x0
 #define CCM_GMAC_CTRL_TX_CLK_SRC_EXT_RGMII 0x1

arch/arm/include/asm/arch-sunxi/cpu_sun4i.h

@@ -52,10 +52,18 @@
 #define SUNXI_USB2_BASE			0x01c1c000
 #endif
 #ifdef CONFIG_SUNXI_GEN_SUN6I
+#ifdef CONFIG_MACH_SUN8I_H3
+#define SUNXI_USBPHY_BASE		0x01c19000
+#define SUNXI_USB0_BASE			0x01c1a000
+#define SUNXI_USB1_BASE			0x01c1b000
+#define SUNXI_USB2_BASE			0x01c1c000
+#define SUNXI_USB3_BASE			0x01c1d000
+#else
 #define SUNXI_USB0_BASE			0x01c19000
 #define SUNXI_USB1_BASE			0x01c1a000
 #define SUNXI_USB2_BASE			0x01c1b000
 #endif
+#endif
 #define SUNXI_CSI1_BASE			0x01c1d000
 #define SUNXI_TZASC_BASE		0x01c1e000
 #define SUNXI_SPI3_BASE			0x01c1f000

configs/orangepi_pc_defconfig

@@ -13,3 +13,4 @@ CONFIG_SPL=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 CONFIG_SY8106A_POWER=y
+CONFIG_USB_EHCI_HCD=y

configs/orangepi_plus_defconfig

@@ -13,3 +13,4 @@ CONFIG_SPL=y
 # CONFIG_CMD_FPGA is not set
 CONFIG_CMD_GPIO=y
 CONFIG_SY8106A_POWER=y
+CONFIG_USB_EHCI_HCD=y

drivers/usb/host/ehci-sunxi.c

@@ -35,13 +35,12 @@ static int ehci_usb_probe(struct udevice *dev)
 	 * This should go away once we've moved to the driver model for
 	 * clocks resp. phys.
 	 */
-	if (hccr == (void *)SUNXI_USB1_BASE) {
-		priv->ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_EHCI0;
-		priv->phy_index = 1;
-	} else {
-		priv->ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_EHCI1;
-		priv->phy_index = 2;
-	}
+	priv->ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_EHCI0;
+#ifdef CONFIG_MACH_SUN8I_H3
+	priv->ahb_gate_mask |= 1 << AHB_GATE_OFFSET_USB_OHCI0;
+#endif
+	priv->phy_index = ((u32)hccr - SUNXI_USB1_BASE) / 0x1000 + 1;
+	priv->ahb_gate_mask <<= priv->phy_index - 1;
 
 	setbits_le32(&ccm->ahb_gate0, priv->ahb_gate_mask);
 #ifdef CONFIG_SUNXI_GEN_SUN6I
@@ -83,6 +82,7 @@ static const struct udevice_id ehci_usb_ids[] = {
 	{ .compatible = "allwinner,sun6i-a31-ehci", },
 	{ .compatible = "allwinner,sun7i-a20-ehci", },
 	{ .compatible = "allwinner,sun8i-a23-ehci", },
+	{ .compatible = "allwinner,sun8i-h3-ehci",  },
 	{ .compatible = "allwinner,sun9i-a80-ehci", },
 	{ }
 };

drivers/usb/host/ohci-sunxi.c

@@ -37,15 +37,14 @@ static int ohci_usb_probe(struct udevice *dev)
 	 * This should go away once we've moved to the driver model for
 	 * clocks resp. phys.
 	 */
-	if (regs == (void *)(SUNXI_USB1_BASE + 0x400)) {
-		priv->ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_OHCI0;
-		priv->usb_gate_mask = CCM_USB_CTRL_OHCI0_CLK;
-		priv->phy_index = 1;
-	} else {
-		priv->ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_OHCI1;
-		priv->usb_gate_mask = CCM_USB_CTRL_OHCI1_CLK;
-		priv->phy_index = 2;
-	}
+	priv->ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_OHCI0;
+#ifdef CONFIG_MACH_SUN8I_H3
+	priv->ahb_gate_mask |= 1 << AHB_GATE_OFFSET_USB_EHCI0;
+#endif
+	priv->usb_gate_mask = CCM_USB_CTRL_OHCI0_CLK;
+	priv->phy_index = ((u32)regs - (SUNXI_USB1_BASE + 0x400)) / 0x1000 + 1;
+	priv->ahb_gate_mask <<= priv->phy_index - 1;
+	priv->usb_gate_mask <<= priv->phy_index - 1;
 
 	setbits_le32(&ccm->ahb_gate0, priv->ahb_gate_mask);
 	setbits_le32(&ccm->usb_clk_cfg, priv->usb_gate_mask);
@@ -86,6 +85,7 @@ static const struct udevice_id ohci_usb_ids[] = {
 	{ .compatible = "allwinner,sun6i-a31-ohci", },
 	{ .compatible = "allwinner,sun7i-a20-ohci", },
 	{ .compatible = "allwinner,sun8i-a23-ohci", },
+	{ .compatible = "allwinner,sun8i-h3-ohci",  },
 	{ .compatible = "allwinner,sun9i-a80-ohci", },
 	{ }
 };

include/configs/sun8i.h

@@ -18,7 +18,11 @@
 #define CONFIG_USB_MAX_CONTROLLER_COUNT	1
 #endif
 
-#define CONFIG_SUNXI_USB_PHYS	2
+#ifdef CONFIG_MACH_SUN8I_H3
+	#define CONFIG_SUNXI_USB_PHYS	4
+#else
+	#define CONFIG_SUNXI_USB_PHYS	2
+#endif
 
 
 #ifndef CONFIG_MACH_SUN8I_A83T