Add support for Atmel AT91RM9200DK w/NAND * Patches by Robert Schwebel, 19 Mar 2003: - use arm-linux-gcc as default compiler for ARM - fix i2c fixup code - fix missing baudrate setting - added $loadaddr / CFG_LOAD_ADDR support to loadb - moved "ignoring trailing characters" _before_ u-boot wants to print out diagnostics messages; removes bogus characters at the end of transmission * Patch by John Zhan, 18 Mar 2003: Add support for SinoVee Microsystems SC8xx boards * Patch by Rolf Offermanns, 21 Mar 2003: ported the dnp1110 related changes from the current armboot cvs to current u-boot cvs. smc91111 does not work. problem marked in smc91111.c, grep for "FIXME". * Patch by Brian Auld, 25 Mar 2003: Add support for STM flash chips on ebony board * Add PCI support for MPC8250 Boards (PM825 module) * Patch by Stefan Roese, 25 Mar 2003:master
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#
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# (C) Copyright 2003
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk |
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LIB = lib$(BOARD).a
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OBJS := at91rm9200dk.o flash.o
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SOBJS :=
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$(LIB): $(OBJS) $(SOBJS) |
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$(AR) crv $@ $^
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clean: |
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rm -f $(SOBJS) $(OBJS)
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distclean: clean |
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rm -f $(LIB) core *.bak .depend
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#########################################################################
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.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) |
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$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
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-include .depend |
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#########################################################################
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@ -0,0 +1,105 @@ |
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/*
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* (C) Copyright 2002 |
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
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* Marius Groeger <mgroeger@sysgo.de> |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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#include <AT91RM9200.h> |
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/* ------------------------------------------------------------------------- */ |
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/*
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* Miscelaneous platform dependent initialisations |
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*/ |
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int board_init(void) |
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{ |
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DECLARE_GLOBAL_DATA_PTR; |
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/* memory and cpu-speed are setup before relocation */ |
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/* so we do _nothing_ here */ |
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/* arch number of AT91RM9200DK-Board */ |
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gd->bd->bi_arch_number = 251; |
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/* adress of boot parameters */ |
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gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; |
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return 0; |
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} |
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int dram_init(void) |
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{ |
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DECLARE_GLOBAL_DATA_PTR; |
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gd->bd->bi_dram[0].start = PHYS_SDRAM; |
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gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; |
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return 0; |
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} |
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|
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/*
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* Disk On Chip (NAND) Millenium initialization. |
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* The NAND lives in the CS2* space |
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*/ |
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#if (CONFIG_COMMANDS & CFG_CMD_NAND) |
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extern void |
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nand_probe(ulong physadr); |
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#define AT91_SMARTMEDIA_BASE 0x40000000 /* physical address to access memory on NCS3 */ |
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void |
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nand_init(void) |
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{ |
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/* Setup Smart Media, fitst enable the address range of CS3 */ |
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*AT91C_EBI_CSA |= AT91C_EBI_CS3A_SMC_SmartMedia; |
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/* set the bus interface characteristics based on
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tDS Data Set up Time 30 - ns |
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tDH Data Hold Time 20 - ns |
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tALS ALE Set up Time 20 - ns |
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16ns at 60 MHz ~= 3 */ |
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/*memory mapping structures */ |
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#define SM_ID_RWH (5 << 28) |
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#define SM_RWH (1 << 28) |
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#define SM_RWS (0 << 24) |
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#define SM_TDF (1 << 8) |
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#define SM_NWS (3) |
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AT91C_BASE_SMC2->SMC2_CSR[3] = ( SM_RWH|SM_RWS | AT91C_SMC2_ACSS_STANDARD | |
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AT91C_SMC2_DBW_8 | SM_TDF | |
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AT91C_SMC2_WSEN | SM_NWS); |
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/* enable the SMOE line PC0=SMCE, A21=CLE, A22=ALE */ |
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*AT91C_PIOC_ASR = AT91C_PC0_BFCK | AT91C_PC1_BFRDY_SMOE | AT91C_PC3_BFBAA_SMWE; |
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*AT91C_PIOC_PDR = AT91C_PC0_BFCK | AT91C_PC1_BFRDY_SMOE | AT91C_PC3_BFBAA_SMWE; |
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/* Configure PC2 as input (signal READY of the SmartMedia) */ |
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*AT91C_PIOC_PER = AT91C_PC2_BFAVD; /* enable direct output enable */ |
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*AT91C_PIOC_ODR = AT91C_PC2_BFAVD; /* disable output */ |
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/* Configure PB1 as input (signal Card Detect of the SmartMedia) */ |
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*AT91C_PIOB_PER = AT91C_PIO_PB1; /* enable direct output enable */ |
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*AT91C_PIOB_ODR = AT91C_PIO_PB1; /* disable output */ |
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if (*AT91C_PIOB_PDSR & AT91C_PIO_PB1) |
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printf ("No "); |
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printf ("SmartMedia card inserted\n"); |
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printf("Probing at 0x%.8x\n", AT91_SMARTMEDIA_BASE); |
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nand_probe(AT91_SMARTMEDIA_BASE); |
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} |
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#endif |
@ -0,0 +1,2 @@ |
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TEXT_BASE = 0x21fa0000
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@ -0,0 +1,397 @@ |
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/*
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* (C) Copyright 2002 |
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* Lineo, Inc. <www.lineo.com> |
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* Bernhard Kuhn <bkuhn@lineo.com> |
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* |
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* (C) Copyright 2002 |
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
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* Alex Zuepke <azu@sysgo.de> |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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ulong myflush(void); |
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#define FLASH_BANK_SIZE 0x200000 /* 2 MB */ |
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#define MAIN_SECT_SIZE 0x10000 /* 64 KB */ |
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flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; |
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#define CMD_READ_ARRAY 0x00F0 |
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#define CMD_UNLOCK1 0x00AA |
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#define CMD_UNLOCK2 0x0055 |
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#define CMD_ERASE_SETUP 0x0080 |
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#define CMD_ERASE_CONFIRM 0x0030 |
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#define CMD_PROGRAM 0x00A0 |
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#define CMD_UNLOCK_BYPASS 0x0020 |
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#define MEM_FLASH_ADDR1 (*(volatile u16 *)(CFG_FLASH_BASE + (0x00005555<<1))) |
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#define MEM_FLASH_ADDR2 (*(volatile u16 *)(CFG_FLASH_BASE + (0x00002AAA<<1))) |
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#define BIT_ERASE_DONE 0x0080 |
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#define BIT_RDY_MASK 0x0080 |
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#define BIT_PROGRAM_ERROR 0x0020 |
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#define BIT_TIMEOUT 0x80000000 /* our flag */ |
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#define READY 1 |
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#define ERR 2 |
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#define TMO 4 |
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/*-----------------------------------------------------------------------
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*/ |
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ulong flash_init(void) |
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{ |
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int i, j; |
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ulong size = 0; |
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for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) |
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{ |
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ulong flashbase = 0; |
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flash_info[i].flash_id = |
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(ATM_MANUFACT & FLASH_VENDMASK) | |
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(ATM_ID_BV1614 & FLASH_TYPEMASK); |
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flash_info[i].size = FLASH_BANK_SIZE; |
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flash_info[i].sector_count = CFG_MAX_FLASH_SECT; |
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memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT); |
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if (i == 0) |
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flashbase = PHYS_FLASH_1; |
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else |
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panic("configured to many flash banks!\n"); |
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for (j = 0; j < flash_info[i].sector_count; j++) |
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{ |
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if (j <= 9) |
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{ |
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/* 1st to 8th are 8 KB */ |
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if (j <= 7) |
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{ |
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flash_info[i].start[j] = flashbase + j*0x2000; |
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} |
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/* 9th and 10th are both 32 KB */ |
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if ((j == 8) || (j == 9)) |
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{ |
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flash_info[i].start[j] = flashbase + 0x10000 + (j-8)*0x8000; |
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} |
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} |
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else |
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{ |
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flash_info[i].start[j] = flashbase + (j-8)*MAIN_SECT_SIZE; |
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} |
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} |
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size += flash_info[i].size; |
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} |
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flash_protect(FLAG_PROTECT_SET, |
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CFG_FLASH_BASE, |
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CFG_ENV_ADDR - 1, |
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&flash_info[0]); |
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flash_protect(FLAG_PROTECT_SET, |
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CFG_ENV_ADDR, |
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CFG_ENV_ADDR + CFG_ENV_SIZE - 1, |
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&flash_info[0]); |
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return size; |
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} |
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/*-----------------------------------------------------------------------
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*/ |
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void flash_print_info (flash_info_t *info) |
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{ |
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int i; |
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switch (info->flash_id & FLASH_VENDMASK) |
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{ |
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case (ATM_MANUFACT & FLASH_VENDMASK): |
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printf("Atmel: "); |
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break; |
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default: |
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printf("Unknown Vendor "); |
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break; |
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} |
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switch (info->flash_id & FLASH_TYPEMASK) |
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{ |
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case (ATM_ID_BV1614 & FLASH_TYPEMASK): |
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printf("AT49BV1614 (16Mbit)\n"); |
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break; |
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default: |
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printf("Unknown Chip Type\n"); |
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goto Done; |
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break; |
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} |
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printf(" Size: %ld MB in %d Sectors\n", |
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info->size >> 20, info->sector_count); |
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printf(" Sector Start Addresses:"); |
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for (i = 0; i < info->sector_count; i++) |
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{ |
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if ((i % 5) == 0) |
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{ |
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printf ("\n "); |
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} |
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printf (" %08lX%s", info->start[i], |
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info->protect[i] ? " (RO)" : " "); |
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} |
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printf ("\n"); |
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Done: |
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} |
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/*-----------------------------------------------------------------------
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*/ |
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int flash_erase (flash_info_t *info, int s_first, int s_last) |
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{ |
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ulong result; |
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int iflag, cflag, prot, sect; |
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int rc = ERR_OK; |
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int chip1; |
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/* first look for protection bits */ |
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if (info->flash_id == FLASH_UNKNOWN) |
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return ERR_UNKNOWN_FLASH_TYPE; |
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if ((s_first < 0) || (s_first > s_last)) { |
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return ERR_INVAL; |
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} |
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if ((info->flash_id & FLASH_VENDMASK) != |
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(ATM_MANUFACT & FLASH_VENDMASK)) { |
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return ERR_UNKNOWN_FLASH_VENDOR; |
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} |
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prot = 0; |
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for (sect=s_first; sect<=s_last; ++sect) { |
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if (info->protect[sect]) { |
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prot++; |
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} |
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} |
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if (prot) |
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return ERR_PROTECTED; |
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|
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/*
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* Disable interrupts which might cause a timeout |
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* here. Remember that our exception vectors are |
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* at address 0 in the flash, and we don't want a |
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* (ticker) exception to happen while the flash |
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* chip is in programming mode. |
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*/ |
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cflag = icache_status(); |
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icache_disable(); |
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iflag = disable_interrupts(); |
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|
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/* Start erase on unprotected sectors */ |
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for (sect = s_first; sect<=s_last && !ctrlc(); sect++) |
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{ |
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printf("Erasing sector %2d ... ", sect); |
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/* arm simple, non interrupt dependent timer */ |
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reset_timer_masked(); |
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if (info->protect[sect] == 0) |
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{ /* not protected */ |
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volatile u16 *addr = (volatile u16 *)(info->start[sect]); |
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MEM_FLASH_ADDR1 = CMD_UNLOCK1; |
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MEM_FLASH_ADDR2 = CMD_UNLOCK2; |
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MEM_FLASH_ADDR1 = CMD_ERASE_SETUP; |
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MEM_FLASH_ADDR1 = CMD_UNLOCK1; |
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MEM_FLASH_ADDR2 = CMD_UNLOCK2; |
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*addr = CMD_ERASE_CONFIRM; |
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|
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/* wait until flash is ready */ |
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chip1 = 0; |
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do |
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{ |
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result = *addr; |
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|
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/* check timeout */ |
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if (get_timer_masked() > CFG_FLASH_ERASE_TOUT) |
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{ |
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MEM_FLASH_ADDR1 = CMD_READ_ARRAY; |
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chip1 = TMO; |
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break; |
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} |
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if (!chip1 && (result & 0xFFFF) & BIT_ERASE_DONE) |
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chip1 = READY; |
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} while (!chip1); |
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MEM_FLASH_ADDR1 = CMD_READ_ARRAY; |
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if (chip1 == ERR) |
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{ |
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rc = ERR_PROG_ERROR; |
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goto outahere; |
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} |
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if (chip1 == TMO) |
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{ |
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rc = ERR_TIMOUT; |
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goto outahere; |
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} |
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printf("ok.\n"); |
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} |
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else /* it was protected */ |
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{ |
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printf("protected!\n"); |
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} |
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} |
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if (ctrlc()) |
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printf("User Interrupt!\n"); |
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|
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outahere: |
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/* allow flash to settle - wait 10 ms */ |
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udelay_masked(10000); |
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if (iflag) |
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enable_interrupts(); |
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|
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if (cflag) |
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icache_enable(); |
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|
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return rc; |
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} |
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|
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/*-----------------------------------------------------------------------
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* Copy memory to flash |
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*/ |
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|
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volatile static int write_word (flash_info_t *info, ulong dest, ulong data) |
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{ |
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volatile u16 *addr = (volatile u16 *)dest; |
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ulong result; |
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int rc = ERR_OK; |
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int cflag, iflag; |
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int chip1; |
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|
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/*
|
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* Check if Flash is (sufficiently) erased |
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*/ |
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result = *addr; |
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if ((result & data) != data) |
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return ERR_NOT_ERASED; |
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|
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|
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/*
|
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* Disable interrupts which might cause a timeout |
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* here. Remember that our exception vectors are |
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* at address 0 in the flash, and we don't want a |
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* (ticker) exception to happen while the flash |
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* chip is in programming mode. |
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*/ |
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cflag = icache_status(); |
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icache_disable(); |
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iflag = disable_interrupts(); |
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|
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MEM_FLASH_ADDR1 = CMD_UNLOCK1; |
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MEM_FLASH_ADDR2 = CMD_UNLOCK2; |
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MEM_FLASH_ADDR1 = CMD_PROGRAM; |
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*addr = data; |
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|
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/* arm simple, non interrupt dependent timer */ |
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reset_timer_masked(); |
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|
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/* wait until flash is ready */ |
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chip1 = 0; |
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do |
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{ |
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result = *addr; |
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|
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/* check timeout */ |
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if (get_timer_masked() > CFG_FLASH_ERASE_TOUT) |
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{ |
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chip1 = ERR | TMO; |
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break; |
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} |
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if (!chip1 && ((result & 0x80) == (data & 0x80))) |
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chip1 = READY; |
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|
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} while (!chip1); |
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|
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*addr = CMD_READ_ARRAY; |
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|
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if (chip1 == ERR || *addr != data) |
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rc = ERR_PROG_ERROR; |
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|
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if (iflag) |
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enable_interrupts(); |
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|
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if (cflag) |
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icache_enable(); |
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|
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return rc; |
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} |
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|
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/*-----------------------------------------------------------------------
|
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* Copy memory to flash. |
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*/ |
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|
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int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) |
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{ |
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ulong wp, data; |
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int rc; |
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|
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if(addr & 1) { |
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printf("unaligned destination not supported\n"); |
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return ERR_ALIGN; |
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}; |
||||
|
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if((int)src & 1) { |
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printf("unaligned source not supported\n"); |
||||
return ERR_ALIGN; |
||||
}; |
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|
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wp = addr; |
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|
||||
while (cnt >= 2) { |
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data = *((volatile u16*)src); |
||||
if ((rc = write_word(info, wp, data)) != 0) { |
||||
return (rc); |
||||
} |
||||
src += 2; |
||||
wp += 2; |
||||
cnt -= 2; |
||||
} |
||||
|
||||
if(cnt == 1) { |
||||
data = (*((volatile u8*)src)) | (*((volatile u8*)(wp+1)) << 8); |
||||
if ((rc = write_word(info, wp, data)) != 0) { |
||||
return (rc); |
||||
} |
||||
src += 1; |
||||
wp += 1; |
||||
cnt -= 1; |
||||
}; |
||||
|
||||
return ERR_OK; |
||||
} |
@ -0,0 +1,54 @@ |
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/* |
||||
* (C) Copyright 2002 |
||||
* Gary Jennejohn, DENX Software Engineering, <gj@denx.de> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") |
||||
/*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/ |
||||
OUTPUT_ARCH(arm) |
||||
ENTRY(_start) |
||||
SECTIONS |
||||
{ |
||||
. = 0x00000000; |
||||
|
||||
. = ALIGN(4); |
||||
.text : |
||||
{ |
||||
cpu/at91rm9200/start.o (.text) |
||||
*(.text) |
||||
} |
||||
|
||||
. = ALIGN(4); |
||||
.rodata : { *(.rodata) } |
||||
|
||||
. = ALIGN(4); |
||||
.data : { *(.data) } |
||||
|
||||
. = ALIGN(4); |
||||
.got : { *(.got) } |
||||
|
||||
armboot_end_data = .; |
||||
|
||||
. = ALIGN(4); |
||||
.bss : { *(.bss) } |
||||
|
||||
armboot_end = .; |
||||
} |
@ -0,0 +1,40 @@ |
||||
#
|
||||
# (C) Copyright 2000
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk |
||||
|
||||
LIB = lib$(BOARD).a
|
||||
|
||||
OBJS = $(BOARD).o flash.o
|
||||
|
||||
$(LIB): .depend $(OBJS) |
||||
$(AR) crv $@ $^
|
||||
|
||||
#########################################################################
|
||||
|
||||
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) |
||||
$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
|
||||
|
||||
sinclude .depend |
||||
|
||||
#########################################################################
|
@ -0,0 +1,24 @@ |
||||
#
|
||||
# (C) Copyright 2000
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
TEXT_BASE = 0x40000000
|
@ -0,0 +1,801 @@ |
||||
/*
|
||||
* (C) Copyright 2000 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <mpc8xx.h> |
||||
|
||||
#ifndef CFG_ENV_ADDR |
||||
#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) |
||||
#endif |
||||
|
||||
flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Functions |
||||
*/ |
||||
static int write_word (flash_info_t *info, ulong dest, ulong data); |
||||
#if 0 |
||||
static ulong flash_get_size (vu_long *addr, flash_info_t *info); |
||||
static void flash_get_offsets (ulong base, flash_info_t *info); |
||||
#endif |
||||
#ifdef CONFIG_BOOT_8B |
||||
static int my_in_8( unsigned char *addr); |
||||
static void my_out_8( unsigned char *addr, int val); |
||||
#endif |
||||
#ifdef CONFIG_BOOT_16B |
||||
static int my_in_be16( unsigned short *addr); |
||||
static void my_out_be16( unsigned short *addr, int val); |
||||
#endif |
||||
#ifdef CONFIG_BOOT_32B |
||||
static unsigned my_in_be32( unsigned *addr); |
||||
static void my_out_be32( unsigned *addr, int val); |
||||
#endif |
||||
/*-----------------------------------------------------------------------
|
||||
*/ |
||||
|
||||
unsigned long flash_init (void) |
||||
{ |
||||
volatile immap_t *immap = (immap_t *)CFG_IMMR; |
||||
volatile memctl8xx_t *memctl = &immap->im_memctl; |
||||
unsigned long size_b0, size_b1; |
||||
int i; |
||||
|
||||
size_b0=0; |
||||
size_b1=0; |
||||
/* Init: no FLASHes known */ |
||||
for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) { |
||||
flash_info[i].flash_id = FLASH_UNKNOWN; |
||||
} |
||||
#ifdef CFG_DOC_BASE |
||||
#ifndef CONFIG_FEL8xx_AT |
||||
memctl->memc_or5 = (0xffff8000 | CFG_OR_TIMING_DOC ); /* 32k bytes */ |
||||
memctl->memc_br5 = CFG_DOC_BASE | 0x401; |
||||
#else |
||||
memctl->memc_or3 = (0xffff8000 | CFG_OR_TIMING_DOC ); /* 32k bytes */ |
||||
memctl->memc_br3 = CFG_DOC_BASE | 0x401; |
||||
#endif |
||||
#endif |
||||
#if defined( CONFIG_BOOT_8B) |
||||
// memctl->memc_or0 = 0xfff80ff4; /* 4MB bytes */
|
||||
// memctl->memc_br0 = 0x40000401;
|
||||
size_b0 = 0x80000; /* 512 K */ |
||||
flash_info[0].flash_id = FLASH_MAN_AMD | FLASH_AM040; |
||||
flash_info[0].sector_count = 8; |
||||
flash_info[0].size = 0x00080000; |
||||
/* set up sector start address table */ |
||||
for (i = 0; i < flash_info[0].sector_count; i++) |
||||
flash_info[0].start[i] = 0x40000000 + (i * 0x10000); |
||||
/* protect all sectors */ |
||||
for (i = 0; i < flash_info[0].sector_count; i++) |
||||
flash_info[0].protect[i] = 0x1; |
||||
#elif defined (CONFIG_BOOT_16B) |
||||
// memctl->memc_or0 = 0xfff80ff4; /* 4MB bytes */
|
||||
// memctl->memc_br0 = 0x40000401;
|
||||
size_b0 = 0x400000; /* 4MB , assume AMD29LV320B */ |
||||
flash_info[0].flash_id = FLASH_MAN_AMD | FLASH_AM320B; |
||||
flash_info[0].sector_count = 67; |
||||
flash_info[0].size = 0x00400000; |
||||
/* set up sector start address table */ |
||||
flash_info[0].start[0] = 0x40000000 ; |
||||
flash_info[0].start[1] = 0x40000000 + 0x4000; |
||||
flash_info[0].start[2] = 0x40000000 + 0x6000; |
||||
flash_info[0].start[3] = 0x40000000 + 0x8000; |
||||
for (i = 4; i < flash_info[0].sector_count; i++) |
||||
flash_info[0].start[i] = 0x40000000 + 0x10000 + ((i-4) * 0x10000); |
||||
/* protect all sectors */ |
||||
for (i = 0; i < flash_info[0].sector_count; i++) |
||||
flash_info[0].protect[i] = 0x1; |
||||
#endif |
||||
|
||||
|
||||
#ifdef CONFIG_BOOT_32B |
||||
|
||||
/* Static FLASH Bank configuration here - FIXME XXX */ |
||||
|
||||
size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]); |
||||
|
||||
if (flash_info[0].flash_id == FLASH_UNKNOWN) { |
||||
printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", |
||||
size_b0, size_b0<<20); |
||||
} |
||||
|
||||
size_b1 = flash_get_size((vu_long *)FLASH_BASE1_PRELIM, &flash_info[1]); |
||||
|
||||
if (size_b1 > size_b0) { |
||||
printf ("## ERROR: " |
||||
"Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n", |
||||
size_b1, size_b1<<20, |
||||
size_b0, size_b0<<20 |
||||
); |
||||
flash_info[0].flash_id = FLASH_UNKNOWN; |
||||
flash_info[1].flash_id = FLASH_UNKNOWN; |
||||
flash_info[0].sector_count = -1; |
||||
flash_info[1].sector_count = -1; |
||||
flash_info[0].size = 0; |
||||
flash_info[1].size = 0; |
||||
return (0); |
||||
} |
||||
|
||||
/* Remap FLASH according to real size */ |
||||
memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & OR_AM_MSK); |
||||
memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V; |
||||
|
||||
/* Re-do sizing to get full correct info */ |
||||
size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]); |
||||
|
||||
flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]); |
||||
|
||||
#if CFG_MONITOR_BASE >= CFG_FLASH_BASE |
||||
/* monitor protection ON by default */ |
||||
flash_protect(FLAG_PROTECT_SET, |
||||
CFG_MONITOR_BASE, |
||||
CFG_MONITOR_BASE+CFG_MONITOR_LEN-1, |
||||
&flash_info[0]); |
||||
#endif |
||||
|
||||
#ifdef CFG_ENV_IS_IN_FLASH |
||||
/* ENV protection ON by default */ |
||||
flash_protect(FLAG_PROTECT_SET, |
||||
CFG_ENV_ADDR, |
||||
CFG_ENV_ADDR+CFG_ENV_SIZE-1, |
||||
&flash_info[0]); |
||||
#endif |
||||
|
||||
if (size_b1) { |
||||
memctl->memc_or1 = CFG_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000); |
||||
memctl->memc_br1 = ((CFG_FLASH_BASE + size_b0) & BR_BA_MSK) | |
||||
BR_MS_GPCM | BR_V; |
||||
|
||||
/* Re-do sizing to get full correct info */ |
||||
size_b1 = flash_get_size((vu_long *)(CFG_FLASH_BASE + size_b0), |
||||
&flash_info[1]); |
||||
|
||||
flash_get_offsets (CFG_FLASH_BASE + size_b0, &flash_info[1]); |
||||
|
||||
#if CFG_MONITOR_BASE >= CFG_FLASH_BASE |
||||
/* monitor protection ON by default */ |
||||
flash_protect(FLAG_PROTECT_SET, |
||||
CFG_MONITOR_BASE, |
||||
CFG_MONITOR_BASE+CFG_MONITOR_LEN-1, |
||||
&flash_info[1]); |
||||
#endif |
||||
|
||||
#ifdef CFG_ENV_IS_IN_FLASH |
||||
/* ENV protection ON by default */ |
||||
flash_protect(FLAG_PROTECT_SET, |
||||
CFG_ENV_ADDR, |
||||
CFG_ENV_ADDR+CFG_ENV_SIZE-1, |
||||
&flash_info[1]); |
||||
#endif |
||||
} else { |
||||
memctl->memc_br1 = 0; /* invalidate bank */ |
||||
|
||||
flash_info[1].flash_id = FLASH_UNKNOWN; |
||||
flash_info[1].sector_count = -1; |
||||
} |
||||
|
||||
flash_info[0].size = size_b0; |
||||
flash_info[1].size = size_b1; |
||||
|
||||
|
||||
#endif /* CONFIG_BOOT_32B */ |
||||
|
||||
return (size_b0 + size_b1); |
||||
} |
||||
#if 0 |
||||
/*-----------------------------------------------------------------------
|
||||
*/ |
||||
static void flash_get_offsets (ulong base, flash_info_t *info) |
||||
{ |
||||
int i; |
||||
|
||||
/* set up sector start address table */ |
||||
if (info->flash_id & FLASH_BTYPE) { |
||||
/* set sector offsets for bottom boot block type */ |
||||
info->start[0] = base + 0x00000000; |
||||
info->start[1] = base + 0x00008000; |
||||
info->start[2] = base + 0x0000C000; |
||||
info->start[3] = base + 0x00010000; |
||||
for (i = 4; i < info->sector_count; i++) { |
||||
info->start[i] = base + (i * 0x00020000) - 0x00060000; |
||||
} |
||||
} else { |
||||
/* set sector offsets for top boot block type */ |
||||
i = info->sector_count - 1; |
||||
info->start[i--] = base + info->size - 0x00008000; |
||||
info->start[i--] = base + info->size - 0x0000C000; |
||||
info->start[i--] = base + info->size - 0x00010000; |
||||
for (; i >= 0; i--) { |
||||
info->start[i] = base + i * 0x00020000; |
||||
} |
||||
} |
||||
} |
||||
#endif |
||||
/*-----------------------------------------------------------------------
|
||||
*/ |
||||
void flash_print_info (flash_info_t *info) |
||||
{ |
||||
int i; |
||||
|
||||
if (info->flash_id == FLASH_UNKNOWN) { |
||||
printf ("missing or unknown FLASH type\n"); |
||||
return; |
||||
} |
||||
|
||||
switch (info->flash_id & FLASH_VENDMASK) { |
||||
case FLASH_MAN_AMD: printf ("AMD "); break; |
||||
case FLASH_MAN_FUJ: printf ("FUJITSU "); break; |
||||
default: printf ("Unknown Vendor "); break; |
||||
} |
||||
|
||||
switch (info->flash_id & FLASH_TYPEMASK) { |
||||
case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); |
||||
break; |
||||
case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n"); |
||||
break; |
||||
case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); |
||||
break; |
||||
case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n"); |
||||
break; |
||||
case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); |
||||
break; |
||||
case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n"); |
||||
break; |
||||
case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); |
||||
break; |
||||
case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n"); |
||||
break; |
||||
default: printf ("Unknown Chip Type\n"); |
||||
break; |
||||
} |
||||
|
||||
printf (" Size: %ld MB in %d Sectors\n", |
||||
info->size >> 20, info->sector_count); |
||||
|
||||
printf (" Sector Start Addresses:"); |
||||
for (i=0; i<info->sector_count; ++i) { |
||||
if ((i % 5) == 0) |
||||
printf ("\n "); |
||||
printf (" %08lX%s", |
||||
info->start[i], |
||||
info->protect[i] ? " (RO)" : " " |
||||
); |
||||
} |
||||
printf ("\n"); |
||||
return; |
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/ |
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/ |
||||
|
||||
/*
|
||||
* The following code cannot be run from FLASH! |
||||
*/ |
||||
#if 0 |
||||
static ulong flash_get_size (vu_long *addr, flash_info_t *info) |
||||
{ |
||||
short i; |
||||
ulong value; |
||||
ulong base = (ulong)addr; |
||||
|
||||
/* Write auto select command: read Manufacturer ID */ |
||||
addr[0x0555] = 0x00AA00AA; |
||||
addr[0x02AA] = 0x00550055; |
||||
addr[0x0555] = 0x00900090; |
||||
|
||||
value = addr[0]; |
||||
|
||||
switch (value) { |
||||
case AMD_MANUFACT: |
||||
info->flash_id = FLASH_MAN_AMD; |
||||
break; |
||||
case FUJ_MANUFACT: |
||||
info->flash_id = FLASH_MAN_FUJ; |
||||
break; |
||||
default: |
||||
info->flash_id = FLASH_UNKNOWN; |
||||
info->sector_count = 0; |
||||
info->size = 0; |
||||
return (0); /* no or unknown flash */ |
||||
} |
||||
|
||||
value = addr[1]; /* device ID */ |
||||
|
||||
switch (value) { |
||||
case AMD_ID_LV400T: |
||||
info->flash_id += FLASH_AM400T; |
||||
info->sector_count = 11; |
||||
info->size = 0x00100000; |
||||
break; /* => 1 MB */ |
||||
|
||||
case AMD_ID_LV400B: |
||||
info->flash_id += FLASH_AM400B; |
||||
info->sector_count = 11; |
||||
info->size = 0x00100000; |
||||
break; /* => 1 MB */ |
||||
|
||||
case AMD_ID_LV800T: |
||||
info->flash_id += FLASH_AM800T; |
||||
info->sector_count = 19; |
||||
info->size = 0x00200000; |
||||
break; /* => 2 MB */ |
||||
|
||||
case AMD_ID_LV800B: |
||||
info->flash_id += FLASH_AM800B; |
||||
info->sector_count = 19; |
||||
info->size = 0x00200000; |
||||
break; /* => 2 MB */ |
||||
|
||||
case AMD_ID_LV160T: |
||||
info->flash_id += FLASH_AM160T; |
||||
info->sector_count = 35; |
||||
info->size = 0x00400000; |
||||
break; /* => 4 MB */ |
||||
|
||||
case AMD_ID_LV160B: |
||||
info->flash_id += FLASH_AM160B; |
||||
info->sector_count = 35; |
||||
info->size = 0x00400000; |
||||
break; /* => 4 MB */ |
||||
#if 0 /* enable when device IDs are available */
|
||||
case AMD_ID_LV320T: |
||||
info->flash_id += FLASH_AM320T; |
||||
info->sector_count = 67; |
||||
info->size = 0x00800000; |
||||
break; /* => 8 MB */ |
||||
|
||||
case AMD_ID_LV320B: |
||||
info->flash_id += FLASH_AM320B; |
||||
info->sector_count = 67; |
||||
info->size = 0x00800000; |
||||
break; /* => 8 MB */ |
||||
#endif |
||||
default: |
||||
info->flash_id = FLASH_UNKNOWN; |
||||
return (0); /* => no or unknown flash */ |
||||
} |
||||
|
||||
/* set up sector start address table */ |
||||
if (info->flash_id & FLASH_BTYPE) { |
||||
/* set sector offsets for bottom boot block type */ |
||||
info->start[0] = base + 0x00000000; |
||||
info->start[1] = base + 0x00008000; |
||||
info->start[2] = base + 0x0000C000; |
||||
info->start[3] = base + 0x00010000; |
||||
for (i = 4; i < info->sector_count; i++) { |
||||
info->start[i] = base + (i * 0x00020000) - 0x00060000; |
||||
} |
||||
} else { |
||||
/* set sector offsets for top boot block type */ |
||||
i = info->sector_count - 1; |
||||
info->start[i--] = base + info->size - 0x00008000; |
||||
info->start[i--] = base + info->size - 0x0000C000; |
||||
info->start[i--] = base + info->size - 0x00010000; |
||||
for (; i >= 0; i--) { |
||||
info->start[i] = base + i * 0x00020000; |
||||
} |
||||
} |
||||
|
||||
/* check for protected sectors */ |
||||
for (i = 0; i < info->sector_count; i++) { |
||||
/* read sector protection at sector address, (A7 .. A0) = 0x02 */ |
||||
/* D0 = 1 if protected */ |
||||
addr = (volatile unsigned long *)(info->start[i]); |
||||
info->protect[i] = addr[2] & 1; |
||||
} |
||||
|
||||
/*
|
||||
* Prevent writes to uninitialized FLASH. |
||||
*/ |
||||
if (info->flash_id != FLASH_UNKNOWN) { |
||||
addr = (volatile unsigned long *)info->start[0]; |
||||
|
||||
*addr = 0x00F000F0; /* reset bank */ |
||||
} |
||||
|
||||
return (info->size); |
||||
} |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/ |
||||
|
||||
int flash_erase (flash_info_t *info, int s_first, int s_last) |
||||
{ |
||||
vu_long *addr = (vu_long*)(info->start[0]); |
||||
int flag, prot, sect, l_sect,in_mid,in_did; |
||||
ulong start, now, last; |
||||
|
||||
if ((s_first < 0) || (s_first > s_last)) { |
||||
if (info->flash_id == FLASH_UNKNOWN) { |
||||
printf ("- missing\n"); |
||||
} else { |
||||
printf ("- no sectors to erase\n"); |
||||
} |
||||
return 1; |
||||
} |
||||
|
||||
if ((info->flash_id == FLASH_UNKNOWN) || |
||||
(info->flash_id > FLASH_AMD_COMP)) { |
||||
printf ("Can't erase unknown flash type %08lx - aborted\n", |
||||
info->flash_id); |
||||
return 1; |
||||
} |
||||
|
||||
prot = 0; |
||||
for (sect=s_first; sect<=s_last; ++sect) { |
||||
if (info->protect[sect]) { |
||||
prot++; |
||||
} |
||||
} |
||||
|
||||
if (prot) { |
||||
printf ("- Warning: %d protected sectors will not be erased!\n", |
||||
prot); |
||||
} else { |
||||
printf ("\n"); |
||||
} |
||||
|
||||
l_sect = -1; |
||||
|
||||
/* Disable interrupts which might cause a timeout here */ |
||||
flag = disable_interrupts(); |
||||
#if defined (CONFIG_BOOT_8B ) |
||||
my_out_8( (unsigned char * ) ((ulong)addr+0x555) , 0xaa ); |
||||
my_out_8( (unsigned char * ) ((ulong)addr+0x2aa) , 0x55 ); |
||||
my_out_8( (unsigned char * ) ((ulong)addr+0x555) , 0x90 ); |
||||
in_mid=my_in_8( (unsigned char * ) addr ); |
||||
in_did=my_in_8( (unsigned char * ) ((ulong)addr+1) ); |
||||
printf(" man ID=0x%x, dev ID=0x%x.\n",in_mid,in_did ); |
||||
my_out_8( (unsigned char *)addr, 0xf0); |
||||
udelay(1); |
||||
my_out_8( (unsigned char *) ((ulong)addr+0x555),0xaa ); |
||||
my_out_8( (unsigned char *) ((ulong)addr+0x2aa),0x55 ); |
||||
my_out_8( (unsigned char *) ((ulong)addr+0x555),0x80 ); |
||||
my_out_8( (unsigned char *) ((ulong)addr+0x555),0xaa ); |
||||
my_out_8( (unsigned char *) ((ulong)addr+0x2aa),0x55 ); |
||||
/* Start erase on unprotected sectors */ |
||||
for (sect = s_first; sect<=s_last; sect++) { |
||||
if (info->protect[sect] == 0) { /* not protected */ |
||||
addr = (vu_long*)(info->start[sect]); |
||||
//addr[0] = 0x00300030;
|
||||
my_out_8( (unsigned char *) ((ulong)addr),0x30 ); |
||||
l_sect = sect; |
||||
} |
||||
} |
||||
#elif defined(CONFIG_BOOT_16B ) |
||||
my_out_be16( (unsigned short * ) ((ulong)addr+ (0xaaa)) , 0xaa ); |
||||
my_out_be16( (unsigned short * ) ((ulong)addr+ (0x554)) , 0x55 ); |
||||
my_out_be16( (unsigned short * ) ((ulong)addr+ (0xaaa)) , 0x90 ); |
||||
in_mid=my_in_be16( (unsigned short * ) addr ); |
||||
in_did=my_in_be16 ( (unsigned short * ) ((ulong)addr+2) ); |
||||
printf(" man ID=0x%x, dev ID=0x%x.\n",in_mid,in_did ); |
||||
my_out_be16( (unsigned short *)addr, 0xf0); |
||||
udelay(1); |
||||
my_out_be16( (unsigned short *) ((ulong)addr+ 0xaaa),0xaa ); |
||||
my_out_be16( (unsigned short *) ((ulong)addr+0x554),0x55 ); |
||||
my_out_be16( (unsigned short *) ((ulong)addr+0xaaa),0x80 ); |
||||
my_out_be16( (unsigned short *) ((ulong)addr+0xaaa),0xaa ); |
||||
my_out_be16( (unsigned short *) ((ulong)addr+0x554),0x55 ); |
||||
/* Start erase on unprotected sectors */ |
||||
for (sect = s_first; sect<=s_last; sect++) { |
||||
if (info->protect[sect] == 0) { /* not protected */ |
||||
addr = (vu_long*)(info->start[sect]); |
||||
my_out_be16( (unsigned short *) ((ulong)addr),0x30 ); |
||||
l_sect = sect; |
||||
} |
||||
} |
||||
|
||||
#elif defined(CONFIG_BOOT_32B) |
||||
my_out_be32( (unsigned * ) ((ulong)addr+0x1554) , 0xaa ); |
||||
my_out_be32( (unsigned * ) ((ulong)addr+0xaa8) , 0x55 ); |
||||
my_out_be32( (unsigned *) ((ulong)addr+0x1554) , 0x90 ); |
||||
in_mid=my_in_be32( (unsigned * ) addr ); |
||||
in_did=my_in_be32( (unsigned * ) ((ulong)addr+4) ); |
||||
printf(" man ID=0x%x, dev ID=0x%x.\n",in_mid,in_did ); |
||||
my_out_be32( (unsigned *)addr, 0xf0); |
||||
udelay(1); |
||||
my_out_be32( (unsigned *) ((ulong)addr+0x1554),0xaa ); |
||||
my_out_be32( (unsigned *) ((ulong)addr+0xaa8),0x55 ); |
||||
my_out_be32( (unsigned *) ((ulong)addr+0x1554),0x80 ); |
||||
my_out_be32( (unsigned *) ((ulong)addr+0x1554),0xaa ); |
||||
my_out_be32( (unsigned *) ((ulong)addr+0xaa8),0x55 ); |
||||
/* Start erase on unprotected sectors */ |
||||
for (sect = s_first; sect<=s_last; sect++) { |
||||
if (info->protect[sect] == 0) { /* not protected */ |
||||
addr = (vu_long*)(info->start[sect]); |
||||
my_out_be32( (unsigned *) ((ulong)addr),0x00300030 ); |
||||
l_sect = sect; |
||||
} |
||||
} |
||||
|
||||
#else |
||||
# error CONFIG_BOOT_(size)B missing. |
||||
#endif |
||||
/* re-enable interrupts if necessary */ |
||||
if (flag) |
||||
enable_interrupts(); |
||||
|
||||
/* wait at least 80us - let's wait 1 ms */ |
||||
udelay (1000); |
||||
|
||||
/*
|
||||
* We wait for the last triggered sector |
||||
*/ |
||||
if (l_sect < 0) |
||||
goto DONE; |
||||
|
||||
start = get_timer (0); |
||||
last = start; |
||||
addr = (vu_long*)(info->start[l_sect]); |
||||
#if defined (CONFIG_BOOT_8B) |
||||
while ( (my_in_8((unsigned char *)addr) & 0x80) != 0x80 )
|
||||
#elif defined(CONFIG_BOOT_16B ) |
||||
while ( (my_in_be16((unsigned short *)addr) & 0x0080) != 0x0080 )
|
||||
#elif defined(CONFIG_BOOT_32B) |
||||
while ( (my_in_be32((unsigned *)addr) & 0x00800080) != 0x00800080 )
|
||||
#else |
||||
# error CONFIG_BOOT_(size)B missing. |
||||
#endif |
||||
{ |
||||
if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { |
||||
printf ("Timeout\n"); |
||||
return 1; |
||||
} |
||||
/* show that we're waiting */ |
||||
if ((now - last) > 1000) { /* every second */ |
||||
putc ('.'); |
||||
last = now; |
||||
} |
||||
} |
||||
DONE: |
||||
/* reset to read mode */ |
||||
addr = (volatile unsigned long *)info->start[0]; |
||||
#if defined (CONFIG_BOOT_8B) |
||||
my_out_8( (unsigned char *)addr, 0xf0); |
||||
#elif defined(CONFIG_BOOT_16B ) |
||||
my_out_be16( (unsigned short * ) addr , 0x00f0 ); |
||||
#elif defined(CONFIG_BOOT_32B) |
||||
my_out_be32 ( (unsigned *)addr, 0x00F000F0 ); /* reset bank */ |
||||
#else |
||||
# error CONFIG_BOOT_(size)B missing. |
||||
#endif |
||||
printf (" done\n"); |
||||
return 0; |
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Copy memory to flash, returns: |
||||
* 0 - OK |
||||
* 1 - write timeout |
||||
* 2 - Flash not erased |
||||
*/ |
||||
|
||||
int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) |
||||
{ |
||||
ulong cp, wp, data; |
||||
int i, l, rc; |
||||
|
||||
wp = (addr & ~3); /* get lower word aligned address */ |
||||
|
||||
/*
|
||||
* handle unaligned start bytes |
||||
*/ |
||||
if ((l = addr - wp) != 0) { |
||||
data = 0; |
||||
for (i=0, cp=wp; i<l; ++i, ++cp) { |
||||
data = (data << 8) | (*(uchar *)cp); |
||||
} |
||||
for (; i<4 && cnt>0; ++i) { |
||||
data = (data << 8) | *src++; |
||||
--cnt; |
||||
++cp; |
||||
} |
||||
for (; cnt==0 && i<4; ++i, ++cp) { |
||||
data = (data << 8) | (*(uchar *)cp); |
||||
} |
||||
|
||||
if ((rc = write_word(info, wp, data)) != 0) { |
||||
return (rc); |
||||
} |
||||
wp += 4; |
||||
} |
||||
|
||||
/*
|
||||
* handle word aligned part |
||||
*/ |
||||
while (cnt >= 4) { |
||||
data = 0; |
||||
for (i=0; i<4; ++i) { |
||||
data = (data << 8) | *src++; |
||||
} |
||||
if ((rc = write_word(info, wp, data)) != 0) { |
||||
return (rc); |
||||
} |
||||
wp += 4; |
||||
cnt -= 4; |
||||
} |
||||
|
||||
if (cnt == 0) { |
||||
return (0); |
||||
} |
||||
|
||||
/*
|
||||
* handle unaligned tail bytes |
||||
*/ |
||||
data = 0; |
||||
for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { |
||||
data = (data << 8) | *src++; |
||||
--cnt; |
||||
} |
||||
for (; i<4; ++i, ++cp) { |
||||
data = (data << 8) | (*(uchar *)cp); |
||||
} |
||||
|
||||
return (write_word(info, wp, data)); |
||||
} |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Write a word to Flash, returns: |
||||
* 0 - OK |
||||
* 1 - write timeout |
||||
* 2 - Flash not erased |
||||
*/ |
||||
static int write_word (flash_info_t *info, ulong dest, ulong data) |
||||
{ |
||||
ulong addr = (ulong)(info->start[0]); |
||||
ulong start,last; |
||||
int flag; |
||||
ulong i; |
||||
int data_short[2]; |
||||
|
||||
/* Check if Flash is (sufficiently) erased */ |
||||
if ( ((ulong) *(ulong *)dest & data) != data ) { |
||||
return (2); |
||||
} |
||||
/* Disable interrupts which might cause a timeout here */ |
||||
flag = disable_interrupts(); |
||||
#if defined(CONFIG_BOOT_8B) |
||||
#ifdef DEBUG |
||||
{ |
||||
int in_mid,in_did; |
||||
my_out_8( (unsigned char * ) (addr+0x555) , 0xaa ); |
||||
my_out_8( (unsigned char * ) (addr+0x2aa) , 0x55 ); |
||||
my_out_8( (unsigned char * ) (addr+0x555) , 0x90 ); |
||||
in_mid=my_in_8( (unsigned char * ) addr ); |
||||
in_did=my_in_8( (unsigned char * ) (addr+1) ); |
||||
printf(" man ID=0x%x, dev ID=0x%x.\n",in_mid,in_did ); |
||||
my_out_8( (unsigned char *)addr, 0xf0); |
||||
udelay(1); |
||||
} |
||||
#endif |
||||
{ |
||||
int data_ch[4]; |
||||
data_ch[0]=(int ) ((data>>24) & 0xff); |
||||
data_ch[1]=(int ) ((data>>16) &0xff );
|
||||
data_ch[2]=(int ) ((data >>8) & 0xff); |
||||
data_ch[3]=(int ) (data & 0xff); |
||||
for (i=0;i<4;i++ ){ |
||||
my_out_8( (unsigned char *) (addr+0x555),0xaa); |
||||
my_out_8((unsigned char *) (addr+0x2aa),0x55); |
||||
my_out_8( (unsigned char *) (addr+0x555),0xa0); |
||||
my_out_8((unsigned char *) (dest+i) ,data_ch[i]); |
||||
/* re-enable interrupts if necessary */ |
||||
if (flag) |
||||
enable_interrupts(); |
||||
|
||||
start = get_timer (0); |
||||
last = start; |
||||
while( ( my_in_8((unsigned char *) (dest+i)) ) != ( data_ch[i] ) ) { |
||||
if (get_timer(start) > CFG_FLASH_WRITE_TOUT ) { |
||||
return 1; |
||||
} |
||||
} |
||||
}/* for */ |
||||
} |
||||
#elif defined( CONFIG_BOOT_16B) |
||||
data_short[0]=(int) (data>>16) & 0xffff; |
||||
data_short[1]=(int ) data & 0xffff ;
|
||||
for (i=0;i<2;i++ ){ |
||||
my_out_be16( (unsigned short *) ((ulong)addr+ 0xaaa),0xaa ); |
||||
my_out_be16( (unsigned short *) ((ulong)addr+ 0x554),0x55 ); |
||||
my_out_be16( (unsigned short *) ((ulong)addr+ 0xaaa),0xa0 ); |
||||
my_out_be16( (unsigned short *) (dest+(i*2)) ,data_short[i]); |
||||
/* re-enable interrupts if necessary */ |
||||
if (flag) |
||||
enable_interrupts(); |
||||
start = get_timer (0); |
||||
last = start; |
||||
while( ( my_in_be16((unsigned short *) (dest+(i*2))) ) != ( data_short[i] ) ) { |
||||
if (get_timer(start) > CFG_FLASH_WRITE_TOUT ) { |
||||
return 1; |
||||
} |
||||
} |
||||
} |
||||
#elif defined( CONFIG_BOOT_32B) |
||||
addr[0x0555] = 0x00AA00AA; |
||||
addr[0x02AA] = 0x00550055; |
||||
addr[0x0555] = 0x00A000A0; |
||||
|
||||
*((vu_long *)dest) = data; |
||||
|
||||
/* re-enable interrupts if necessary */ |
||||
if (flag) |
||||
enable_interrupts(); |
||||
|
||||
/* data polling for D7 */ |
||||
start = get_timer (0); |
||||
while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) { |
||||
if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { |
||||
return (1); |
||||
} |
||||
} |
||||
#endif |
||||
|
||||
|
||||
return (0); |
||||
} |
||||
#ifdef CONFIG_BOOT_8B |
||||
static int my_in_8 ( unsigned char *addr) |
||||
{ |
||||
int ret; |
||||
__asm__ __volatile__("lbz%U1%X1 %0,%1; eieio" : "=r" (ret) : "m" (*addr)); |
||||
return ret; |
||||
} |
||||
|
||||
static void my_out_8 ( unsigned char *addr, int val) |
||||
{ |
||||
__asm__ __volatile__("stb%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val)); |
||||
} |
||||
#endif |
||||
#ifdef CONFIG_BOOT_16B |
||||
static int my_in_be16( unsigned short *addr) |
||||
{ |
||||
int ret; |
||||
__asm__ __volatile__("lhz%U1%X1 %0,%1; eieio" : "=r" (ret) : "m" (*addr)); |
||||
return ret; |
||||
} |
||||
static void my_out_be16( unsigned short *addr, int val) |
||||
{ |
||||
__asm__ __volatile__("sth%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val)); |
||||
} |
||||
#endif |
||||
#ifdef CONFIG_BOOT_32B |
||||
static unsigned my_in_be32( unsigned *addr) |
||||
{ |
||||
unsigned ret; |
||||
__asm__ __volatile__("lwz%U1%X1 %0,%1; eieio" : "=r" (ret) : "m" (*addr)); |
||||
return ret; |
||||
} |
||||
static void my_out_be32( unsigned *addr, int val) |
||||
{ |
||||
__asm__ __volatile__("stw%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val)); |
||||
} |
||||
#endif |
||||
|
||||
|
||||
|
@ -0,0 +1,133 @@ |
||||
/* |
||||
* (C) Copyright 2000 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
OUTPUT_ARCH(powerpc) |
||||
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); |
||||
/* Do we need any of these for elf? |
||||
__DYNAMIC = 0; */ |
||||
SECTIONS |
||||
{ |
||||
/* Read-only sections, merged into text segment: */ |
||||
. = + SIZEOF_HEADERS; |
||||
.interp : { *(.interp) } |
||||
.hash : { *(.hash) } |
||||
.dynsym : { *(.dynsym) } |
||||
.dynstr : { *(.dynstr) } |
||||
.rel.text : { *(.rel.text) } |
||||
.rela.text : { *(.rela.text) } |
||||
.rel.data : { *(.rel.data) } |
||||
.rela.data : { *(.rela.data) } |
||||
.rel.rodata : { *(.rel.rodata) } |
||||
.rela.rodata : { *(.rela.rodata) } |
||||
.rel.got : { *(.rel.got) } |
||||
.rela.got : { *(.rela.got) } |
||||
.rel.ctors : { *(.rel.ctors) } |
||||
.rela.ctors : { *(.rela.ctors) } |
||||
.rel.dtors : { *(.rel.dtors) } |
||||
.rela.dtors : { *(.rela.dtors) } |
||||
.rel.bss : { *(.rel.bss) } |
||||
.rela.bss : { *(.rela.bss) } |
||||
.rel.plt : { *(.rel.plt) } |
||||
.rela.plt : { *(.rela.plt) } |
||||
.init : { *(.init) } |
||||
.plt : { *(.plt) } |
||||
.text : |
||||
{ |
||||
/* WARNING - the following is hand-optimized to fit within */ |
||||
/* the sector layout of our flash chips! XXX FIXME XXX */ |
||||
|
||||
cpu/mpc8xx/start.o (.text) |
||||
common/dlmalloc.o (.text) |
||||
ppc/ppcstring.o (.text) |
||||
ppc/vsprintf.o (.text) |
||||
ppc/crc32.o (.text) |
||||
ppc/zlib.o (.text) |
||||
|
||||
. = env_offset; |
||||
common/environment.o(.text) |
||||
|
||||
*(.text) |
||||
*(.fixup) |
||||
*(.got1) |
||||
} |
||||
_etext = .; |
||||
PROVIDE (etext = .); |
||||
.rodata : |
||||
{ |
||||
*(.rodata) |
||||
*(.rodata1) |
||||
} |
||||
.fini : { *(.fini) } =0 |
||||
.ctors : { *(.ctors) } |
||||
.dtors : { *(.dtors) } |
||||
|
||||
/* Read-write section, merged into data segment: */ |
||||
. = (. + 0x00FF) & 0xFFFFFF00; |
||||
_erotext = .; |
||||
PROVIDE (erotext = .); |
||||
.reloc : |
||||
{ |
||||
*(.got) |
||||
_GOT2_TABLE_ = .; |
||||
*(.got2) |
||||
_FIXUP_TABLE_ = .; |
||||
*(.fixup) |
||||
} |
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; |
||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2; |
||||
|
||||
.data : |
||||
{ |
||||
*(.data) |
||||
*(.data1) |
||||
*(.sdata) |
||||
*(.sdata2) |
||||
*(.dynamic) |
||||
CONSTRUCTORS |
||||
} |
||||
_edata = .; |
||||
PROVIDE (edata = .); |
||||
|
||||
__start___ex_table = .; |
||||
__ex_table : { *(__ex_table) } |
||||
__stop___ex_table = .; |
||||
|
||||
. = ALIGN(256); |
||||
__init_begin = .; |
||||
.text.init : { *(.text.init) } |
||||
.data.init : { *(.data.init) } |
||||
. = ALIGN(256); |
||||
__init_end = .; |
||||
|
||||
__bss_start = .; |
||||
.bss : |
||||
{ |
||||
*(.sbss) *(.scommon) |
||||
*(.dynbss) |
||||
*(.bss) |
||||
*(COMMON) |
||||
} |
||||
_end = . ; |
||||
PROVIDE (end = .); |
||||
} |
||||
|
@ -0,0 +1,131 @@ |
||||
/* |
||||
* (C) Copyright 2000 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
OUTPUT_ARCH(powerpc) |
||||
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); |
||||
/* Do we need any of these for elf? |
||||
__DYNAMIC = 0; */ |
||||
SECTIONS |
||||
{ |
||||
/* Read-only sections, merged into text segment: */ |
||||
. = + SIZEOF_HEADERS; |
||||
.interp : { *(.interp) } |
||||
.hash : { *(.hash) } |
||||
.dynsym : { *(.dynsym) } |
||||
.dynstr : { *(.dynstr) } |
||||
.rel.text : { *(.rel.text) } |
||||
.rela.text : { *(.rela.text) } |
||||
.rel.data : { *(.rel.data) } |
||||
.rela.data : { *(.rela.data) } |
||||
.rel.rodata : { *(.rel.rodata) } |
||||
.rela.rodata : { *(.rela.rodata) } |
||||
.rel.got : { *(.rel.got) } |
||||
.rela.got : { *(.rela.got) } |
||||
.rel.ctors : { *(.rel.ctors) } |
||||
.rela.ctors : { *(.rela.ctors) } |
||||
.rel.dtors : { *(.rel.dtors) } |
||||
.rela.dtors : { *(.rela.dtors) } |
||||
.rel.bss : { *(.rel.bss) } |
||||
.rela.bss : { *(.rela.bss) } |
||||
.rel.plt : { *(.rel.plt) } |
||||
.rela.plt : { *(.rela.plt) } |
||||
.init : { *(.init) } |
||||
.plt : { *(.plt) } |
||||
.text : |
||||
{ |
||||
/* WARNING - the following is hand-optimized to fit within */ |
||||
/* the sector layout of our flash chips! XXX FIXME XXX */ |
||||
|
||||
cpu/mpc8xx/start.o (.text) |
||||
common/dlmalloc.o (.text) |
||||
ppc/vsprintf.o (.text) |
||||
ppc/crc32.o (.text) |
||||
|
||||
. = env_offset; |
||||
common/environment.o(.text) |
||||
|
||||
*(.text) |
||||
*(.fixup) |
||||
*(.got1) |
||||
} |
||||
_etext = .; |
||||
PROVIDE (etext = .); |
||||
.rodata : |
||||
{ |
||||
*(.rodata) |
||||
*(.rodata1) |
||||
} |
||||
.fini : { *(.fini) } =0 |
||||
.ctors : { *(.ctors) } |
||||
.dtors : { *(.dtors) } |
||||
|
||||
/* Read-write section, merged into data segment: */ |
||||
. = (. + 0x0FFF) & 0xFFFFF000; |
||||
_erotext = .; |
||||
PROVIDE (erotext = .); |
||||
.reloc : |
||||
{ |
||||
*(.got) |
||||
_GOT2_TABLE_ = .; |
||||
*(.got2) |
||||
_FIXUP_TABLE_ = .; |
||||
*(.fixup) |
||||
} |
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; |
||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2; |
||||
|
||||
.data : |
||||
{ |
||||
*(.data) |
||||
*(.data1) |
||||
*(.sdata) |
||||
*(.sdata2) |
||||
*(.dynamic) |
||||
CONSTRUCTORS |
||||
} |
||||
_edata = .; |
||||
PROVIDE (edata = .); |
||||
|
||||
__start___ex_table = .; |
||||
__ex_table : { *(__ex_table) } |
||||
__stop___ex_table = .; |
||||
|
||||
. = ALIGN(4096); |
||||
__init_begin = .; |
||||
.text.init : { *(.text.init) } |
||||
.data.init : { *(.data.init) } |
||||
. = ALIGN(4096); |
||||
__init_end = .; |
||||
|
||||
__bss_start = .; |
||||
.bss : |
||||
{ |
||||
*(.sbss) *(.scommon) |
||||
*(.dynbss) |
||||
*(.bss) |
||||
*(COMMON) |
||||
} |
||||
_end = . ; |
||||
PROVIDE (end = .); |
||||
} |
||||
|
@ -0,0 +1,163 @@ |
||||
/*
|
||||
* (C) Copyright 2000, 2001, 2002 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <mpc8xx.h> |
||||
|
||||
/* ------------------------------------------------------------------------- */ |
||||
const uint sdram_table[] = |
||||
{ |
||||
/*-----------------
|
||||
UPM A contents: |
||||
----------------- */ |
||||
/*---------------------------------------------------
|
||||
Read Single Beat Cycle. Offset 0 in the RAM array. |
||||
---------------------------------------------------- */ |
||||
0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00 , |
||||
0x1ff77c47, 0x1ff77c35, 0xefeabc34, 0x1fb57c35 , |
||||
/*------------------------------------------------
|
||||
Read Burst Cycle. Offset 0x8 in the RAM array. |
||||
------------------------------------------------ */ |
||||
0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00, |
||||
0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47, |
||||
0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, |
||||
0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, |
||||
/*-------------------------------------------------------
|
||||
Write Single Beat Cycle. Offset 0x18 in the RAM array |
||||
------------------------------------------------------- */ |
||||
0x1f27fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47 , |
||||
0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff , |
||||
/*-------------------------------------------------
|
||||
Write Burst Cycle. Offset 0x20 in the RAM array |
||||
------------------------------------------------- */ |
||||
0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00, |
||||
0xf0affc00, 0xe1bbbc04, 0x1ff77c47, 0xffffffff, |
||||
0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff , |
||||
0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff , |
||||
/*------------------------------------------------------------------------
|
||||
Periodic Timer Expired. For DRAM refresh. Offset 0x30 in the RAM array |
||||
------------------------------------------------------------------------ */ |
||||
0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04, |
||||
0xfffffc84, 0xfffffc07, 0xffffffff, 0xffffffff, |
||||
0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff , |
||||
/*-----------
|
||||
* Exception: |
||||
* ----------- */ |
||||
0x7ffefc07, 0xffffffff, 0xffffffff, 0xffffffff , |
||||
}; |
||||
|
||||
/* ------------------------------------------------------------------------- */ |
||||
/*
|
||||
* Check Board Identity: |
||||
* |
||||
* Test ID string (SVM8...) |
||||
* |
||||
* Return 1 for "SC8xx" type, 0 else. |
||||
*/ |
||||
|
||||
int checkboard (void) |
||||
{ |
||||
unsigned char *s = getenv("serial#"); |
||||
int board_type; |
||||
|
||||
if (!s || strncmp(s, "SVM8", 4)) { |
||||
printf ("### No HW ID - assuming SVM SC8xx\n"); |
||||
return (0); |
||||
} |
||||
|
||||
board_type = 1; |
||||
|
||||
for (; *s; ++s) { |
||||
if (*s == ' ') |
||||
break; |
||||
putc (*s); |
||||
} |
||||
|
||||
putc ('\n'); |
||||
|
||||
return (0); |
||||
} |
||||
|
||||
/* ------------------------------------------------------------------------- */ |
||||
|
||||
long int initdram (int board_type) |
||||
{
|
||||
volatile immap_t *immap = (immap_t *)CFG_IMMR; |
||||
volatile memctl8xx_t *memctl = &immap->im_memctl; |
||||
long int size_b0 = 0; |
||||
|
||||
upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint)); |
||||
|
||||
memctl->memc_mptpr = CFG_MPTPR; |
||||
#if defined (CONFIG_SDRAM_16M) |
||||
memctl->memc_mamr = 0x00802114 | CFG_MxMR_PTx; |
||||
memctl->memc_mcr = 0x80002105; /* SDRAM bank 0 */ |
||||
udelay(1); |
||||
memctl->memc_mcr = 0x80002830; |
||||
udelay(1); |
||||
memctl->memc_mar = 0x00000088; |
||||
udelay(1); |
||||
memctl->memc_mcr = 0x80002106; |
||||
udelay(1); |
||||
memctl->memc_or1 = 0xff000a00; |
||||
size_b0 = 0x01000000; |
||||
#elif defined (CONFIG_SDRAM_32M) |
||||
memctl->memc_mamr = 0x00904114 | CFG_MxMR_PTx; |
||||
memctl->memc_mcr = 0x80002105; /* SDRAM bank 0 */ |
||||
udelay(1); |
||||
memctl->memc_mcr = 0x80002830; |
||||
udelay(1); |
||||
memctl->memc_mar = 0x00000088; |
||||
udelay(1); |
||||
memctl->memc_mcr = 0x80002106; |
||||
udelay(1); |
||||
memctl->memc_or1 = 0xfe000a00; |
||||
size_b0 = 0x02000000; |
||||
#elif defined (CONFIG_SDRAM_64M) |
||||
memctl->memc_mamr = 0x00a04114 | CFG_MxMR_PTx; |
||||
memctl->memc_mcr = 0x80002105; /* SDRAM bank 0 */ |
||||
udelay(1); |
||||
memctl->memc_mcr = 0x80002830; |
||||
udelay(1); |
||||
memctl->memc_mar = 0x00000088; |
||||
udelay(1); |
||||
memctl->memc_mcr = 0x80002106; |
||||
udelay(1); |
||||
memctl->memc_or1 = 0xfc000a00; |
||||
size_b0 = 0x04000000; |
||||
#else |
||||
#error SDRAM size configuration missing. |
||||
#endif |
||||
memctl->memc_br1 = 0x00000081; |
||||
udelay(200); |
||||
return (size_b0 ); |
||||
} |
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_DOC) |
||||
extern void doc_probe (ulong physadr); |
||||
void doc_init (void) |
||||
{ |
||||
doc_probe (CFG_DOC_BASE); |
||||
} |
||||
#endif |
||||
|
@ -0,0 +1,136 @@ |
||||
/* |
||||
* (C) Copyright 2000 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
OUTPUT_ARCH(powerpc) |
||||
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); |
||||
/* Do we need any of these for elf? |
||||
__DYNAMIC = 0; */ |
||||
SECTIONS |
||||
{ |
||||
/* Read-only sections, merged into text segment: */ |
||||
. = + SIZEOF_HEADERS; |
||||
.interp : { *(.interp) } |
||||
.hash : { *(.hash) } |
||||
.dynsym : { *(.dynsym) } |
||||
.dynstr : { *(.dynstr) } |
||||
.rel.text : { *(.rel.text) } |
||||
.rela.text : { *(.rela.text) } |
||||
.rel.data : { *(.rel.data) } |
||||
.rela.data : { *(.rela.data) } |
||||
.rel.rodata : { *(.rel.rodata) } |
||||
.rela.rodata : { *(.rela.rodata) } |
||||
.rel.got : { *(.rel.got) } |
||||
.rela.got : { *(.rela.got) } |
||||
.rel.ctors : { *(.rel.ctors) } |
||||
.rela.ctors : { *(.rela.ctors) } |
||||
.rel.dtors : { *(.rel.dtors) } |
||||
.rela.dtors : { *(.rela.dtors) } |
||||
.rel.bss : { *(.rel.bss) } |
||||
.rela.bss : { *(.rela.bss) } |
||||
.rel.plt : { *(.rel.plt) } |
||||
.rela.plt : { *(.rela.plt) } |
||||
.init : { *(.init) } |
||||
.plt : { *(.plt) } |
||||
.text : |
||||
{ |
||||
/* WARNING - the following is hand-optimized to fit within */ |
||||
/* the sector layout of our flash chips! XXX FIXME XXX */ |
||||
|
||||
cpu/mpc8xx/start.o (.text) |
||||
cpu/mpc8xx/traps.o (.text) |
||||
common/dlmalloc.o (.text) |
||||
lib_ppc/ppcstring.o (.text) |
||||
lib_generic/vsprintf.o (.text) |
||||
lib_generic/crc32.o (.text) |
||||
lib_generic/zlib.o (.text) |
||||
lib_ppc/cache.o (.text) |
||||
lib_ppc/time.o (.text) |
||||
|
||||
. = env_offset; |
||||
common/environment.o (.ppcenv) |
||||
|
||||
*(.text) |
||||
*(.fixup) |
||||
*(.got1) |
||||
} |
||||
_etext = .; |
||||
PROVIDE (etext = .); |
||||
.rodata : |
||||
{ |
||||
*(.rodata) |
||||
*(.rodata1) |
||||
} |
||||
.fini : { *(.fini) } =0 |
||||
.ctors : { *(.ctors) } |
||||
.dtors : { *(.dtors) } |
||||
|
||||
/* Read-write section, merged into data segment: */ |
||||
. = (. + 0x00FF) & 0xFFFFFF00; |
||||
_erotext = .; |
||||
PROVIDE (erotext = .); |
||||
.reloc : |
||||
{ |
||||
*(.got) |
||||
_GOT2_TABLE_ = .; |
||||
*(.got2) |
||||
_FIXUP_TABLE_ = .; |
||||
*(.fixup) |
||||
} |
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; |
||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2; |
||||
|
||||
.data : |
||||
{ |
||||
*(.data) |
||||
*(.data1) |
||||
*(.sdata) |
||||
*(.sdata2) |
||||
*(.dynamic) |
||||
CONSTRUCTORS |
||||
} |
||||
_edata = .; |
||||
PROVIDE (edata = .); |
||||
|
||||
__start___ex_table = .; |
||||
__ex_table : { *(__ex_table) } |
||||
__stop___ex_table = .; |
||||
|
||||
. = ALIGN(256); |
||||
__init_begin = .; |
||||
.text.init : { *(.text.init) } |
||||
.data.init : { *(.data.init) } |
||||
. = ALIGN(256); |
||||
__init_end = .; |
||||
|
||||
__bss_start = .; |
||||
.bss : |
||||
{ |
||||
*(.sbss) *(.scommon) |
||||
*(.dynbss) |
||||
*(.bss) |
||||
*(COMMON) |
||||
} |
||||
_end = . ; |
||||
PROVIDE (end = .); |
||||
} |
||||
|
@ -0,0 +1,131 @@ |
||||
/* |
||||
* (C) Copyright 2000 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
OUTPUT_ARCH(powerpc) |
||||
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); |
||||
/* Do we need any of these for elf? |
||||
__DYNAMIC = 0; */ |
||||
SECTIONS |
||||
{ |
||||
/* Read-only sections, merged into text segment: */ |
||||
. = + SIZEOF_HEADERS; |
||||
.interp : { *(.interp) } |
||||
.hash : { *(.hash) } |
||||
.dynsym : { *(.dynsym) } |
||||
.dynstr : { *(.dynstr) } |
||||
.rel.text : { *(.rel.text) } |
||||
.rela.text : { *(.rela.text) } |
||||
.rel.data : { *(.rel.data) } |
||||
.rela.data : { *(.rela.data) } |
||||
.rel.rodata : { *(.rel.rodata) } |
||||
.rela.rodata : { *(.rela.rodata) } |
||||
.rel.got : { *(.rel.got) } |
||||
.rela.got : { *(.rela.got) } |
||||
.rel.ctors : { *(.rel.ctors) } |
||||
.rela.ctors : { *(.rela.ctors) } |
||||
.rel.dtors : { *(.rel.dtors) } |
||||
.rela.dtors : { *(.rela.dtors) } |
||||
.rel.bss : { *(.rel.bss) } |
||||
.rela.bss : { *(.rela.bss) } |
||||
.rel.plt : { *(.rel.plt) } |
||||
.rela.plt : { *(.rela.plt) } |
||||
.init : { *(.init) } |
||||
.plt : { *(.plt) } |
||||
.text : |
||||
{ |
||||
/* WARNING - the following is hand-optimized to fit within */ |
||||
/* the sector layout of our flash chips! XXX FIXME XXX */ |
||||
|
||||
cpu/mpc8xx/start.o (.text) |
||||
common/dlmalloc.o (.text) |
||||
lib_generic/vsprintf.o (.text) |
||||
lib_generic/crc32.o (.text) |
||||
|
||||
. = env_offset; |
||||
common/environment.o(.text) |
||||
|
||||
*(.text) |
||||
*(.fixup) |
||||
*(.got1) |
||||
} |
||||
_etext = .; |
||||
PROVIDE (etext = .); |
||||
.rodata : |
||||
{ |
||||
*(.rodata) |
||||
*(.rodata1) |
||||
} |
||||
.fini : { *(.fini) } =0 |
||||
.ctors : { *(.ctors) } |
||||
.dtors : { *(.dtors) } |
||||
|
||||
/* Read-write section, merged into data segment: */ |
||||
. = (. + 0x0FFF) & 0xFFFFF000; |
||||
_erotext = .; |
||||
PROVIDE (erotext = .); |
||||
.reloc : |
||||
{ |
||||
*(.got) |
||||
_GOT2_TABLE_ = .; |
||||
*(.got2) |
||||
_FIXUP_TABLE_ = .; |
||||
*(.fixup) |
||||
} |
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; |
||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2; |
||||
|
||||
.data : |
||||
{ |
||||
*(.data) |
||||
*(.data1) |
||||
*(.sdata) |
||||
*(.sdata2) |
||||
*(.dynamic) |
||||
CONSTRUCTORS |
||||
} |
||||
_edata = .; |
||||
PROVIDE (edata = .); |
||||
|
||||
__start___ex_table = .; |
||||
__ex_table : { *(__ex_table) } |
||||
__stop___ex_table = .; |
||||
|
||||
. = ALIGN(4096); |
||||
__init_begin = .; |
||||
.text.init : { *(.text.init) } |
||||
.data.init : { *(.data.init) } |
||||
. = ALIGN(4096); |
||||
__init_end = .; |
||||
|
||||
__bss_start = .; |
||||
.bss : |
||||
{ |
||||
*(.sbss) *(.scommon) |
||||
*(.dynbss) |
||||
*(.bss) |
||||
*(COMMON) |
||||
} |
||||
_end = . ; |
||||
PROVIDE (end = .); |
||||
} |
||||
|
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,43 @@ |
||||
#
|
||||
# (C) Copyright 2003
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk |
||||
|
||||
LIB = lib$(CPU).a
|
||||
|
||||
START = start.o
|
||||
OBJS = serial.o interrupts.o cpu.o
|
||||
|
||||
all: .depend $(START) $(LIB) |
||||
|
||||
$(LIB): $(OBJS) |
||||
$(AR) crv $@ $(OBJS)
|
||||
|
||||
#########################################################################
|
||||
|
||||
.depend: Makefile $(START:.o=.S) $(OBJS:.o=.c) |
||||
$(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@
|
||||
|
||||
sinclude .depend |
||||
|
||||
#########################################################################
|
@ -0,0 +1,27 @@ |
||||
#
|
||||
# (C) Copyright 2002
|
||||
# Sysgo Real-Time Solutions, GmbH <www.elinos.com>
|
||||
# Marius Groeger <mgroeger@sysgo.de>
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \
|
||||
-mshort-load-bytes -msoft-float
|
||||
|
||||
PLATFORM_CPPFLAGS += -mapcs-32 -march=armv4 -mtune=arm7tdmi
|
@ -0,0 +1,177 @@ |
||||
/*
|
||||
* (C) Copyright 2002 |
||||
* Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
||||
* Marius Groeger <mgroeger@sysgo.de> |
||||
* |
||||
* (C) Copyright 2002 |
||||
* Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
||||
* Alex Zuepke <azu@sysgo.de> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
/*
|
||||
* CPU specific code |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <command.h> |
||||
#include <AT91RM9200.h> |
||||
|
||||
/* read co-processor 15, register #1 (control register) */ |
||||
static unsigned long read_p15_c1(void) |
||||
{ |
||||
unsigned long value; |
||||
|
||||
__asm__ __volatile__( |
||||
"mrc p15, 0, %0, c1, c0, 0 @ read control reg\n" |
||||
: "=r" (value) |
||||
: |
||||
: "memory"); |
||||
/*printf("p15/c1 is = %08lx\n", value); */ |
||||
return value; |
||||
} |
||||
|
||||
/* write to co-processor 15, register #1 (control register) */ |
||||
static void write_p15_c1(unsigned long value) |
||||
{ |
||||
/*printf("write %08lx to p15/c1\n", value); */ |
||||
__asm__ __volatile__( |
||||
"mcr p15, 0, %0, c1, c0, 0 @ write it back\n" |
||||
: "=r" (value) |
||||
: |
||||
: "memory"); |
||||
|
||||
read_p15_c1(); |
||||
} |
||||
|
||||
static void cp_delay(void) |
||||
{ |
||||
volatile int i; |
||||
|
||||
/* copro seems to need some delay between reading and writing */ |
||||
for (i=0; i<100; i++); |
||||
} |
||||
/* See also ARM Ref. Man. */ |
||||
#define C1_MMU (1<<0) /* mmu off/on */ |
||||
#define C1_ALIGN (1<<1) /* alignment faults off/on */ |
||||
#define C1_IDC (1<<2) /* icache and/or dcache off/on */ |
||||
#define C1_WRITE_BUFFER (1<<3) /* write buffer off/on */ |
||||
#define C1_BIG_ENDIAN (1<<7) /* big endian off/on */ |
||||
#define C1_SYS_PROT (1<<8) /* system protection */ |
||||
#define C1_ROM_PROT (1<<9) /* ROM protection */ |
||||
#define C1_HIGH_VECTORS (1<<13) /* location of vectors: low/high addresses */ |
||||
|
||||
int cpu_init(void) |
||||
{ |
||||
/*
|
||||
* setup up stack if necessary |
||||
*/ |
||||
#ifdef CONFIG_USE_IRQ |
||||
IRQ_STACK_START = _armboot_end + |
||||
CONFIG_STACKSIZE + CONFIG_STACKSIZE_IRQ - 4; |
||||
FIQ_STACK_START = IRQ_STACK_START + CONFIG_STACKSIZE_FIQ; |
||||
_armboot_real_end = FIQ_STACK_START + 4; |
||||
#else |
||||
_armboot_real_end = _armboot_end + CONFIG_STACKSIZE; |
||||
#endif |
||||
return 0; |
||||
} |
||||
|
||||
int cleanup_before_linux(void) |
||||
{ |
||||
/*
|
||||
* this function is called just before we call linux |
||||
* it prepares the processor for linux |
||||
* |
||||
* we turn off caches etc ... |
||||
* and we set the CPU-speed to 73 MHz - see start.S for details |
||||
*/ |
||||
|
||||
disable_interrupts(); |
||||
return 0; |
||||
} |
||||
|
||||
int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) |
||||
{ |
||||
|
||||
#ifdef CFG_SOFT_RESET |
||||
extern void reset_cpu(ulong addr); |
||||
|
||||
disable_interrupts(); |
||||
reset_cpu(0); |
||||
#else |
||||
AT91PS_USART us = AT91C_BASE_US1; |
||||
AT91PS_PIO pio = AT91C_BASE_PIOA; |
||||
|
||||
/*shutdown the console to avoid strange chars during reset */ |
||||
us->US_CR = (AT91C_US_RSTRX | AT91C_US_RSTTX); |
||||
|
||||
/* Clear PA19 to trigger the hard reset */ |
||||
pio->PIO_CODR = 0x00080000; |
||||
pio->PIO_OER = 0x00080000; |
||||
pio->PIO_PER = 0x00080000; |
||||
/* Never reached */ |
||||
#endif |
||||
return 0; |
||||
} |
||||
|
||||
void icache_enable(void) |
||||
{ |
||||
ulong reg; |
||||
reg = read_p15_c1(); |
||||
cp_delay(); |
||||
write_p15_c1(reg | C1_IDC); |
||||
} |
||||
|
||||
void icache_disable(void) |
||||
{ |
||||
ulong reg; |
||||
reg = read_p15_c1(); |
||||
cp_delay(); |
||||
write_p15_c1(reg & ~C1_IDC); |
||||
} |
||||
|
||||
int icache_status(void) |
||||
{ |
||||
return (read_p15_c1() & C1_IDC) != 0; |
||||
return 0; |
||||
} |
||||
|
||||
void dcache_enable(void) |
||||
{ |
||||
ulong reg; |
||||
reg = read_p15_c1(); |
||||
cp_delay(); |
||||
write_p15_c1(reg | C1_IDC); |
||||
} |
||||
|
||||
void dcache_disable(void) |
||||
{ |
||||
ulong reg; |
||||
reg = read_p15_c1(); |
||||
cp_delay(); |
||||
write_p15_c1(reg & ~C1_IDC); |
||||
} |
||||
|
||||
int dcache_status(void) |
||||
{ |
||||
return (read_p15_c1() & C1_IDC) != 0; |
||||
return 0; |
||||
} |
@ -0,0 +1,236 @@ |
||||
/*
|
||||
* (C) Copyright 2002 |
||||
* Lineo, Inc. <www.lineo.com> |
||||
* Bernhard Kuhn <bkuhn@lineo.com> |
||||
* |
||||
* (C) Copyright 2002 |
||||
* Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
||||
* Marius Groeger <mgroeger@sysgo.de> |
||||
* |
||||
* (C) Copyright 2002 |
||||
* Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
||||
* Alex Zuepke <azu@sysgo.de> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <AT91RM9200.h> |
||||
#include <asm/proc-armv/ptrace.h> |
||||
|
||||
extern void reset_cpu(ulong addr); |
||||
|
||||
/* we always count down the max. */ |
||||
#define TIMER_LOAD_VAL 0xffff |
||||
|
||||
/* macro to read the 16 bit timer */ |
||||
#define READ_TIMER (tmr->TC_CV) |
||||
AT91PS_TC tmr; |
||||
|
||||
|
||||
|
||||
void enable_interrupts (void) |
||||
{ |
||||
return; |
||||
} |
||||
int disable_interrupts (void) |
||||
{ |
||||
return 0; |
||||
} |
||||
|
||||
|
||||
void bad_mode(void) |
||||
{ |
||||
panic("Resetting CPU ...\n"); |
||||
reset_cpu(0); |
||||
} |
||||
|
||||
void show_regs(struct pt_regs * regs) |
||||
{ |
||||
unsigned long flags; |
||||
const char *processor_modes[]= |
||||
{ "USER_26", "FIQ_26" , "IRQ_26" , "SVC_26" , "UK4_26" , "UK5_26" , "UK6_26" , "UK7_26" , |
||||
"UK8_26" , "UK9_26" , "UK10_26", "UK11_26", "UK12_26", "UK13_26", "UK14_26", "UK15_26", |
||||
"USER_32", "FIQ_32" , "IRQ_32" , "SVC_32" , "UK4_32" , "UK5_32" , "UK6_32" , "ABT_32" , |
||||
"UK8_32" , "UK9_32" , "UK10_32", "UND_32" , "UK12_32", "UK13_32", "UK14_32", "SYS_32" |
||||
}; |
||||
|
||||
flags = condition_codes(regs); |
||||
|
||||
printf("pc : [<%08lx>] lr : [<%08lx>]\n" |
||||
"sp : %08lx ip : %08lx fp : %08lx\n", |
||||
instruction_pointer(regs), |
||||
regs->ARM_lr, regs->ARM_sp, |
||||
regs->ARM_ip, regs->ARM_fp); |
||||
printf("r10: %08lx r9 : %08lx r8 : %08lx\n", |
||||
regs->ARM_r10, regs->ARM_r9, |
||||
regs->ARM_r8); |
||||
printf("r7 : %08lx r6 : %08lx r5 : %08lx r4 : %08lx\n", |
||||
regs->ARM_r7, regs->ARM_r6, |
||||
regs->ARM_r5, regs->ARM_r4); |
||||
printf("r3 : %08lx r2 : %08lx r1 : %08lx r0 : %08lx\n", |
||||
regs->ARM_r3, regs->ARM_r2, |
||||
regs->ARM_r1, regs->ARM_r0); |
||||
printf("Flags: %c%c%c%c", |
||||
flags & CC_N_BIT ? 'N' : 'n', |
||||
flags & CC_Z_BIT ? 'Z' : 'z', |
||||
flags & CC_C_BIT ? 'C' : 'c', |
||||
flags & CC_V_BIT ? 'V' : 'v'); |
||||
printf(" IRQs %s FIQs %s Mode %s%s\n", |
||||
interrupts_enabled(regs) ? "on" : "off", |
||||
fast_interrupts_enabled(regs) ? "on" : "off", |
||||
processor_modes[processor_mode(regs)], |
||||
thumb_mode(regs) ? " (T)" : ""); |
||||
} |
||||
|
||||
void do_undefined_instruction(struct pt_regs *pt_regs) |
||||
{ |
||||
printf("undefined instruction\n"); |
||||
show_regs(pt_regs); |
||||
bad_mode(); |
||||
} |
||||
|
||||
void do_software_interrupt(struct pt_regs *pt_regs) |
||||
{ |
||||
printf("software interrupt\n"); |
||||
show_regs(pt_regs); |
||||
bad_mode(); |
||||
} |
||||
|
||||
void do_prefetch_abort(struct pt_regs *pt_regs) |
||||
{ |
||||
printf("prefetch abort\n"); |
||||
show_regs(pt_regs); |
||||
bad_mode(); |
||||
} |
||||
|
||||
void do_data_abort(struct pt_regs *pt_regs) |
||||
{ |
||||
printf("data abort\n"); |
||||
show_regs(pt_regs); |
||||
bad_mode(); |
||||
} |
||||
|
||||
void do_not_used(struct pt_regs *pt_regs) |
||||
{ |
||||
printf("not used\n"); |
||||
show_regs(pt_regs); |
||||
bad_mode(); |
||||
} |
||||
|
||||
void do_fiq(struct pt_regs *pt_regs) |
||||
{ |
||||
printf("fast interrupt request\n"); |
||||
show_regs(pt_regs); |
||||
bad_mode(); |
||||
} |
||||
|
||||
void do_irq(struct pt_regs *pt_regs) |
||||
{ |
||||
printf("interrupt request\n"); |
||||
show_regs(pt_regs); |
||||
bad_mode(); |
||||
} |
||||
|
||||
static ulong timestamp; |
||||
static ulong lastinc; |
||||
|
||||
int interrupt_init (void) |
||||
{ |
||||
|
||||
tmr = AT91C_BASE_TC0; |
||||
|
||||
/* enables TC1.0 clock */ |
||||
*AT91C_PMC_PCER = 1 << AT91C_ID_TC0; /* enable clock */ |
||||
|
||||
*AT91C_TCB0_BCR = 0; |
||||
*AT91C_TCB0_BMR = AT91C_TCB_TC0XC0S_NONE | AT91C_TCB_TC1XC1S_NONE | AT91C_TCB_TC2XC2S_NONE; |
||||
tmr->TC_CCR = AT91C_TC_CLKDIS; |
||||
tmr->TC_CMR = AT91C_TC_TIMER_DIV1_CLOCK; /* set to MCLK/2 */ |
||||
|
||||
tmr->TC_IDR = ~0ul; |
||||
tmr->TC_RC = TIMER_LOAD_VAL; |
||||
lastinc = TIMER_LOAD_VAL; |
||||
tmr->TC_CCR = AT91C_TC_SWTRG | AT91C_TC_CLKEN; |
||||
timestamp = 0; |
||||
return (0); |
||||
} |
||||
|
||||
/*
|
||||
* timer without interrupts |
||||
*/ |
||||
|
||||
void reset_timer(void) |
||||
{ |
||||
reset_timer_masked(); |
||||
} |
||||
|
||||
ulong get_timer (ulong base) |
||||
{ |
||||
return get_timer_masked() - base; |
||||
} |
||||
|
||||
void set_timer (ulong t) |
||||
{ |
||||
timestamp = t; |
||||
} |
||||
|
||||
void udelay(unsigned long usec) |
||||
{ |
||||
udelay_masked(usec); |
||||
} |
||||
|
||||
void reset_timer_masked(void) |
||||
{ |
||||
/* reset time */ |
||||
lastinc = READ_TIMER; |
||||
timestamp = 0; |
||||
} |
||||
|
||||
ulong get_timer_masked(void) |
||||
{ |
||||
ulong now = READ_TIMER; |
||||
if (now >= lastinc) |
||||
{ |
||||
/* normal mode */ |
||||
timestamp += now - lastinc; |
||||
} else { |
||||
/* we have an overflow ... */ |
||||
timestamp += now + TIMER_LOAD_VAL - lastinc; |
||||
} |
||||
lastinc = now; |
||||
|
||||
return timestamp; |
||||
} |
||||
|
||||
void udelay_masked(unsigned long usec) |
||||
{ |
||||
ulong tmo; |
||||
|
||||
tmo = usec / 1000; |
||||
tmo *= CFG_HZ; |
||||
tmo /= 1000; |
||||
|
||||
reset_timer_masked(); |
||||
|
||||
while(get_timer_masked() < tmo); |
||||
/*NOP*/; |
||||
} |
||||
|
||||
|
@ -0,0 +1,89 @@ |
||||
/*
|
||||
* (C) Copyright 2002 |
||||
* Lineo, Inc <www.lineo.com> |
||||
* Bernhard Kuhn <bkuhn@lineo.com> |
||||
* |
||||
* (C) Copyright 2002 |
||||
* Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
||||
* Marius Groeger <mgroeger@sysgo.de> |
||||
* |
||||
* (C) Copyright 2002 |
||||
* Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
||||
* Alex Zuepke <azu@sysgo.de> |
||||
* |
||||
* Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License as published by |
||||
* the Free Software Foundation; either version 2 of the License, or |
||||
* (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
||||
* |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <AT91RM9200.h> |
||||
|
||||
/* ggi thunder */ |
||||
AT91PS_USART us = (AT91PS_USART) AT91C_BASE_DBGU; |
||||
|
||||
void serial_setbrg(void) |
||||
{ |
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
int baudrate; |
||||
|
||||
if ((baudrate = gd->bd->bi_baudrate) <= 0) |
||||
baudrate = CONFIG_BAUDRATE; |
||||
us->US_BRGR = 33 /* AT91C_MASTER_CLOCK / baudrate / 16 */; /* hardcode so no __divsi3 */ |
||||
} |
||||
|
||||
int serial_init(void) |
||||
{ |
||||
/* make any port initializations specific to this port */ |
||||
*AT91C_PIOA_PDR = AT91C_PA31_DTXD | AT91C_PA30_DRXD; /* PA 31 & 30 */ |
||||
*AT91C_PMC_PCER = 1 << AT91C_ID_SYS; /* enable clock */ |
||||
serial_setbrg(); |
||||
|
||||
us->US_CR = AT91C_US_RSTRX | AT91C_US_RSTTX; |
||||
us->US_CR = AT91C_US_RXEN | AT91C_US_TXEN; |
||||
us->US_MR = ( AT91C_US_CLKS_CLOCK | AT91C_US_CHRL_8_BITS | AT91C_US_PAR_NONE | AT91C_US_NBSTOP_1_BIT ); |
||||
us->US_IMR = ~0ul; |
||||
return (0); |
||||
} |
||||
|
||||
void serial_putc(const char c) |
||||
{ |
||||
if (c == '\n') |
||||
serial_putc('\r'); |
||||
while( (us->US_CSR & AT91C_US_TXRDY) == 0 ) |
||||
; |
||||
us->US_THR=c; |
||||
} |
||||
|
||||
void |
||||
serial_puts (const char *s) |
||||
{ |
||||
while (*s) |
||||
{ |
||||
serial_putc (*s++); |
||||
} |
||||
} |
||||
|
||||
int serial_getc(void) |
||||
{ |
||||
while( (us->US_CSR & AT91C_US_RXRDY) == 0 ); |
||||
return us->US_RHR; |
||||
} |
||||
|
||||
int serial_tstc(void) |
||||
{ |
||||
return ((us->US_CSR & AT91C_US_RXRDY) == AT91C_US_RXRDY); |
||||
} |
@ -0,0 +1,347 @@ |
||||
/* |
||||
* armboot - Startup Code for ARM720 CPU-core |
||||
* |
||||
* Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
|
||||
* Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
|
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
|
||||
|
||||
#include "config.h" |
||||
#include "version.h" |
||||
|
||||
|
||||
/* |
||||
************************************************************************* |
||||
* |
||||
* Jump vector table as in table 3.1 in [1] |
||||
* |
||||
************************************************************************* |
||||
*/ |
||||
|
||||
|
||||
.globl _start
|
||||
_start: b reset |
||||
ldr pc, _undefined_instruction |
||||
ldr pc, _software_interrupt |
||||
ldr pc, _prefetch_abort |
||||
ldr pc, _data_abort |
||||
ldr pc, _not_used |
||||
ldr pc, _irq |
||||
ldr pc, _fiq |
||||
|
||||
_undefined_instruction: .word undefined_instruction |
||||
_software_interrupt: .word software_interrupt |
||||
_prefetch_abort: .word prefetch_abort |
||||
_data_abort: .word data_abort |
||||
_not_used: .word not_used |
||||
_irq: .word irq |
||||
_fiq: .word fiq |
||||
|
||||
.balignl 16,0xdeadbeef |
||||
|
||||
|
||||
/* |
||||
************************************************************************* |
||||
* |
||||
* Startup Code (reset vector) |
||||
* |
||||
* do important init only if we don't start from memory! |
||||
* relocate armboot to ram |
||||
* setup stack |
||||
* jump to second stage |
||||
* |
||||
************************************************************************* |
||||
*/ |
||||
|
||||
/* |
||||
* CFG_MEM_END is in the board dependent config-file (configs/config_BOARD.h) |
||||
*/ |
||||
_TEXT_BASE: |
||||
.word TEXT_BASE
|
||||
|
||||
.globl _armboot_start
|
||||
_armboot_start: |
||||
.word _start
|
||||
|
||||
/* |
||||
* Note: _armboot_end_data and _armboot_end are defined |
||||
* by the (board-dependent) linker script. |
||||
* _armboot_end_data is the first usable FLASH address after armboot |
||||
*/ |
||||
.globl _armboot_end_data
|
||||
_armboot_end_data: |
||||
.word armboot_end_data
|
||||
/* |
||||
* Note: armboot_end is defined by the (board-dependent) linker script |
||||
*/ |
||||
.globl _armboot_end
|
||||
_armboot_end: |
||||
.word armboot_end
|
||||
|
||||
/* |
||||
* _armboot_real_end is the first usable RAM address behind armboot |
||||
* and the various stacks |
||||
*/ |
||||
.globl _armboot_real_end
|
||||
_armboot_real_end: |
||||
.word 0x0badc0de
|
||||
|
||||
#ifdef CONFIG_USE_IRQ |
||||
/* IRQ stack memory (calculated at run-time) */ |
||||
.globl IRQ_STACK_START
|
||||
IRQ_STACK_START: |
||||
.word 0x0badc0de
|
||||
|
||||
/* IRQ stack memory (calculated at run-time) */ |
||||
.globl FIQ_STACK_START
|
||||
FIQ_STACK_START: |
||||
.word 0x0badc0de
|
||||
#endif |
||||
|
||||
|
||||
/* |
||||
* the actual reset code |
||||
*/ |
||||
|
||||
reset: |
||||
/* |
||||
* set the cpu to SVC32 mode |
||||
*/ |
||||
mrs r0,cpsr |
||||
bic r0,r0,#0x1f |
||||
orr r0,r0,#0x13 |
||||
msr cpsr,r0 |
||||
|
||||
/* |
||||
* relocate exeception table |
||||
*/ |
||||
ldr r0, =_start |
||||
ldr r1, =0x0 |
||||
mov r2, #16 |
||||
copyex: |
||||
subs r2, r2, #1 |
||||
ldr r3, [r0], #4 |
||||
str r3, [r1], #4 |
||||
bne copyex |
||||
|
||||
/* |
||||
* we do sys-critical inits only at reboot, |
||||
* not when booting from ram! |
||||
*/ |
||||
#ifdef CONFIG_INIT_CRITICAL |
||||
bl cpu_init_crit |
||||
#endif |
||||
|
||||
/* set up the stack */ |
||||
ldr r0, _armboot_end |
||||
add r0, r0, #CONFIG_STACKSIZE |
||||
sub sp, r0, #12 /* leave 3 words for abort-stack */ |
||||
ldr pc,_start_armboot |
||||
|
||||
_start_armboot: .word start_armboot |
||||
|
||||
/* |
||||
************************************************************************* |
||||
* |
||||
* CPU_init_critical registers |
||||
* |
||||
************************************************************************* |
||||
*/ |
||||
|
||||
cpu_init_crit: |
||||
# actually do nothing for now! |
||||
mov pc, lr |
||||
|
||||
|
||||
|
||||
|
||||
/* |
||||
************************************************************************* |
||||
* |
||||
* Interrupt handling |
||||
* |
||||
************************************************************************* |
||||
*/ |
||||
|
||||
@
|
||||
@ IRQ stack frame.
|
||||
@
|
||||
#define S_FRAME_SIZE 72 |
||||
|
||||
#define S_OLD_R0 68 |
||||
#define S_PSR 64 |
||||
#define S_PC 60 |
||||
#define S_LR 56 |
||||
#define S_SP 52 |
||||
|
||||
#define S_IP 48 |
||||
#define S_FP 44 |
||||
#define S_R10 40 |
||||
#define S_R9 36 |
||||
#define S_R8 32 |
||||
#define S_R7 28 |
||||
#define S_R6 24 |
||||
#define S_R5 20 |
||||
#define S_R4 16 |
||||
#define S_R3 12 |
||||
#define S_R2 8 |
||||
#define S_R1 4 |
||||
#define S_R0 0 |
||||
|
||||
#define MODE_SVC 0x13 |
||||
#define I_BIT 0x80 |
||||
|
||||
/* |
||||
* use bad_save_user_regs for abort/prefetch/undef/swi ... |
||||
* use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling |
||||
*/ |
||||
|
||||
.macro bad_save_user_regs
|
||||
sub sp, sp, #S_FRAME_SIZE |
||||
stmia sp, {r0 - r12} @ Calling r0-r12
|
||||
add r8, sp, #S_PC |
||||
|
||||
ldr r2, _armboot_end |
||||
add r2, r2, #CONFIG_STACKSIZE |
||||
sub r2, r2, #8 |
||||
ldmia r2, {r2 - r4} @ get pc, cpsr, old_r0
|
||||
add r0, sp, #S_FRAME_SIZE @ restore sp_SVC |
||||
|
||||
add r5, sp, #S_SP |
||||
mov r1, lr |
||||
stmia r5, {r0 - r4} @ save sp_SVC, lr_SVC, pc, cpsr, old_r
|
||||
mov r0, sp |
||||
.endm |
||||
|
||||
.macro irq_save_user_regs
|
||||
sub sp, sp, #S_FRAME_SIZE |
||||
stmia sp, {r0 - r12} @ Calling r0-r12
|
||||
add r8, sp, #S_PC |
||||
stmdb r8, {sp, lr}^ @ Calling SP, LR
|
||||
str lr, [r8, #0] @ Save calling PC
|
||||
mrs r6, spsr |
||||
str r6, [r8, #4] @ Save CPSR
|
||||
str r0, [r8, #8] @ Save OLD_R0
|
||||
mov r0, sp |
||||
.endm |
||||
|
||||
.macro irq_restore_user_regs
|
||||
ldmia sp, {r0 - lr}^ @ Calling r0 - lr
|
||||
mov r0, r0 |
||||
ldr lr, [sp, #S_PC] @ Get PC |
||||
add sp, sp, #S_FRAME_SIZE |
||||
subs pc, lr, #4 @ return & move spsr_svc into cpsr
|
||||
.endm |
||||
|
||||
.macro get_bad_stack
|
||||
ldr r13, _armboot_end @ setup our mode stack
|
||||
add r13, r13, #CONFIG_STACKSIZE @ resides at top of normal stack |
||||
sub r13, r13, #8 |
||||
|
||||
str lr, [r13] @ save caller lr / spsr
|
||||
mrs lr, spsr |
||||
str lr, [r13, #4] |
||||
|
||||
mov r13, #MODE_SVC @ prepare SVC-Mode |
||||
msr spsr_c, r13 |
||||
mov lr, pc |
||||
movs pc, lr |
||||
.endm |
||||
|
||||
.macro get_irq_stack @ setup IRQ stack
|
||||
ldr sp, IRQ_STACK_START |
||||
.endm |
||||
|
||||
.macro get_fiq_stack @ setup FIQ stack
|
||||
ldr sp, FIQ_STACK_START |
||||
.endm |
||||
|
||||
/* |
||||
* exception handlers |
||||
*/ |
||||
.align 5
|
||||
undefined_instruction: |
||||
get_bad_stack |
||||
bad_save_user_regs |
||||
bl do_undefined_instruction |
||||
|
||||
.align 5
|
||||
software_interrupt: |
||||
get_bad_stack |
||||
bad_save_user_regs |
||||
bl do_software_interrupt |
||||
|
||||
.align 5
|
||||
prefetch_abort: |
||||
get_bad_stack |
||||
bad_save_user_regs |
||||
bl do_prefetch_abort |
||||
|
||||
.align 5
|
||||
data_abort: |
||||
get_bad_stack |
||||
bad_save_user_regs |
||||
bl do_data_abort |
||||
|
||||
.align 5
|
||||
not_used: |
||||
get_bad_stack |
||||
bad_save_user_regs |
||||
bl do_not_used |
||||
|
||||
#ifdef CONFIG_USE_IRQ |
||||
|
||||
.align 5
|
||||
irq: |
||||
get_irq_stack |
||||
irq_save_user_regs |
||||
bl do_irq |
||||
irq_restore_user_regs |
||||
|
||||
.align 5
|
||||
fiq: |
||||
get_fiq_stack |
||||
/* someone ought to write a more effiction fiq_save_user_regs */ |
||||
irq_save_user_regs |
||||
bl do_fiq |
||||
irq_restore_user_regs |
||||
|
||||
#else |
||||
|
||||
.align 5
|
||||
irq: |
||||
get_bad_stack |
||||
bad_save_user_regs |
||||
bl do_irq |
||||
|
||||
.align 5
|
||||
fiq: |
||||
get_bad_stack |
||||
bad_save_user_regs |
||||
bl do_fiq |
||||
|
||||
#endif |
||||
|
||||
.align 5
|
||||
.globl reset_cpu
|
||||
reset_cpu: |
||||
mov pc, r0 |
@ -0,0 +1,251 @@ |
||||
|
||||
#include <common.h> |
||||
#include <command.h> |
||||
#include <AT91RM9200.h> |
||||
#include <net.h> |
||||
|
||||
/* ----- Ethernet Buffer definitions ----- */ |
||||
|
||||
typedef struct { |
||||
unsigned long addr,size; |
||||
} rbf_t; |
||||
|
||||
#define RBF_ADDR 0xfffffffc |
||||
#define RBF_OWNER (1<<0) |
||||
#define RBF_WRAP (1<<1) |
||||
#define RBF_BROADCAST (1<<31) |
||||
#define RBF_MULTICAST (1<<30) |
||||
#define RBF_UNICAST (1<<29) |
||||
#define RBF_EXTERNAL (1<<28) |
||||
#define RBF_UNKOWN (1<<27) |
||||
#define RBF_SIZE 0x07ff |
||||
#define RBF_LOCAL4 (1<<26) |
||||
#define RBF_LOCAL3 (1<<25) |
||||
#define RBF_LOCAL2 (1<<24) |
||||
#define RBF_LOCAL1 (1<<23) |
||||
|
||||
#define RBF_FRAMEMAX 10 |
||||
#define RBF_FRAMEMEM 0x200000 |
||||
#define RBF_FRAMELEN 0x600 |
||||
|
||||
#define RBF_FRAMEBTD RBF_FRAMEMEM |
||||
#define RBF_FRAMEBUF (RBF_FRAMEMEM + RBF_FRAMEMAX*sizeof(rbf_t)) |
||||
|
||||
/* stolen from mii.h */ |
||||
/* Generic MII registers. */ |
||||
|
||||
#define MII_BMCR 0x00 /* Basic mode control register */ |
||||
#define MII_BMSR 0x01 /* Basic mode status register */ |
||||
#define BMSR_JCD 0x0002 /* Jabber detected */ |
||||
#define BMSR_LSTATUS 0x0004 /* Link status */ |
||||
#define BMSR_10HALF 0x0800 /* Can do 10mbps, half-duplex */ |
||||
#define BMSR_100FULL 0x4000 /* Can do 100mbps, full-duplex */ |
||||
#define BMSR_10FULL 0x1000 /* Can do 10mbps, full-duplex */ |
||||
#define BMSR_100HALF 0x2000 /* Can do 100mbps, half-duplex */ |
||||
|
||||
#define MII_STS2_REG 17 /* Davicom specific */ |
||||
#define MII_MDINTR_REG 21 /* Davicom specific */ |
||||
|
||||
#ifdef CONFIG_DRIVER_ETHER |
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_NET) |
||||
|
||||
AT91PS_EMAC p_mac; |
||||
|
||||
int MII_ReadPhy(unsigned char addr, unsigned short *ret) |
||||
{ |
||||
|
||||
p_mac->EMAC_MAN = 0x60020000 | (addr << 18); |
||||
udelay(10000); |
||||
*ret = (unsigned short)p_mac->EMAC_MAN; |
||||
return 1; |
||||
} |
||||
|
||||
|
||||
int MII_GetLinkSpeed(void) |
||||
{ |
||||
unsigned short stat1, stat2; |
||||
int ret; |
||||
|
||||
if (!(ret = MII_ReadPhy(MII_BMSR, &stat1))) |
||||
return 0; |
||||
|
||||
if (stat1 & BMSR_JCD) |
||||
{ |
||||
#ifdef DEBUG |
||||
printf("MII: jabber condition detected\n"); |
||||
#endif /*jabber detected re-read the register*/ |
||||
} |
||||
if (!(ret = MII_ReadPhy(MII_BMSR, &stat1))) |
||||
return 0; |
||||
if (!(stat1 & BMSR_LSTATUS)) /* link status up? */ |
||||
{ |
||||
printf("MII: no Link\n"); |
||||
return 0; |
||||
} |
||||
|
||||
if (!(ret = MII_ReadPhy(MII_STS2_REG, &stat2))) |
||||
return 0; |
||||
|
||||
if ((stat1 & BMSR_100FULL) && (stat2 & 0x8000) ) |
||||
{ |
||||
/* set MII for 100BaseTX and Full Duplex */ |
||||
p_mac->EMAC_CFG |= AT91C_EMAC_SPD | AT91C_EMAC_FD; |
||||
#ifdef DEBUG |
||||
printf("MII: 100BaseTX and Full Duplex detected\n"); |
||||
#endif |
||||
return 1; |
||||
} |
||||
|
||||
else |
||||
if ((stat1 & BMSR_10FULL) && (stat2 & 0x2000)) |
||||
{ |
||||
/* set MII for 10BaseT and Full Duplex */ |
||||
p_mac->EMAC_CFG = (p_mac->EMAC_CFG & ~(AT91C_EMAC_SPD | AT91C_EMAC_FD)); |
||||
#ifdef DEBUG |
||||
printf("MII: 10BaseT and Full Duplex detected\n"); |
||||
#endif |
||||
return 1; |
||||
} |
||||
else |
||||
if ((stat1 & BMSR_100HALF) && (stat2 & 0x4000)) |
||||
{ |
||||
/* set MII for 100BaseTX and Half Duplex */ |
||||
p_mac->EMAC_CFG = (p_mac->EMAC_CFG & ~(AT91C_EMAC_SPD | AT91C_EMAC_FD)); |
||||
#ifdef DEBUG |
||||
printf("MII: 100BaseTX and Hall Duplex detected\n"); |
||||
#endif |
||||
return 1; |
||||
} |
||||
else |
||||
if ((stat1 & BMSR_10HALF) && (stat2 & 0x1000)) |
||||
{ |
||||
/*set MII for 10BaseT and Half Duplex */ |
||||
p_mac->EMAC_CFG &= ~(AT91C_EMAC_SPD | AT91C_EMAC_FD); |
||||
#ifdef DEBUG |
||||
printf("MII: 10BaseT and Hall Duplex detected\n"); |
||||
#endif |
||||
return 1; |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
|
||||
int MDIO_StartupPhy(void) |
||||
{ |
||||
int ret; |
||||
|
||||
if(p_mac->EMAC_SR & AT91C_EMAC_LINK) |
||||
{ |
||||
printf("MDIO_StartupPhy: no link\n"); |
||||
return 0; |
||||
}; |
||||
|
||||
p_mac->EMAC_CTL |= AT91C_EMAC_MPE; |
||||
|
||||
ret = MII_GetLinkSpeed(); |
||||
if (ret == 0) |
||||
{ |
||||
printf("MDIO_StartupPhy: MII_GetLinkSpeed failed\n"); |
||||
ret = 0; |
||||
} |
||||
else |
||||
{ |
||||
ret = 1; |
||||
} |
||||
|
||||
p_mac->EMAC_CTL &= ~AT91C_EMAC_MPE; |
||||
return ret; |
||||
|
||||
} |
||||
|
||||
|
||||
rbf_t* rbfdt; |
||||
rbf_t* rbfp; |
||||
|
||||
int eth_init( bd_t *bd ) |
||||
{ |
||||
int ret; |
||||
int i; |
||||
p_mac = AT91C_BASE_EMAC; |
||||
|
||||
*AT91C_PIOA_PDR = AT91C_PA16_EMDIO | |
||||
AT91C_PA15_EMDC | AT91C_PA14_ERXER | AT91C_PA13_ERX1 | AT91C_PA12_ERX0 | |
||||
AT91C_PA11_ECRS_ECRSDV | AT91C_PA10_ETX1 | AT91C_PA9_ETX0 | AT91C_PA8_ETXEN | |
||||
AT91C_PA7_ETXCK_EREFCK; /* PIO Disable Register */ |
||||
|
||||
*AT91C_PIOB_PDR = AT91C_PB25_EF100 | |
||||
AT91C_PB19_ERXCK | AT91C_PB18_ECOL | AT91C_PB17_ERXDV | AT91C_PB16_ERX3 | |
||||
AT91C_PB15_ERX2 | AT91C_PB14_ETXER | AT91C_PB13_ETX3 | AT91C_PB12_ETX2; |
||||
|
||||
*AT91C_PIOB_BSR = AT91C_PB25_EF100 | |
||||
AT91C_PB19_ERXCK | AT91C_PB18_ECOL | AT91C_PB17_ERXDV | AT91C_PB16_ERX3 | |
||||
AT91C_PB15_ERX2 | AT91C_PB14_ETXER | AT91C_PB13_ETX3 | AT91C_PB12_ETX2; /* Select B Register */ |
||||
*AT91C_PMC_PCER = 1 << AT91C_ID_EMAC; /* Peripheral Clock Enable Register */ |
||||
p_mac->EMAC_CFG |= AT91C_EMAC_CSR; /* Clear statistics */ |
||||
|
||||
rbfdt=(rbf_t *)RBF_FRAMEBTD; |
||||
for(i = 0; i < RBF_FRAMEMAX; i++) |
||||
{ |
||||
rbfdt[i].addr=RBF_FRAMEBUF+RBF_FRAMELEN*i; |
||||
rbfdt[i].size=0; |
||||
} |
||||
rbfdt[RBF_FRAMEMAX-1].addr|=RBF_WRAP; |
||||
rbfp=&rbfdt[0]; |
||||
|
||||
if (!(ret = MDIO_StartupPhy())) |
||||
{ |
||||
printf("MAC: error during MII initialization\n"); |
||||
return 0; |
||||
} |
||||
|
||||
p_mac->EMAC_SA2L = (bd->bi_enetaddr[3] << 24) | (bd->bi_enetaddr[2] << 16) |
||||
| (bd->bi_enetaddr[1] << 8) | (bd->bi_enetaddr[0]); |
||||
p_mac->EMAC_SA2H = (bd->bi_enetaddr[5] << 8) | (bd->bi_enetaddr[4]); |
||||
|
||||
p_mac->EMAC_RBQP = (long)(&rbfdt[0]); |
||||
p_mac->EMAC_RSR &= ~(AT91C_EMAC_RSR_OVR | AT91C_EMAC_REC | AT91C_EMAC_BNA); |
||||
p_mac->EMAC_CFG = (p_mac->EMAC_CFG | AT91C_EMAC_CAF | AT91C_EMAC_NBC | AT91C_EMAC_RMII) & ~AT91C_EMAC_CLK; |
||||
p_mac->EMAC_CTL |= AT91C_EMAC_TE | AT91C_EMAC_RE ; |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int eth_send(volatile void *packet, int length) |
||||
{ |
||||
while(!(p_mac->EMAC_TSR & AT91C_EMAC_BNQ)) |
||||
; |
||||
p_mac->EMAC_TAR = (long)packet; |
||||
p_mac->EMAC_TCR = length; |
||||
while(p_mac->EMAC_TCR & 0x7ff) |
||||
; |
||||
p_mac->EMAC_TSR |= AT91C_EMAC_COMP; |
||||
return 0; |
||||
} |
||||
|
||||
int eth_rx(void) |
||||
{ |
||||
int size; |
||||
|
||||
if(!(rbfp->addr & RBF_OWNER)) |
||||
return 0; |
||||
|
||||
size=rbfp->size & RBF_SIZE; |
||||
NetReceive((volatile uchar *) (rbfp->addr & RBF_ADDR), size); |
||||
|
||||
rbfp->addr &= ~RBF_OWNER; |
||||
if(rbfp->addr & RBF_WRAP) |
||||
rbfp = &rbfdt[0]; |
||||
else |
||||
rbfp++; |
||||
|
||||
p_mac->EMAC_RSR |= AT91C_EMAC_REC; |
||||
|
||||
return size; |
||||
} |
||||
|
||||
void eth_halt( void ) |
||||
{}; |
||||
#endif |
||||
#endif |
@ -0,0 +1,349 @@ |
||||
/* ---------------------------------------------------------------------------- */ |
||||
/* ATMEL Microcontroller Software Support - ROUSSET - */ |
||||
/* ---------------------------------------------------------------------------- */ |
||||
/* The software is delivered "AS IS" without warranty or condition of any */ |
||||
/* kind, either express, implied or statutory. This includes without */ |
||||
/* limitation any warranty or condition with respect to merchantability or */ |
||||
/* fitness for any particular purpose, or against the infringements of */ |
||||
/* intellectual property rights of others. */ |
||||
/* ---------------------------------------------------------------------------- */ |
||||
/* File Name : AT91RM9200.h */ |
||||
/* Object : AT91RM9200 definitions */ |
||||
/* Generated : AT91 SW Application Group 10/29/2002 (16:10:51) */ |
||||
#ifndef AT91RM9200_H |
||||
#define AT91RM9200_H |
||||
|
||||
typedef volatile unsigned int AT91_REG;/* Hardware register definition */ |
||||
|
||||
/* ***************************************************************************** */ |
||||
/* SOFTWARE API DEFINITION FOR Timer Counter Channel Interface */ |
||||
/* ***************************************************************************** */ |
||||
typedef struct _AT91S_TC { |
||||
AT91_REG TC_CCR; /* Channel Control Register */ |
||||
AT91_REG TC_CMR; /* Channel Mode Register */ |
||||
AT91_REG Reserved0[2]; /* */ |
||||
AT91_REG TC_CV; /* Counter Value */ |
||||
AT91_REG TC_RA; /* Register A */ |
||||
AT91_REG TC_RB; /* Register B */ |
||||
AT91_REG TC_RC; /* Register C */ |
||||
AT91_REG TC_SR; /* Status Register */ |
||||
AT91_REG TC_IER; /* Interrupt Enable Register */ |
||||
AT91_REG TC_IDR; /* Interrupt Disable Register */ |
||||
AT91_REG TC_IMR; /* Interrupt Mask Register */ |
||||
} AT91S_TC, *AT91PS_TC; |
||||
|
||||
/* ***************************************************************************** */ |
||||
/* SOFTWARE API DEFINITION FOR Usart */ |
||||
/* ***************************************************************************** */ |
||||
typedef struct _AT91S_USART { |
||||
AT91_REG US_CR; /* Control Register */ |
||||
AT91_REG US_MR; /* Mode Register */ |
||||
AT91_REG US_IER; /* Interrupt Enable Register */ |
||||
AT91_REG US_IDR; /* Interrupt Disable Register */ |
||||
AT91_REG US_IMR; /* Interrupt Mask Register */ |
||||
AT91_REG US_CSR; /* Channel Status Register */ |
||||
AT91_REG US_RHR; /* Receiver Holding Register */ |
||||
AT91_REG US_THR; /* Transmitter Holding Register */ |
||||
AT91_REG US_BRGR; /* Baud Rate Generator Register */ |
||||
AT91_REG US_RTOR; /* Receiver Time-out Register */ |
||||
AT91_REG US_TTGR; /* Transmitter Time-guard Register */ |
||||
AT91_REG Reserved0[5]; /* */ |
||||
AT91_REG US_FIDI; /* FI_DI_Ratio Register */ |
||||
AT91_REG US_NER; /* Nb Errors Register */ |
||||
AT91_REG US_XXR; /* XON_XOFF Register */ |
||||
AT91_REG US_IF; /* IRDA_FILTER Register */ |
||||
AT91_REG Reserved1[44]; /* */ |
||||
AT91_REG US_RPR; /* Receive Pointer Register */ |
||||
AT91_REG US_RCR; /* Receive Counter Register */ |
||||
AT91_REG US_TPR; /* Transmit Pointer Register */ |
||||
AT91_REG US_TCR; /* Transmit Counter Register */ |
||||
AT91_REG US_RNPR; /* Receive Next Pointer Register */ |
||||
AT91_REG US_RNCR; /* Receive Next Counter Register */ |
||||
AT91_REG US_TNPR; /* Transmit Next Pointer Register */ |
||||
AT91_REG US_TNCR; /* Transmit Next Counter Register */ |
||||
AT91_REG US_PTCR; /* PDC Transfer Control Register */ |
||||
AT91_REG US_PTSR; /* PDC Transfer Status Register */ |
||||
} AT91S_USART, *AT91PS_USART; |
||||
|
||||
/* ***************************************************************************** */ |
||||
/* SOFTWARE API DEFINITION FOR Parallel Input Output Controler */ |
||||
/* ***************************************************************************** */ |
||||
typedef struct _AT91S_PIO { |
||||
AT91_REG PIO_PER; /* PIO Enable Register */ |
||||
AT91_REG PIO_PDR; /* PIO Disable Register */ |
||||
AT91_REG PIO_PSR; /* PIO Status Register */ |
||||
AT91_REG Reserved0[1]; /* */ |
||||
AT91_REG PIO_OER; /* Output Enable Register */ |
||||
AT91_REG PIO_ODR; /* Output Disable Registerr */ |
||||
AT91_REG PIO_OSR; /* Output Status Register */ |
||||
AT91_REG Reserved1[1]; /* */ |
||||
AT91_REG PIO_IFER; /* Input Filter Enable Register */ |
||||
AT91_REG PIO_IFDR; /* Input Filter Disable Register */ |
||||
AT91_REG PIO_IFSR; /* Input Filter Status Register */ |
||||
AT91_REG Reserved2[1]; /* */ |
||||
AT91_REG PIO_SODR; /* Set Output Data Register */ |
||||
AT91_REG PIO_CODR; /* Clear Output Data Register */ |
||||
AT91_REG PIO_ODSR; /* Output Data Status Register */ |
||||
AT91_REG PIO_PDSR; /* Pin Data Status Register */ |
||||
AT91_REG PIO_IER; /* Interrupt Enable Register */ |
||||
AT91_REG PIO_IDR; /* Interrupt Disable Register */ |
||||
AT91_REG PIO_IMR; /* Interrupt Mask Register */ |
||||
AT91_REG PIO_ISR; /* Interrupt Status Register */ |
||||
AT91_REG PIO_MDER; /* Multi-driver Enable Register */ |
||||
AT91_REG PIO_MDDR; /* Multi-driver Disable Register */ |
||||
AT91_REG PIO_MDSR; /* Multi-driver Status Register */ |
||||
AT91_REG Reserved3[1]; /* */ |
||||
AT91_REG PIO_PPUDR; /* Pull-up Disable Register */ |
||||
AT91_REG PIO_PPUER; /* Pull-up Enable Register */ |
||||
AT91_REG PIO_PPUSR; /* Pad Pull-up Status Register */ |
||||
AT91_REG Reserved4[1]; /* */ |
||||
AT91_REG PIO_ASR; /* Select A Register */ |
||||
AT91_REG PIO_BSR; /* Select B Register */ |
||||
AT91_REG PIO_ABSR; /* AB Select Status Register */ |
||||
AT91_REG Reserved5[9]; /* */ |
||||
AT91_REG PIO_OWER; /* Output Write Enable Register */ |
||||
AT91_REG PIO_OWDR; /* Output Write Disable Register */ |
||||
AT91_REG PIO_OWSR; /* Output Write Status Register */ |
||||
} AT91S_PIO, *AT91PS_PIO; |
||||
|
||||
|
||||
/* ***************************************************************************** */ |
||||
/* SOFTWARE API DEFINITION FOR Debug Unit */ |
||||
/* ***************************************************************************** */ |
||||
typedef struct _AT91S_DBGU { |
||||
AT91_REG DBGU_CR; /* Control Register */ |
||||
AT91_REG DBGU_MR; /* Mode Register */ |
||||
AT91_REG DBGU_IER; /* Interrupt Enable Register */ |
||||
AT91_REG DBGU_IDR; /* Interrupt Disable Register */ |
||||
AT91_REG DBGU_IMR; /* Interrupt Mask Register */ |
||||
AT91_REG DBGU_CSR; /* Channel Status Register */ |
||||
AT91_REG DBGU_RHR; /* Receiver Holding Register */ |
||||
AT91_REG DBGU_THR; /* Transmitter Holding Register */ |
||||
AT91_REG DBGU_BRGR; /* Baud Rate Generator Register */ |
||||
AT91_REG Reserved0[7]; /* */ |
||||
AT91_REG DBGU_C1R; /* Chip ID1 Register */ |
||||
AT91_REG DBGU_C2R; /* Chip ID2 Register */ |
||||
AT91_REG DBGU_FNTR; /* Force NTRST Register */ |
||||
AT91_REG Reserved1[45]; /* */ |
||||
AT91_REG DBGU_RPR; /* Receive Pointer Register */ |
||||
AT91_REG DBGU_RCR; /* Receive Counter Register */ |
||||
AT91_REG DBGU_TPR; /* Transmit Pointer Register */ |
||||
AT91_REG DBGU_TCR; /* Transmit Counter Register */ |
||||
AT91_REG DBGU_RNPR; /* Receive Next Pointer Register */ |
||||
AT91_REG DBGU_RNCR; /* Receive Next Counter Register */ |
||||
AT91_REG DBGU_TNPR; /* Transmit Next Pointer Register */ |
||||
AT91_REG DBGU_TNCR; /* Transmit Next Counter Register */ |
||||
AT91_REG DBGU_PTCR; /* PDC Transfer Control Register */ |
||||
AT91_REG DBGU_PTSR; /* PDC Transfer Status Register */ |
||||
} AT91S_DBGU, *AT91PS_DBGU; |
||||
|
||||
|
||||
/* ***************************************************************************** */ |
||||
/* SOFTWARE API DEFINITION FOR Static Memory Controller 2 Interface */ |
||||
/* ***************************************************************************** */ |
||||
typedef struct _AT91S_SMC2 { |
||||
AT91_REG SMC2_CSR[8]; /* SMC2 Chip Select Register */ |
||||
} AT91S_SMC2, *AT91PS_SMC2; |
||||
|
||||
/* ***************************************************************************** */ |
||||
/* SOFTWARE API DEFINITION FOR Ethernet MAC */ |
||||
/* ***************************************************************************** */ |
||||
typedef struct _AT91S_EMAC { |
||||
AT91_REG EMAC_CTL; /* Network Control Register */ |
||||
AT91_REG EMAC_CFG; /* Network Configuration Register */ |
||||
AT91_REG EMAC_SR; /* Network Status Register */ |
||||
AT91_REG EMAC_TAR; /* Transmit Address Register */ |
||||
AT91_REG EMAC_TCR; /* Transmit Control Register */ |
||||
AT91_REG EMAC_TSR; /* Transmit Status Register */ |
||||
AT91_REG EMAC_RBQP; /* Receive Buffer Queue Pointer */ |
||||
AT91_REG Reserved0[1]; /* */ |
||||
AT91_REG EMAC_RSR; /* Receive Status Register */ |
||||
AT91_REG EMAC_ISR; /* Interrupt Status Register */ |
||||
AT91_REG EMAC_IER; /* Interrupt Enable Register */ |
||||
AT91_REG EMAC_IDR; /* Interrupt Disable Register */ |
||||
AT91_REG EMAC_IMR; /* Interrupt Mask Register */ |
||||
AT91_REG EMAC_MAN; /* PHY Maintenance Register */ |
||||
AT91_REG Reserved1[2]; /* */ |
||||
AT91_REG EMAC_FRA; /* Frames Transmitted OK Register */ |
||||
AT91_REG EMAC_SCOL; /* Single Collision Frame Register */ |
||||
AT91_REG EMAC_MCOL; /* Multiple Collision Frame Register */ |
||||
AT91_REG EMAC_OK; /* Frames Received OK Register */ |
||||
AT91_REG EMAC_SEQE; /* Frame Check Sequence Error Register */ |
||||
AT91_REG EMAC_ALE; /* Alignment Error Register */ |
||||
AT91_REG EMAC_DTE; /* Deferred Transmission Frame Register */ |
||||
AT91_REG EMAC_LCOL; /* Late Collision Register */ |
||||
AT91_REG EMAC_ECOL; /* Excessive Collision Register */ |
||||
AT91_REG EMAC_CSE; /* Carrier Sense Error Register */ |
||||
AT91_REG EMAC_TUE; /* Transmit Underrun Error Register */ |
||||
AT91_REG EMAC_CDE; /* Code Error Register */ |
||||
AT91_REG EMAC_ELR; /* Excessive Length Error Register */ |
||||
AT91_REG EMAC_RJB; /* Receive Jabber Register */ |
||||
AT91_REG EMAC_USF; /* Undersize Frame Register */ |
||||
AT91_REG EMAC_SQEE; /* SQE Test Error Register */ |
||||
AT91_REG EMAC_DRFC; /* Discarded RX Frame Register */ |
||||
AT91_REG Reserved2[3]; /* */ |
||||
AT91_REG EMAC_HSH; /* Hash Address High[63:32] */ |
||||
AT91_REG EMAC_HSL; /* Hash Address Low[31:0] */ |
||||
AT91_REG EMAC_SA1L; /* Specific Address 1 Low, First 4 bytes */ |
||||
AT91_REG EMAC_SA1H; /* Specific Address 1 High, Last 2 bytes */ |
||||
AT91_REG EMAC_SA2L; /* Specific Address 2 Low, First 4 bytes */ |
||||
AT91_REG EMAC_SA2H; /* Specific Address 2 High, Last 2 bytes */ |
||||
AT91_REG EMAC_SA3L; /* Specific Address 3 Low, First 4 bytes */ |
||||
AT91_REG EMAC_SA3H; /* Specific Address 3 High, Last 2 bytes */ |
||||
AT91_REG EMAC_SA4L; /* Specific Address 4 Low, First 4 bytes */ |
||||
AT91_REG EMAC_SA4H; /* Specific Address 4 High, Last 2 bytesr */ |
||||
} AT91S_EMAC, *AT91PS_EMAC; |
||||
|
||||
/* -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- */ |
||||
#define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) /* (DBGU) RXRDY Interrupt */ |
||||
#define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) /* (DBGU) TXRDY Interrupt */ |
||||
#define AT91C_US_ENDRX ((unsigned int) 0x1 << 3) /* (DBGU) End of Receive Transfer Interrupt */ |
||||
#define AT91C_US_ENDTX ((unsigned int) 0x1 << 4) /* (DBGU) End of Transmit Interrupt */ |
||||
#define AT91C_US_OVRE ((unsigned int) 0x1 << 5) /* (DBGU) Overrun Interrupt */ |
||||
#define AT91C_US_FRAME ((unsigned int) 0x1 << 6) /* (DBGU) Framing Error Interrupt */ |
||||
#define AT91C_US_PARE ((unsigned int) 0x1 << 7) /* (DBGU) Parity Error Interrupt */ |
||||
#define AT91C_US_TXEMPTY ((unsigned int) 0x1 << 9) /* (DBGU) TXEMPTY Interrupt */ |
||||
#define AT91C_US_TXBUFE ((unsigned int) 0x1 << 11) /* (DBGU) TXBUFE Interrupt */ |
||||
#define AT91C_US_RXBUFF ((unsigned int) 0x1 << 12) /* (DBGU) RXBUFF Interrupt */ |
||||
#define AT91C_US_COMM_TX ((unsigned int) 0x1 << 30) /* (DBGU) COMM_TX Interrupt */ |
||||
#define AT91C_US_COMM_RX ((unsigned int) 0x1 << 31) /* (DBGU) COMM_RX Interrupt */ |
||||
|
||||
/* -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- */ |
||||
#define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) /* (DBGU) Reset Receiver */ |
||||
#define AT91C_US_RSTTX ((unsigned int) 0x1 << 3) /* (DBGU) Reset Transmitter */ |
||||
#define AT91C_US_RXEN ((unsigned int) 0x1 << 4) /* (DBGU) Receiver Enable */ |
||||
#define AT91C_US_RXDIS ((unsigned int) 0x1 << 5) /* (DBGU) Receiver Disable */ |
||||
#define AT91C_US_TXEN ((unsigned int) 0x1 << 6) /* (DBGU) Transmitter Enable */ |
||||
#define AT91C_US_TXDIS ((unsigned int) 0x1 << 7) /* (DBGU) Transmitter Disable */ |
||||
|
||||
#define AT91C_US_CLKS_CLOCK ((unsigned int) 0x0 << 4) /* (USART) Clock */ |
||||
#define AT91C_US_CHRL_8_BITS ((unsigned int) 0x3 << 6) /* (USART) Character Length: 8 bits */ |
||||
#define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) /* (DBGU) No Parity */ |
||||
#define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) /* (USART) 1 stop bit */ |
||||
|
||||
#define AT91C_PMC_PCER ((AT91_REG *) 0xFFFFFC10) /* (PMC) Peripheral Clock Enable Register */ |
||||
#define AT91C_PIOA_PDR ((AT91_REG *) 0xFFFFF404) /* (PIOA) PIO Disable Register */ |
||||
#define AT91C_PIO_PA30 ((unsigned int) 1 << 30) /* Pin Controlled by PA30 */ |
||||
#define AT91C_PIO_PC0 ((unsigned int) 1 << 0) /* Pin Controlled by PC0 */ |
||||
#define AT91C_PC0_BFCK ((unsigned int) AT91C_PIO_PC0) /* Burst Flash Clock */ |
||||
#define AT91C_PA30_DRXD ((unsigned int) AT91C_PIO_PA30) /* DBGU Debug Receive Data */ |
||||
#define AT91C_PIO_PA31 ((unsigned int) 1 << 31) /* Pin Controlled by PA31 */ |
||||
#define AT91C_PA31_DTXD ((unsigned int) AT91C_PIO_PA31) /* DBGU Debug Transmit Data */ |
||||
|
||||
#define AT91C_ID_SYS ((unsigned int) 1) /* System Peripheral */ |
||||
#define AT91C_ID_TC0 ((unsigned int) 17) /* Timer Counter 0 */ |
||||
#define AT91C_ID_EMAC ((unsigned int) 24) /* Ethernet MAC */ |
||||
|
||||
#define AT91C_PIO_PC1 ((unsigned int) 1 << 1) /* Pin Controlled by PC1 */ |
||||
#define AT91C_PC1_BFRDY_SMOE ((unsigned int) AT91C_PIO_PC1) /* Burst Flash Ready */ |
||||
#define AT91C_PIO_PC3 ((unsigned int) 1 << 3) /* Pin Controlled by PC3 */ |
||||
#define AT91C_PC3_BFBAA_SMWE ((unsigned int) AT91C_PIO_PC3) /* Burst Flash Address Advance / SmartMedia Write Enable */ |
||||
#define AT91C_PIO_PC2 ((unsigned int) 1 << 2) /* Pin Controlled by PC2 */ |
||||
#define AT91C_PC2_BFAVD ((unsigned int) AT91C_PIO_PC2) /* Burst Flash Address Valid */ |
||||
#define AT91C_PIO_PB1 ((unsigned int) 1 << 1) /* Pin Controlled by PB1 */ |
||||
|
||||
#define AT91C_TC_TIMER_DIV1_CLOCK ((unsigned int) 0x0 << 0) /* (TC) MCK/2 */ |
||||
#define AT91C_TC_TIMER_DIV2_CLOCK ((unsigned int) 0x1 << 0) /* (TC) MCK/8 */ |
||||
#define AT91C_TC_TIMER_DIV3_CLOCK ((unsigned int) 0x2 << 0) /* (TC) MCK/32 */ |
||||
#define AT91C_TC_TIMER_DIV4_CLOCK ((unsigned int) 0x3 << 0) /* (TC) MCK/128 */ |
||||
#define AT91C_TC_SLOW_CLOCK ((unsigned int) 0x4 << 0) /* (TC) SLOW CLK */ |
||||
#define AT91C_TC_XC0_CLOCK ((unsigned int) 0x5 << 0) /* (TC) XC0 */ |
||||
#define AT91C_TC_XC1_CLOCK ((unsigned int) 0x6 << 0) /* (TC) XC1 */ |
||||
#define AT91C_TC_XC2_CLOCK ((unsigned int) 0x7 << 0) /* (TC) XC2 */ |
||||
#define AT91C_TCB_TC0XC0S_NONE ((unsigned int) 0x1) /* (TCB) None signal connected to XC0 */ |
||||
#define AT91C_TCB_TC1XC1S_NONE ((unsigned int) 0x1 << 2) /* (TCB) None signal connected to XC1 */ |
||||
#define AT91C_TCB_TC2XC2S_NONE ((unsigned int) 0x1 << 4) /* (TCB) None signal connected to XC2 */ |
||||
#define AT91C_TC_CLKDIS ((unsigned int) 0x1 << 1) /* (TC) Counter Clock Disable Command */ |
||||
#define AT91C_TC_SWTRG ((unsigned int) 0x1 << 2) /* (TC) Software Trigger Command */ |
||||
#define AT91C_TC_CLKEN ((unsigned int) 0x1 << 0) /* (TC) Counter Clock Enable Command */ |
||||
|
||||
#define AT91C_EMAC_BNQ ((unsigned int) 0x1 << 4) /* (EMAC) */ |
||||
#define AT91C_EMAC_COMP ((unsigned int) 0x1 << 5) /* (EMAC) */ |
||||
#define AT91C_EMAC_REC ((unsigned int) 0x1 << 1) /* (EMAC) */ |
||||
#define AT91C_EMAC_RE ((unsigned int) 0x1 << 2) /* (EMAC) Receive enable. */ |
||||
#define AT91C_EMAC_TE ((unsigned int) 0x1 << 3) /* (EMAC) Transmit enable. */ |
||||
#define AT91C_EMAC_CLK ((unsigned int) 0x3 << 10) /* (EMAC) */ |
||||
#define AT91C_EMAC_RMII ((unsigned int) 0x1 << 13) /* (EMAC) */ |
||||
#define AT91C_EMAC_NBC ((unsigned int) 0x1 << 5) /* (EMAC) No broadcast. */ |
||||
#define AT91C_EMAC_CAF ((unsigned int) 0x1 << 4) /* (EMAC) Copy all frames. */ |
||||
#define AT91C_EMAC_BNA ((unsigned int) 0x1 << 0) /* (EMAC) */ |
||||
#define AT91C_EMAC_REC ((unsigned int) 0x1 << 1) /* (EMAC) */ |
||||
#define AT91C_EMAC_RSR_OVR ((unsigned int) 0x1 << 2) /* (EMAC) */ |
||||
#define AT91C_EMAC_CSR ((unsigned int) 0x1 << 5) /* (EMAC) Clear statistics registers. */ |
||||
#define AT91C_EMAC_SPD ((unsigned int) 0x1 << 0) /* (EMAC) Speed. */ |
||||
#define AT91C_EMAC_FD ((unsigned int) 0x1 << 1) /* (EMAC) Full duplex. */ |
||||
#define AT91C_EMAC_LINK ((unsigned int) 0x1 << 0) /* (EMAC) */ |
||||
#define AT91C_EMAC_MPE ((unsigned int) 0x1 << 4) /* (EMAC) Management port enable. */ |
||||
#define AT91C_PIO_PA16 ((unsigned int) 1 << 16) /* Pin Controlled by PA16 */ |
||||
#define AT91C_PA16_EMDIO ((unsigned int) AT91C_PIO_PA16) /* Ethernet MAC Management Data Input/Output */ |
||||
#define AT91C_PIO_PA15 ((unsigned int) 1 << 15) /* Pin Controlled by PA15 */ |
||||
#define AT91C_PA15_EMDC ((unsigned int) AT91C_PIO_PA15) /* Ethernet MAC Management Data Clock */ |
||||
#define AT91C_PIO_PA14 ((unsigned int) 1 << 14) /* Pin Controlled by PA14 */ |
||||
#define AT91C_PA14_ERXER ((unsigned int) AT91C_PIO_PA14) /* Ethernet MAC Receive Error */ |
||||
#define AT91C_PIO_PA13 ((unsigned int) 1 << 13) /* Pin Controlled by PA13 */ |
||||
#define AT91C_PA13_ERX1 ((unsigned int) AT91C_PIO_PA13) /* Ethernet MAC Receive Data 1 */ |
||||
#define AT91C_PIO_PA12 ((unsigned int) 1 << 12) /* Pin Controlled by PA12 */ |
||||
#define AT91C_PA12_ERX0 ((unsigned int) AT91C_PIO_PA12) /* Ethernet MAC Receive Data 0 */ |
||||
#define AT91C_PIO_PA11 ((unsigned int) 1 << 11) /* Pin Controlled by PA11 */ |
||||
#define AT91C_PA11_ECRS_ECRSDV ((unsigned int) AT91C_PIO_PA11) /* Ethernet MAC Carrier Sense/Carrier Sense and Data Valid */ |
||||
#define AT91C_PIO_PA10 ((unsigned int) 1 << 10) /* Pin Controlled by PA10 */ |
||||
#define AT91C_PA10_ETX1 ((unsigned int) AT91C_PIO_PA10) /* Ethernet MAC Transmit Data 1 */ |
||||
#define AT91C_PIO_PA9 ((unsigned int) 1 << 9) /* Pin Controlled by PA9 */ |
||||
#define AT91C_PA9_ETX0 ((unsigned int) AT91C_PIO_PA9) /* Ethernet MAC Transmit Data 0 */ |
||||
#define AT91C_PIO_PA8 ((unsigned int) 1 << 8) /* Pin Controlled by PA8 */ |
||||
#define AT91C_PA8_ETXEN ((unsigned int) AT91C_PIO_PA8) /* Ethernet MAC Transmit Enable */ |
||||
#define AT91C_PIO_PA7 ((unsigned int) 1 << 7) /* Pin Controlled by PA7 */ |
||||
#define AT91C_PA7_ETXCK_EREFCK ((unsigned int) AT91C_PIO_PA7) /* Ethernet MAC Transmit Clock/Reference Clock */ |
||||
#define AT91C_PIO_PB25 ((unsigned int) 1 << 25) /* Pin Controlled by PB25 */ |
||||
#define AT91C_PB25_DSR1 ((unsigned int) AT91C_PIO_PB25) /* USART 1 Data Set ready */ |
||||
#define AT91C_PB25_EF100 ((unsigned int) AT91C_PIO_PB25) /* Ethernet MAC Force 100 Mbits */ |
||||
#define AT91C_PIO_PB19 ((unsigned int) 1 << 19) /* Pin Controlled by PB19 */ |
||||
#define AT91C_PB19_DTR1 ((unsigned int) AT91C_PIO_PB19) /* USART 1 Data Terminal ready */ |
||||
#define AT91C_PB19_ERXCK ((unsigned int) AT91C_PIO_PB19) /* Ethernet MAC Receive Clock */ |
||||
#define AT91C_PIO_PB18 ((unsigned int) 1 << 18) /* Pin Controlled by PB18 */ |
||||
#define AT91C_PB18_RI1 ((unsigned int) AT91C_PIO_PB18) /* USART 1 Ring Indicator */ |
||||
#define AT91C_PB18_ECOL ((unsigned int) AT91C_PIO_PB18) /* Ethernet MAC Collision Detected */ |
||||
#define AT91C_PIO_PB17 ((unsigned int) 1 << 17) /* Pin Controlled by PB17 */ |
||||
#define AT91C_PB17_RF2 ((unsigned int) AT91C_PIO_PB17) /* SSC Receive Frame Sync 2 */ |
||||
#define AT91C_PB17_ERXDV ((unsigned int) AT91C_PIO_PB17) /* Ethernet MAC Receive Data Valid */ |
||||
#define AT91C_PIO_PB16 ((unsigned int) 1 << 16) /* Pin Controlled by PB16 */ |
||||
#define AT91C_PB16_RK2 ((unsigned int) AT91C_PIO_PB16) /* SSC Receive Clock 2 */ |
||||
#define AT91C_PB16_ERX3 ((unsigned int) AT91C_PIO_PB16) /* Ethernet MAC Receive Data 3 */ |
||||
#define AT91C_PIO_PB15 ((unsigned int) 1 << 15) /* Pin Controlled by PB15 */ |
||||
#define AT91C_PB15_RD2 ((unsigned int) AT91C_PIO_PB15) /* SSC Receive Data 2 */ |
||||
#define AT91C_PB15_ERX2 ((unsigned int) AT91C_PIO_PB15) /* Ethernet MAC Receive Data 2 */ |
||||
#define AT91C_PIO_PB14 ((unsigned int) 1 << 14) /* Pin Controlled by PB14 */ |
||||
#define AT91C_PB14_TD2 ((unsigned int) AT91C_PIO_PB14) /* SSC Transmit Data 2 */ |
||||
#define AT91C_PB14_ETXER ((unsigned int) AT91C_PIO_PB14) /* Ethernet MAC Transmikt Coding Error */ |
||||
#define AT91C_PIO_PB13 ((unsigned int) 1 << 13) /* Pin Controlled by PB13 */ |
||||
#define AT91C_PB13_TK2 ((unsigned int) AT91C_PIO_PB13) /* SSC Transmit Clock 2 */ |
||||
#define AT91C_PB13_ETX3 ((unsigned int) AT91C_PIO_PB13) /* Ethernet MAC Transmit Data 3 */ |
||||
#define AT91C_PIO_PB12 ((unsigned int) 1 << 12) /* Pin Controlled by PB12 */ |
||||
#define AT91C_PB12_TF2 ((unsigned int) AT91C_PIO_PB12) /* SSC Transmit Frame Sync 2 */ |
||||
#define AT91C_PB12_ETX2 ((unsigned int) AT91C_PIO_PB12) /* Ethernet MAC Transmit Data 2 */ |
||||
|
||||
#define AT91C_PIOB_BSR ((AT91_REG *) 0xFFFFF674) /* (PIOB) Select B Register */ |
||||
#define AT91C_BASE_EMAC ((AT91PS_EMAC) 0xFFFBC000) /* (EMAC) Base Address */ |
||||
#define AT91C_PIOB_PDR ((AT91_REG *) 0xFFFFF604) /* (PIOB) PIO Disable Register */ |
||||
|
||||
#define AT91C_EBI_CS3A_SMC_SmartMedia ((unsigned int) 0x1 << 3) /* (EBI) Chip Select 3 is assigned to the Static Memory Controller and the SmartMedia Logic is activated. */ |
||||
#define AT91C_SMC2_ACSS_STANDARD ((unsigned int) 0x0 << 16) /* (SMC2) Standard, asserted at the beginning of the access and deasserted at the end. */ |
||||
#define AT91C_SMC2_DBW_8 ((unsigned int) 0x2 << 13) /* (SMC2) 8-bit. */ |
||||
#define AT91C_SMC2_WSEN ((unsigned int) 0x1 << 7) /* (SMC2) Wait State Enable */ |
||||
#define AT91C_PIOC_ASR ((AT91_REG *) 0xFFFFF870) /* (PIOC) Select A Register */ |
||||
|
||||
#define AT91C_BASE_TC0 ((AT91PS_TC) 0xFFFA0000) /* (TC0) Base Address */ |
||||
#define AT91C_BASE_DBGU ((AT91PS_DBGU) 0xFFFFF200) /* (DBGU) Base Address */ |
||||
#define AT91C_BASE_PIOA ((AT91PS_PIO) 0xFFFFF400) /* (PIOA) Base Address */ |
||||
#define AT91C_EBI_CSA ((AT91_REG *) 0xFFFFFF60) /* (EBI) Chip Select Assignment Register */ |
||||
#define AT91C_BASE_SMC2 ((AT91PS_SMC2) 0xFFFFFF70) /* (SMC2) Base Address */ |
||||
#define AT91C_BASE_US1 ((AT91PS_USART) 0xFFFC4000) /* (US1) Base Address */ |
||||
#define AT91C_TCB0_BMR ((AT91_REG *) 0xFFFA00C4) /* (TCB0) TC Block Mode Register */ |
||||
#define AT91C_TCB0_BCR ((AT91_REG *) 0xFFFA00C0) /* (TCB0) TC Block Control Register */ |
||||
#define AT91C_PIOC_PDR ((AT91_REG *) 0xFFFFF804) /* (PIOC) PIO Disable Register */ |
||||
#define AT91C_PIOC_PER ((AT91_REG *) 0xFFFFF800) /* (PIOC) PIO Enable Register */ |
||||
#define AT91C_PIOC_ODR ((AT91_REG *) 0xFFFFF814) /* (PIOC) Output Disable Registerr */ |
||||
#define AT91C_PIOB_PER ((AT91_REG *) 0xFFFFF600) /* (PIOB) PIO Enable Register */ |
||||
#define AT91C_PIOB_ODR ((AT91_REG *) 0xFFFFF614) /* (PIOB) Output Disable Registerr */ |
||||
#define AT91C_PIOB_PDSR ((AT91_REG *) 0xFFFFF63C) /* (PIOB) Pin Data Status Register */ |
||||
#endif |
@ -0,0 +1,55 @@ |
||||
/*
|
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
/*
|
||||
* NAND support |
||||
*/ |
||||
#ifndef _CMD_NAND_H |
||||
#define _CMD_NAND_H |
||||
|
||||
#include <common.h> |
||||
#include <command.h> |
||||
|
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_NAND) |
||||
#define CMD_TBL_NAND MK_CMD_TBL_ENTRY( \ |
||||
"nand", 3, 5, 1, do_nand, \
|
||||
"nand - NAND sub-system\n", \
|
||||
"info - show available NAND devices\n" \
|
||||
"nand device [dev] - show or set current device\n" \
|
||||
"nand read addr off size\n" \
|
||||
"nand write addr off size - read/write `size'" \
|
||||
" bytes starting at offset `off'\n" \
|
||||
" to/from memory address `addr'\n" \
|
||||
"nand erase off size - erase `size' bytes of NAND from offset `off'\n" \
|
||||
), |
||||
|
||||
#define CMD_TBL_NANDBOOT MK_CMD_TBL_ENTRY( \ |
||||
"nboot", 4, 4, 1, do_nandboot, \
|
||||
"nboot - boot from NAND device\n", \
|
||||
"loadAddr dev\n" \
|
||||
), |
||||
|
||||
int do_nand (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); |
||||
int do_nandboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); |
||||
|
||||
#else |
||||
#define CMD_TBL_NAND |
||||
#define CMD_TBL_NANDBOOT |
||||
#endif |
||||
|
||||
#endif /* _CMD_NAND_H */ |
@ -0,0 +1,153 @@ |
||||
/*
|
||||
* Rick Bronson <rick@efn.org> |
||||
* |
||||
* Configuation settings for the AT91RM9200DK board. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/* ARM asynchronous clock */ |
||||
#define AT91C_MAIN_CLOCK 179712000 /* from 18.432 MHz crystal (18432000 / 4 * 39) */ |
||||
#define AT91C_MASTER_CLOCK 59904000 /* peripheral clock (AT91C_MASTER_CLOCK / 3) */ |
||||
|
||||
#define CONFIG_AT91RM9200DK 1 /* on an AT91RM9200DK Board */ |
||||
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ |
||||
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ |
||||
#define CONFIG_SETUP_MEMORY_TAGS 1 |
||||
#define CONFIG_INITRD_TAG 1 |
||||
/*
|
||||
* Size of malloc() pool |
||||
*/ |
||||
#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) |
||||
#define CONFIG_BAUDRATE 115200 |
||||
/*
|
||||
* Hardware drivers |
||||
*/ |
||||
|
||||
/*
|
||||
* select serial console configuration |
||||
*/ |
||||
#define CONFIG_SERIAL3 1 /* we use SERIAL 3 */ |
||||
|
||||
#undef CONFIG_HWFLOW /* don't include RTS/CTS flow control support */ |
||||
|
||||
#undef CONFIG_MODEM_SUPPORT /* disable modem initialization stuff */ |
||||
|
||||
#define CONFIG_COMMANDS \ |
||||
(CONFIG_CMD_DFL | \
|
||||
CFG_CMD_DHCP | \
|
||||
CFG_CMD_NAND ) |
||||
/* CFG_CMD_EEPROM | \ might consider these
|
||||
CFG_CMD_I2C | \
|
||||
CFG_CMD_USB | \
|
||||
CFG_CMD_MII | \
|
||||
CFG_CMD_SDRAM | \ */ |
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ |
||||
#include <cmd_confdefs.h> |
||||
|
||||
#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ |
||||
#define SECTORSIZE 512 |
||||
|
||||
#define ADDR_COLUMN 1 |
||||
#define ADDR_PAGE 2 |
||||
#define ADDR_COLUMN_PAGE 3 |
||||
|
||||
#define NAND_ChipID_UNKNOWN 0x00 |
||||
#define NAND_MAX_FLOORS 1 |
||||
#define NAND_MAX_CHIPS 1 |
||||
|
||||
#define AT91_SMART_MEDIA_ALE (1 << 22) /* our ALE is AD22 */ |
||||
#define AT91_SMART_MEDIA_CLE (1 << 21) /* our CLE is AD21 */ |
||||
|
||||
#define NAND_DISABLE_CE(nand) do { *AT91C_PIOC_SODR = AT91C_PIO_PC0;} while(0) |
||||
#define NAND_ENABLE_CE(nand) do { *AT91C_PIOC_CODR = AT91C_PIO_PC0;} while(0) |
||||
|
||||
#define NAND_WAIT_READY(nand) while (!(*AT91C_PIOC_PDSR & AT91C_PIO_PC2)) |
||||
|
||||
#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | AT91_SMART_MEDIA_CLE) = (__u8)(d); } while(0) |
||||
#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | AT91_SMART_MEDIA_ALE) = (__u8)(d); } while(0) |
||||
#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0) |
||||
#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr)) |
||||
/* the following are NOP's in our implementation */ |
||||
#define NAND_CTL_CLRALE(nandptr) |
||||
#define NAND_CTL_SETALE(nandptr) |
||||
#define NAND_CTL_CLRCLE(nandptr) |
||||
#define NAND_CTL_SETCLE(nandptr) |
||||
|
||||
#define CONFIG_NR_DRAM_BANKS 1 |
||||
#define PHYS_SDRAM 0x20000000 |
||||
#define PHYS_SDRAM_SIZE 0x2000000 /* 32 megs */ |
||||
|
||||
#define CFG_MEMTEST_START PHYS_SDRAM |
||||
#define CFG_MEMTEST_END CFG_MEMTEST_START + PHYS_SDRAM_SIZE - 262144 |
||||
|
||||
#define CONFIG_DRIVER_ETHER |
||||
|
||||
#define PHYS_FLASH_1 0x10000000 |
||||
#define PHYS_FLASH_SIZE 0x200000 /* 2 megs main flash */ |
||||
#define CFG_FLASH_BASE PHYS_FLASH_1 |
||||
#define CFG_MAX_FLASH_BANKS 1 |
||||
#define CFG_MAX_FLASH_SECT 40 |
||||
#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */ |
||||
#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */ |
||||
#define CFG_ENV_IS_IN_FLASH 1 |
||||
#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0xe000) |
||||
#define CFG_ENV_SIZE 0x2000 |
||||
#define CFG_LOAD_ADDR 0x21000000 /* default load address */ |
||||
|
||||
#define CFG_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 } |
||||
|
||||
#define CFG_PROMPT "Uboot> " /* Monitor Command Prompt */ |
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#define CFG_MAXARGS 16 /* max number of command args */ |
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
||||
|
||||
#ifndef __ASSEMBLY__ |
||||
/*-----------------------------------------------------------------------
|
||||
* Board specific extension for bd_info |
||||
* |
||||
* This structure is embedded in the global bd_info (bd_t) structure |
||||
* and can be used by the board specific code (eg board/...) |
||||
*/ |
||||
|
||||
struct bd_info_ext |
||||
{ |
||||
/* helper variable for board environment handling
|
||||
* |
||||
* env_crc_valid == 0 => uninitialised |
||||
* env_crc_valid > 0 => environment crc in flash is valid |
||||
* env_crc_valid < 0 => environment crc in flash is invalid |
||||
*/ |
||||
int env_crc_valid; |
||||
}; |
||||
#endif |
||||
|
||||
#define CFG_HZ AT91C_MASTER_CLOCK/2 /* AT91C_TC0_CMR is implicitly set to |
||||
AT91C_TC_TIMER_DIV1_CLOCK */ |
||||
|
||||
#define CONFIG_STACKSIZE (32*1024) /* regular stack */ |
||||
|
||||
#ifdef CONFIG_USE_IRQ |
||||
#error CONFIG_USE_IRQ not supported |
||||
#endif |
||||
|
||||
#endif |
@ -0,0 +1,470 @@ |
||||
/*
|
||||
* (C) Copyright 2000, 2001, 2002 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
/*
|
||||
* board/config.h - configuration options, board specific, |
||||
* for SinoVee Microsystems SC8xx series SBC |
||||
* http://www.fel.com.cn (Chinese)
|
||||
* http://www.sinovee.com (English)
|
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/* Custom configuration */ |
||||
/* SC823,SC850,SC860SAR, FEL8xx-AT(823/850/860) */ |
||||
/* SC85T,SC860T, FEL8xx-AT(855T/860T) */ |
||||
/*#define CONFIG_FEL8xx_AT */ |
||||
/*#define CONFIG_LCD */ |
||||
/* if core > 50MHz , un-comment CONFIG_BUS_DIV2 */ |
||||
/* #define CONFIG_50MHz */ |
||||
/* #define CONFIG_66MHz */ |
||||
/* #define CONFIG_75MHz */ |
||||
#define CONFIG_80MHz |
||||
/*#define CONFIG_100MHz */ |
||||
/* #define CONFIG_BUS_DIV2 1 */ |
||||
/* for BOOT device port size */ |
||||
/* #define CONFIG_BOOT_8B */ |
||||
#define CONFIG_BOOT_16B |
||||
/* #define CONFIG_BOOT_32B */ |
||||
/* #define CONFIG_CAN_DRIVER */ |
||||
/* #define DEBUG */ |
||||
#define CONFIG_FEC_ENET |
||||
|
||||
/* #define CONFIG_SDRAM_16M */ |
||||
#define CONFIG_SDRAM_32M |
||||
/* #define CONFIG_SDRAM_64M */ |
||||
#define CFG_RESET_ADDRESS 0xffffffff |
||||
/*
|
||||
* High Level Configuration Options |
||||
* (easy to change) |
||||
*/ |
||||
|
||||
/* #define CONFIG_MPC823 1 */ |
||||
/* #define CONFIG_MPC850 1 */ |
||||
#define CONFIG_MPC855 1 |
||||
/* #define CONFIG_MPC860 1 */ |
||||
/* #define CONFIG_MPC860T 1 */ |
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog */ |
||||
|
||||
#define CONFIG_SVM_SC8xx 1 /* ...on SVM SC8xx series */ |
||||
|
||||
#ifdef CONFIG_LCD /* with LCD controller ? */ |
||||
/* #define CONFIG_NEC_NL6648BC20 1 / * use NEC NL6648BC20 display */ |
||||
#endif |
||||
|
||||
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ |
||||
#undef CONFIG_8xx_CONS_SMC2 |
||||
#undef CONFIG_8xx_CONS_NONE |
||||
#define CONFIG_BAUDRATE 19200 /* console baudrate = 115kbps */ |
||||
#if 0 |
||||
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ |
||||
#else |
||||
#define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ |
||||
#endif |
||||
|
||||
#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ |
||||
|
||||
#define CONFIG_BOARD_TYPES 1 /* support board types */ |
||||
|
||||
#define CONFIG_PREBOOT "echo;echo Welcome to U-Boot SVM port;echo;echo Type \"? or help\" to get on-line help;echo" |
||||
|
||||
#undef CONFIG_BOOTARGS |
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"nfsargs=setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=$(serverip):$(rootpath)\0" \
|
||||
"ramargs=setenv bootargs root=/dev/ram rw\0" \
|
||||
"addip=setenv bootargs $(bootargs) " \
|
||||
"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
|
||||
":$(hostname):$(netdev):off panic=1\0" \
|
||||
"flash_nfs=run nfsargs addip;" \
|
||||
"bootm $(kernel_addr)\0" \
|
||||
"flash_self=run ramargs addip;" \
|
||||
"bootm $(kernel_addr) $(ramdisk_addr)\0" \
|
||||
"net_nfs=tftp 0x210000 $(bootfile);run nfsargs addip;bootm\0" \
|
||||
"rootpath=/opt/sinovee/ppc8xx-linux-2.0/target\0" \
|
||||
"bootfile=pImage-sc855t\0" \
|
||||
"kernel_addr=48000000\0" \
|
||||
"ramdisk_addr=48100000\0" \
|
||||
"" |
||||
#define CONFIG_BOOTCOMMAND \ |
||||
"setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
|
||||
"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \
|
||||
"tftpboot 0x210000 pImage-sc855t;bootm 0x210000" |
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
||||
#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ |
||||
|
||||
|
||||
#ifdef CONFIG_LCD |
||||
# undef CONFIG_STATUS_LED /* disturbs display */ |
||||
#else |
||||
# define CONFIG_STATUS_LED 1 /* Status LED enabled */ |
||||
#endif /* CONFIG_LCD */ |
||||
|
||||
#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ |
||||
|
||||
#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) |
||||
|
||||
#define CONFIG_MAC_PARTITION |
||||
#define CONFIG_DOS_PARTITION |
||||
|
||||
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ |
||||
|
||||
#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ |
||||
CFG_CMD_ASKENV | \
|
||||
CFG_CMD_DHCP | \
|
||||
CFG_CMD_DOC | \
|
||||
/* CFG_CMD_IDE |*/ \
|
||||
CFG_CMD_DATE ) |
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ |
||||
#include <cmd_confdefs.h> |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CFG_LONGHELP /* undef to save memory */ |
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */ |
||||
|
||||
#ifdef CFG_HUSH_PARSER |
||||
#define CFG_PROMPT_HUSH_PS2 "> " |
||||
#endif |
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#else |
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#endif |
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CFG_MAXARGS 16 /* max number of command args */ |
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
||||
|
||||
#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ |
||||
#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ |
||||
|
||||
#define CFG_LOAD_ADDR 0x100000 /* default load address */ |
||||
|
||||
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ |
||||
|
||||
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
||||
|
||||
/*
|
||||
* Low Level Configuration Settings |
||||
* (address mappings, register initial values, etc.) |
||||
* You should know what you are doing if you make changes here. |
||||
*/ |
||||
/*-----------------------------------------------------------------------
|
||||
* Internal Memory Mapped Register |
||||
*/ |
||||
#define CFG_IMMR 0xFF000000 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area (in DPRAM) |
||||
*/ |
||||
#define CFG_INIT_RAM_ADDR CFG_IMMR |
||||
#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ |
||||
#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ |
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration |
||||
* (Set up by the startup code) |
||||
* Please note that CFG_SDRAM_BASE _must_ start at 0 |
||||
*/ |
||||
#define CFG_SDRAM_BASE 0x00000000 |
||||
#define CFG_FLASH_BASE 0x40000000 |
||||
#define CFG_MONITOR_LEN (384 << 10) /* Reserve 192 kB for Monitor */ |
||||
#define CFG_MONITOR_BASE CFG_FLASH_BASE |
||||
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 8 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization. |
||||
*/ |
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization |
||||
*/ |
||||
#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ |
||||
#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ |
||||
|
||||
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
||||
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ |
||||
|
||||
#define CFG_ENV_IS_IN_FLASH 1 |
||||
|
||||
#ifdef CONFIG_BOOT_8B |
||||
#define CFG_ENV_OFFSET 0x10000 /* Offset of Environment Sector */ |
||||
#define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */ |
||||
#elif defined (CONFIG_BOOT_16B) |
||||
#define CFG_ENV_OFFSET 0x10000 /* Offset of Environment Sector */ |
||||
#define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */ |
||||
#elif defined (CONFIG_BOOT_32B) |
||||
#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ |
||||
#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ |
||||
#endif |
||||
|
||||
/* Address and size of Redundant Environment Sector */ |
||||
#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE) |
||||
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) |
||||
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Hardware Information Block |
||||
*/ |
||||
#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ |
||||
#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */ |
||||
#define CFG_HWINFO_MAGIC 0x46454C38 /* 'SVM8' */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration |
||||
*/ |
||||
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SYPCR - System Protection Control 11-9 |
||||
* SYPCR can only be written once after reset! |
||||
*----------------------------------------------------------------------- |
||||
* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze |
||||
*/ |
||||
#if defined(CONFIG_WATCHDOG) |
||||
/*#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
|
||||
SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) |
||||
*/ |
||||
#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_SWF | \ |
||||
SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) |
||||
#else |
||||
#define CFG_SYPCR 0xffffff88 |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SIUMCR - SIU Module Configuration 11-6 |
||||
*----------------------------------------------------------------------- |
||||
* PCMCIA config., multi-function pin tri-state |
||||
*/ |
||||
#ifndef CONFIG_CAN_DRIVER |
||||
/*#define CFG_SIUMCR 0x00610c00 */ |
||||
#define CFG_SIUMCR 0x00000000 |
||||
#else /* we must activate GPL5 in the SIUMCR for CAN */ |
||||
#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) |
||||
#endif /* CONFIG_CAN_DRIVER */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* TBSCR - Time Base Status and Control 11-26 |
||||
*----------------------------------------------------------------------- |
||||
* Clear Reference Interrupt Status, Timebase freezing enabled |
||||
*/ |
||||
#define CFG_TBSCR 0x0001 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* RTCSC - Real-Time Clock Status and Control Register 11-27 |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
#define CFG_RTCSC 0x00c3 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PISCR - Periodic Interrupt Status and Control 11-31 |
||||
*----------------------------------------------------------------------- |
||||
* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled |
||||
*/ |
||||
#define CFG_PISCR 0x0000 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 |
||||
*----------------------------------------------------------------------- |
||||
* Reset PLL lock status sticky bit, timer expired status bit and timer |
||||
* interrupt status bit |
||||
*/ |
||||
#if defined (CONFIG_100MHz) |
||||
#define CFG_PLPRCR 0x06301000 |
||||
#define CONFIG_8xx_GCLK_FREQ 100000000 |
||||
#elif defined (CONFIG_80MHz) |
||||
#define CFG_PLPRCR 0x04f01000 |
||||
#define CONFIG_8xx_GCLK_FREQ 80000000 |
||||
#elif defined(CONFIG_75MHz) |
||||
#define CFG_PLPRCR 0x04a00100 |
||||
#define CONFIG_8xx_GCLK_FREQ 75000000 |
||||
#elif defined(CONFIG_66MHz) |
||||
#define CFG_PLPRCR 0x04101000 |
||||
#define CONFIG_8xx_GCLK_FREQ 66000000 |
||||
#elif defined(CONFIG_50MHz) |
||||
#define CFG_PLPRCR 0x03101000 |
||||
#define CONFIG_8xx_GCLK_FREQ 50000000 |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SCCR - System Clock and reset Control Register 15-27 |
||||
*----------------------------------------------------------------------- |
||||
* Set clock output, timebase and RTC source and divider, |
||||
* power management and some other internal clocks |
||||
*/ |
||||
#define SCCR_MASK SCCR_EBDF11 |
||||
#ifdef CONFIG_BUS_DIV2 |
||||
#define CFG_SCCR 0x02020000 | SCCR_RTSEL |
||||
#else /* up to 50 MHz we use a 1:1 clock */ |
||||
#define CFG_SCCR 0x02000000 | SCCR_RTSEL |
||||
#endif |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PCMCIA stuff |
||||
*----------------------------------------------------------------------- |
||||
* |
||||
*/ |
||||
#define CFG_PCMCIA_MEM_ADDR (0xE0000000) |
||||
#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) |
||||
#define CFG_PCMCIA_DMA_ADDR (0xE4000000) |
||||
#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) |
||||
#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) |
||||
#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) |
||||
#define CFG_PCMCIA_IO_ADDR (0xEC000000) |
||||
#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) |
||||
*----------------------------------------------------------------------- |
||||
*/ |
||||
|
||||
#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ |
||||
|
||||
#define CONFIG_IDE_8xx_DIRECT 1 /* Direct IDE not supported */ |
||||
#undef CONFIG_IDE_LED /* LED for ide not supported */ |
||||
#undef CONFIG_IDE_RESET /* reset for ide not supported */ |
||||
|
||||
#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ |
||||
#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ |
||||
|
||||
#define CFG_ATA_BASE_ADDR 0xFE100010 |
||||
#define CFG_ATA_IDE0_OFFSET 0x0000 |
||||
/*#define CFG_ATA_IDE1_OFFSET 0x0C00 */ |
||||
#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O |
||||
*/ |
||||
#define CFG_ATA_REG_OFFSET 0x0200 /* Offset for normal register accesses |
||||
*/ |
||||
#define CFG_ATA_ALT_OFFSET 0x0210 /* Offset for alternate registers |
||||
*/ |
||||
#define CONFIG_ATAPI |
||||
#define CFG_PIO_MODE 0 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* |
||||
*----------------------------------------------------------------------- |
||||
* |
||||
*/ |
||||
/*#define CFG_DER 0x2002000F*/ |
||||
#define CFG_DER 0x0 |
||||
|
||||
/*
|
||||
* Init Memory Controller: |
||||
* |
||||
* BR0/1 and OR0/1 (FLASH) |
||||
*/ |
||||
|
||||
#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ |
||||
#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ |
||||
|
||||
/* used to re-map FLASH both when starting from SRAM or FLASH:
|
||||
* restrict access enough to keep SRAM working (if any) |
||||
* but not too much to meddle with FLASH accesses |
||||
*/ |
||||
#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ |
||||
#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ |
||||
|
||||
/*
|
||||
* FLASH timing: |
||||
*/ |
||||
#if defined(CONFIG_100MHz) |
||||
#define CFG_OR_TIMING_FLASH 0x000002f4 |
||||
#define CFG_OR_TIMING_DOC 0x000002f4 |
||||
#define CFG_MxMR_PTx 0x61000000 |
||||
#define CFG_MPTPR 0x400 |
||||
|
||||
#elif defined(CONFIG_80MHz) |
||||
#define CFG_OR_TIMING_FLASH 0x00000ff4 |
||||
#define CFG_OR_TIMING_DOC 0x000001f4 |
||||
#define CFG_MxMR_PTx 0x4e000000 |
||||
#define CFG_MPTPR 0x400 |
||||
|
||||
#elif defined(CONFIG_75MHz) |
||||
#define CFG_OR_TIMING_FLASH 0x000008f4 |
||||
#define CFG_OR_TIMING_DOC 0x000002f4 |
||||
#define CFG_MxMR_PTx 0x49000000 |
||||
#define CFG_MPTPR 0x400 |
||||
|
||||
#elif defined(CONFIG_66MHz) |
||||
#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ |
||||
OR_SCY_3_CLK | OR_EHTR | OR_BI) |
||||
/*#define CFG_OR_TIMING_FLASH 0x000001f4 */ |
||||
#define CFG_OR_TIMING_DOC 0x000003f4 |
||||
#define CFG_MxMR_PTx 0x40000000 |
||||
#define CFG_MPTPR 0x400 |
||||
|
||||
#else /* 50 MHz */ |
||||
#define CFG_OR_TIMING_FLASH 0x00000ff4 |
||||
#define CFG_OR_TIMING_DOC 0x000001f4 |
||||
#define CFG_MxMR_PTx 0x30000000 |
||||
#define CFG_MPTPR 0x400 |
||||
#endif /*CONFIG_??MHz */ |
||||
|
||||
|
||||
#if defined (CONFIG_BOOT_8B) /* 512K X 8 ,29F040 , 2MB space */ |
||||
#define CFG_OR0_PRELIM (0xffe00000 | CFG_OR_TIMING_FLASH) |
||||
#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V | BR_PS_8) |
||||
#elif defined (CONFIG_BOOT_16B) /* 29lv160 X 16 , 4MB space */ |
||||
#define CFG_OR0_PRELIM (0xffc00000 | CFG_OR_TIMING_FLASH) |
||||
#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V | BR_PS_16) |
||||
#elif defined( CONFIG_BOOT_32B ) /* 29lv160 X 2 X 32, 4/8/16MB , 64MB space */ |
||||
#define CFG_OR0_PRELIM (0xfc000000 | CFG_OR_TIMING_FLASH) |
||||
#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) |
||||
#else |
||||
#error Boot device port size missing. |
||||
#endif |
||||
|
||||
/*
|
||||
* Disk-On-Chip configuration |
||||
*/ |
||||
|
||||
#define CFG_DOC_SHORT_TIMEOUT |
||||
#define CFG_MAX_DOC_DEVICE 1 /* Max number of DOC devices */ |
||||
|
||||
#define CFG_DOC_SUPPORT_2000 |
||||
#define CFG_DOC_SUPPORT_MILLENNIUM |
||||
#define CFG_DOC_BASE 0x80000000 |
||||
|
||||
|
||||
/*
|
||||
* Internal Definitions |
||||
* |
||||
* Boot Flags |
||||
*/ |
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */ |
||||
|
||||
#endif /* __CONFIG_H */ |
Loading…
Reference in new issue