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@ -52,6 +52,13 @@ |
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#define SDHCI_CDNS_PHY_DLY_HSMMC 0x0c |
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#define SDHCI_CDNS_PHY_DLY_STROBE 0x0d |
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/*
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* The tuned val register is 6 bit-wide, but not the whole of the range is |
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* available. The range 0-42 seems to be available (then 43 wraps around to 0) |
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* but I am not quite sure if it is official. Use only 0 to 39 for safety. |
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*/ |
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#define SDHCI_CDNS_MAX_TUNING_LOOP 40 |
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struct sdhci_cdns_plat { |
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struct mmc_config cfg; |
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struct mmc mmc; |
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@ -135,20 +142,18 @@ static void sdhci_cdns_set_control_reg(struct sdhci_host *host) |
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* The mode should be decided by MMC_TIMING_* like Linux, but |
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* U-Boot does not support timing. Use the clock frequency instead. |
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*/ |
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if (clock <= 26000000) |
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if (clock <= 26000000) { |
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mode = SDHCI_CDNS_HRS06_MODE_SD; /* use this for Legacy */ |
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else if (clock <= 52000000) { |
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} else if (clock <= 52000000) { |
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if (mmc->ddr_mode) |
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mode = SDHCI_CDNS_HRS06_MODE_MMC_DDR; |
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else |
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mode = SDHCI_CDNS_HRS06_MODE_MMC_SDR; |
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} else { |
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/*
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* REVISIT: |
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* The IP supports HS200/HS400, revisit once U-Boot support it |
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*/ |
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printf("unsupported frequency %d\n", clock); |
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return; |
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if (mmc->ddr_mode) |
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mode = SDHCI_CDNS_HRS06_MODE_MMC_HS400; |
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else |
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mode = SDHCI_CDNS_HRS06_MODE_MMC_HS200; |
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} |
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tmp = readl(plat->hrs_addr + SDHCI_CDNS_HRS06); |
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@ -161,6 +166,69 @@ static const struct sdhci_ops sdhci_cdns_ops = { |
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.set_control_reg = sdhci_cdns_set_control_reg, |
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}; |
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static int sdhci_cdns_set_tune_val(struct sdhci_cdns_plat *plat, |
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unsigned int val) |
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{ |
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void __iomem *reg = plat->hrs_addr + SDHCI_CDNS_HRS06; |
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u32 tmp; |
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if (WARN_ON(!FIELD_FIT(SDHCI_CDNS_HRS06_TUNE, val))) |
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return -EINVAL; |
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tmp = readl(reg); |
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tmp &= ~SDHCI_CDNS_HRS06_TUNE; |
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tmp |= FIELD_PREP(SDHCI_CDNS_HRS06_TUNE, val); |
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tmp |= SDHCI_CDNS_HRS06_TUNE_UP; |
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writel(tmp, reg); |
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return readl_poll_timeout(reg, tmp, !(tmp & SDHCI_CDNS_HRS06_TUNE_UP), |
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1); |
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} |
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static int __maybe_unused sdhci_cdns_execute_tuning(struct udevice *dev, |
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unsigned int opcode) |
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{ |
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struct sdhci_cdns_plat *plat = dev_get_platdata(dev); |
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struct mmc *mmc = &plat->mmc; |
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int cur_streak = 0; |
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int max_streak = 0; |
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int end_of_streak = 0; |
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int i; |
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/*
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* This handler only implements the eMMC tuning that is specific to |
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* this controller. The tuning for SD timing should be handled by the |
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* SDHCI core. |
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*/ |
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if (!IS_MMC(mmc)) |
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return -ENOTSUPP; |
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if (WARN_ON(opcode != MMC_CMD_SEND_TUNING_BLOCK_HS200)) |
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return -EINVAL; |
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for (i = 0; i < SDHCI_CDNS_MAX_TUNING_LOOP; i++) { |
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if (sdhci_cdns_set_tune_val(plat, i) || |
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mmc_send_tuning(mmc, opcode, NULL)) { /* bad */ |
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cur_streak = 0; |
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} else { /* good */ |
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cur_streak++; |
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if (cur_streak > max_streak) { |
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max_streak = cur_streak; |
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end_of_streak = i; |
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} |
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} |
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} |
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if (!max_streak) { |
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dev_err(dev, "no tuning point found\n"); |
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return -EIO; |
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} |
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return sdhci_cdns_set_tune_val(plat, end_of_streak - max_streak / 2); |
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} |
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static struct dm_mmc_ops sdhci_cdns_mmc_ops; |
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static int sdhci_cdns_bind(struct udevice *dev) |
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{ |
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struct sdhci_cdns_plat *plat = dev_get_platdata(dev); |
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@ -189,6 +257,10 @@ static int sdhci_cdns_probe(struct udevice *dev) |
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host->ioaddr = plat->hrs_addr + SDHCI_CDNS_SRS_BASE; |
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host->ops = &sdhci_cdns_ops; |
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host->quirks |= SDHCI_QUIRK_WAIT_SEND_CMD; |
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sdhci_cdns_mmc_ops = sdhci_ops; |
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#ifdef MMC_SUPPORTS_TUNING |
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sdhci_cdns_mmc_ops.execute_tuning = sdhci_cdns_execute_tuning; |
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#endif |
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ret = mmc_of_parse(dev, &plat->cfg); |
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if (ret) |
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@ -223,5 +295,5 @@ U_BOOT_DRIVER(sdhci_cdns) = { |
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.probe = sdhci_cdns_probe, |
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.priv_auto_alloc_size = sizeof(struct sdhci_host), |
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.platdata_auto_alloc_size = sizeof(struct sdhci_cdns_plat), |
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.ops = &sdhci_ops, |
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.ops = &sdhci_cdns_mmc_ops, |
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}; |
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