diff --git a/cpu/mcf5227x/start.S b/cpu/mcf5227x/start.S
index 0c9c89c..30428f1 100644
--- a/cpu/mcf5227x/start.S
+++ b/cpu/mcf5227x/start.S
@@ -24,16 +24,12 @@
 #include <config.h>
 #include <timestamp.h>
 #include "version.h"
+#include <asm/cache.h>
 
 #ifndef	 CONFIG_IDENT_STRING
 #define	 CONFIG_IDENT_STRING ""
 #endif
 
-/* last three long word reserved for cache status */
-#define ICACHE_STATUS	(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END- 4)
-#define DCACHE_STATUS	(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END- 8)
-#define CACR_STATUS	(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-12)
-
 #define _START	_start
 #define _FAULT	_fault
 
@@ -378,21 +374,19 @@ _start:
 	movec	%d0, %RAMBAR1
 #endif
 
+	/* invalidate and disable cache */
+	move.l	#CF_CACR_CINV, %d0	/* Invalidate cache cmd */
+	movec	%d0, %CACR		/* Invalidate cache */
+	move.l	#0, %d0
+	movec	%d0, %ACR0
+	movec	%d0, %ACR1
+
 	/* initialize general use internal ram */
 	move.l #0, %d0
 	move.l #(ICACHE_STATUS), %a1	/* icache */
 	move.l #(DCACHE_STATUS), %a2	/* icache */
-	move.l #(CACR_STATUS), %a3	/* CACR */
 	move.l %d0, (%a1)
 	move.l %d0, (%a2)
-	move.l %d0, (%a3)
-
-	/* invalidate and disable cache */
-	move.l	#0x01000000, %d0	/* Invalidate cache cmd */
-	movec	%d0, %CACR		/* Invalidate cache */
-	move.l	#0, %d0
-	movec	%d0, %ACR0
-	movec	%d0, %ACR1
 
 	/* set stackpointer to end of internal ram to get some stackspace for
 	   the first c-code */
@@ -510,84 +504,6 @@ _int_handler:
 	RESTORE_ALL
 
 /*------------------------------------------------------------------------------*/
-/* cache functions */
-	.globl	icache_enable
-icache_enable:
-	move.l	#0x01200000, %d0	/* Invalid cache */
-	movec	%d0, %CACR
-
-	move.l	#(CONFIG_SYS_SDRAM_BASE + 0x1c000), %d0
-	movec	%d0, %ACR0
-
-	move.l	#0x81600610, %d0	/* Enable cache */
-	movec	%d0, %CACR
-
-	move.l	#(ICACHE_STATUS), %a1
-	moveq	#1, %d0
-	move.l	%d0, (%a1)
-	rts
-
-	.globl	icache_disable
-icache_disable:
-	move.l	#0x01F00000, %d0	/* Setup cache mask */
-	movec	%d0, %CACR		/* Invalidate icache */
-	clr.l	%d0
-	movec	%d0, %ACR0
-	movec	%d0, %ACR1
-
-	move.l	#(ICACHE_STATUS), %a1
-	moveq	#0, %d0
-	move.l	%d0, (%a1)
-	rts
-
-	.globl	icache_status
-icache_status:
-	move.l	#(ICACHE_STATUS), %a1
-	move.l	(%a1), %d0
-	rts
-
-	.globl	icache_invalid
-icache_invalid:
-	move.l	#0x80600610, %d0	/* Invalidate icache */
-	movec	%d0, %CACR		/* Enable and invalidate cache */
-	rts
-
-	.globl	dcache_enable
-dcache_enable:
-	move.l	#0x01200000, %d0	/* Invalid cache */
-	movec	%d0, %CACR
-
-	move.l	#0x81300610, %d0
-	movec	%d0, %CACR
-
-	move.l	#(DCACHE_STATUS), %a1
-	moveq	#1, %d0
-	move.l	%d0, (%a1)
-	rts
-
-	.globl	dcache_disable
-dcache_disable:
-	move.l	#0x81600610, %d0	/* Setup cache mask */
-	movec	%d0, %CACR		/* Invalidate icache */
-
-	move.l	#(DCACHE_STATUS), %a1
-	moveq	#0, %d0
-	move.l	%d0, (%a1)
-	rts
-
-	.globl	dcache_invalid
-dcache_invalid:
-	move.l	#0x81100610, %d0	/* Setup cache mask */
-	movec	%d0, %CACR		/* Enable and invalidate cache */
-	rts
-
-	.globl	dcache_status
-dcache_status:
-	move.l	#(DCACHE_STATUS), %a1
-	move.l	(%a1), %d0
-	rts
-
-/*------------------------------------------------------------------------------*/
 
 	.globl	version_string
 version_string:
diff --git a/cpu/mcf523x/start.S b/cpu/mcf523x/start.S
index d44da37..20b50e7 100644
--- a/cpu/mcf523x/start.S
+++ b/cpu/mcf523x/start.S
@@ -24,6 +24,7 @@
 #include <config.h>
 #include <timestamp.h>
 #include "version.h"
+#include <asm/cache.h>
 
 #ifndef	 CONFIG_IDENT_STRING
 #define	 CONFIG_IDENT_STRING ""
@@ -135,7 +136,7 @@ _start:
 	movec	%d0, %RAMBAR1
 
 	/* invalidate and disable cache */
-	move.l	#0x01000000, %d0		/* Invalidate cache cmd */
+	move.l	#CF_CACR_CINV, %d0		/* Invalidate cache cmd */
 	movec	%d0, %CACR			/* Invalidate cache */
 	nop
 	move.l	#0, %d0
@@ -144,8 +145,8 @@ _start:
 
 	/* initialize general use internal ram */
 	move.l #0, %d0
-	move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-8), %a1
-	move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-4), %a2
+	move.l #(ICACHE_STATUS), %a1	/* icache */
+	move.l #(DCACHE_STATUS), %a2	/* icache */
 	move.l %d0, (%a1)
 	move.l %d0, (%a2)
 
@@ -265,74 +266,6 @@ _int_handler:
 	RESTORE_ALL
 
 /*------------------------------------------------------------------------------*/
-/* cache functions */
-	.globl	icache_enable
-icache_enable:
-	move.l	#0x01000000, %d0		/* Invalidate cache cmd */
-	movec	%d0, %CACR			/* Invalidate cache */
-	nop
-	move.l	#(CONFIG_SYS_SDRAM_BASE + 0xc000), %d0	/* Setup cache mask */
-	movec	%d0, %ACR0			/* Enable cache */
-	move.l	#(CONFIG_SYS_FLASH_BASE + 0xc000), %d0	/* Setup cache mask */
-	movec	%d0, %ACR1			/* Enable cache */
-
-	move.l	#0x80400100, %d0		/* Setup cache mask */
-	movec	%d0, %CACR			/* Enable cache */
-	nop
-
-	move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-8), %a1
-	moveq	#1, %d0
-	move.l	%d0, (%a1)
-	rts
-
-	.globl	icache_disable
-icache_disable:
-	move.l	#0x00000100, %d0		/* Setup cache mask */
-	movec	%d0, %CACR			/* Disable cache */
-	clr.l	%d0				/* Setup cache mask */
-	movec	%d0, %ACR0
-	movec	%d0, %ACR1
-
-	move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-8), %a1
-	moveq	#0, %d0
-	move.l	%d0, (%a1)
-	rts
-
-	.globl	icache_status
-icache_status:
-	move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-8), %a1
-	move.l	(%a1), %d0
-	rts
-
-	.globl	icache_invalid
-icache_invalid:
-	move.l	#0x80600100, %d0		/* Setup cache mask */
-	movec	%d0, %CACR			/* Enable cache */
-	nop
-	rts
-
-	.globl	dcache_enable
-dcache_enable:
-	move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-4), %a1
-	moveq	#1, %d0
-	move.l	%d0, (%a1)
-	rts
-
-    /* No dcache, just a dummy function */
-	.globl	dcache_disable
-dcache_disable:
-	move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-4), %a1
-	moveq	#0, %d0
-	move.l	%d0, (%a1)
-	rts
-
-	.globl	dcache_status
-dcache_status:
-	move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-4), %a1
-	move.l	(%a1), %d0
-	rts
-
-/*------------------------------------------------------------------------------*/
 
 	.globl	version_string
 version_string:
diff --git a/cpu/mcf52x2/start.S b/cpu/mcf52x2/start.S
index 0dd4de5..9ef206a 100644
--- a/cpu/mcf52x2/start.S
+++ b/cpu/mcf52x2/start.S
@@ -24,12 +24,12 @@
 #include <config.h>
 #include <timestamp.h>
 #include "version.h"
+#include <asm/cache.h>
 
 #ifndef	 CONFIG_IDENT_STRING
 #define	 CONFIG_IDENT_STRING ""
 #endif
 
-
 #define _START	_start
 #define _FAULT	_fault
 
@@ -201,6 +201,13 @@ _after_flashbar_copy:
 	movec	%d0, %RAMBAR1
 #endif
 
+	/* initialize general use internal ram */
+	move.l #0, %d0
+	move.l #(ICACHE_STATUS), %a1	/* icache */
+	move.l #(DCACHE_STATUS), %a2	/* icache */
+	move.l %d0, (%a1)
+	move.l %d0, (%a2)
+
 	/* set stackpointer to end of internal ram to get some stackspace for the first c-code */
 	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
 	clr.l %sp@-
@@ -283,23 +290,6 @@ clear_bss:
 	cmp.l	%a2, %a1
 	bne	7b
 
-#if defined(CONFIG_M5281) || defined(CONFIG_M5282)
-	/* patch the 3 accesspoints to 3 ichache_state */
-	/* quick and dirty */
-
-	move.l	%a0,%d1
-	add.l	#(icache_state - CONFIG_SYS_MONITOR_BASE),%d1
-	move.l	%a0,%a1
-	add.l	#(icache_state_access_1+2 - CONFIG_SYS_MONITOR_BASE),%a1
-	move.l  %d1,(%a1)
-	move.l	%a0,%a1
-	add.l	#(icache_state_access_2+2 - CONFIG_SYS_MONITOR_BASE),%a1
-	move.l  %d1,(%a1)
-	move.l	%a0,%a1
-	add.l	#(icache_state_access_3+2 - CONFIG_SYS_MONITOR_BASE),%a1
-	move.l  %d1,(%a1)
-#endif
-
 	/* calculate relative jump to board_init_r in ram */
 	move.l %a0, %a1
 	add.l #(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1
@@ -336,156 +326,6 @@ _int_handler:
 	RESTORE_ALL
 
 /*------------------------------------------------------------------------------*/
-/* cache functions */
-#ifdef	CONFIG_M5208
-	.globl	icache_enable
-icache_enable:
-	move.l	#0x01000000, %d0		/* Invalidate cache cmd */
-	movec	%d0, %CACR			/* Invalidate cache */
-	move.l	#(CONFIG_SYS_SDRAM_BASE + 0xC000), %d0	/* Setup cache mask */
-	movec	%d0, %ACR0			/* Enable cache */
-
-	move.l	#0x80000200, %d0		/* Setup cache mask */
-	movec	%d0, %CACR			/* Enable cache */
-	nop
-
-	move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-8), %a1
-	moveq	#1, %d0
-	move.l	%d0, (%a1)
-	rts
-#endif
-
-#ifdef	CONFIG_M5271
-	.globl	icache_enable
-icache_enable:
-	move.l	#0x01000000, %d0		/* Invalidate cache cmd */
-	movec	%d0, %CACR			/* Invalidate cache */
-	move.l	#(CONFIG_SYS_SDRAM_BASE + 0xc000), %d0	/* Setup cache mask */
-	movec	%d0, %ACR0			/* Enable cache */
-
-	move.l	#0x80000200, %d0		/* Setup cache mask */
-	movec	%d0, %CACR			/* Enable cache */
-	nop
-
-	move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-8), %a1
-	moveq	#1, %d0
-	move.l	%d0, (%a1)
-	rts
-#endif
-
-#ifdef	CONFIG_M5272
-	.globl	icache_enable
-icache_enable:
-	move.l	#0x01000000, %d0		/* Invalidate cache cmd */
-	movec	%d0, %CACR			/* Invalidate cache */
-	move.l	#0x0000c000, %d0		/* Setup cache mask */
-	movec	%d0, %ACR0			/* Enable cache */
-	move.l	#0xff00c000, %d0		/* Setup cache mask */
-	movec	%d0, %ACR1			/* Enable cache */
-	move.l	#0x80000100, %d0		/* Setup cache mask */
-	movec	%d0, %CACR			/* Enable cache */
-	moveq	#1, %d0
-	move.l	%d0, icache_state
-	rts
-#endif
-
-#if  defined(CONFIG_M5275)
-/*
- * Instruction cache only
- */
-	.globl	icache_enable
-icache_enable:
-	move.l	#0x01400000, %d0		/* Invalidate cache cmd */
-	movec	%d0, %CACR			/* Invalidate cache */
-	move.l	#0x0000c000, %d0		/* Setup SDRAM caching */
-	movec	%d0, %ACR0			/* Enable cache */
-	move.l	#0x00000000, %d0		/* No other caching */
-	movec	%d0, %ACR1			/* Enable cache */
-	move.l	#0x80400100, %d0		/* Setup cache mask */
-	movec	%d0, %CACR			/* Enable cache */
-	moveq	#1, %d0
-	move.l	%d0, icache_state
-	rts
-#endif
-
-#ifdef CONFIG_M5282
-	.globl	icache_enable
-icache_enable:
-	move.l	#0x01000000, %d0		/* Invalidate cache cmd */
-	movec	%d0, %CACR			/* Invalidate cache */
-	move.l	#0x0000c000, %d0		/* Setup cache mask */
-	movec	%d0, %ACR0			/* Enable cache */
-	move.l	#0xff00c000, %d0		/* Setup cache mask */
-	movec	%d0, %ACR1			/* Enable cache */
-	move.l	#0x80400100, %d0		/* Setup cache mask, data cache disabel*/
-	movec	%d0, %CACR			/* Enable cache */
-	moveq	#1, %d0
-icache_state_access_1:
-	move.l	%d0, icache_state
-	rts
-#endif
-
-#if defined(CONFIG_M5249) || defined(CONFIG_M5253)
-	.globl	icache_enable
-icache_enable:
-	/*
-	 *  Note: The 5249 Documentation doesn't give a bit position for CINV!
-	 *  From the 5272 and the 5307 documentation, I have deduced that it is
-	 *  probably CACR[24]. Should someone say something to Motorola?
-	 *	~Jeremy
-	 */
-	move.l	#0x01000000, %d0		/* Invalidate whole cache */
-	move.c	%d0,%CACR
-	move.l	#0xff00c000, %d0		/* Set FLASH cachable: always match (SM=0b10) */
-	move.c	%d0, %ACR0
-	move.l	#0x0000c000, %d0		/* Set SDRAM cachable: always match (SM=0b10) */
-	move.c	%d0, %ACR1
-	move.l	#0x90000200, %d0		/* Set cache enable cmd */
-	move.c	%d0,%CACR
-	moveq	#1, %d0
-	move.l	%d0, icache_state
-	rts
-#endif
-
-	.globl	icache_disable
-icache_disable:
-	move.l	#0x00000100, %d0		/* Setup cache mask */
-	movec	%d0, %CACR			/* Enable cache */
-	clr.l	%d0				/* Setup cache mask */
-	movec	%d0, %ACR0			/* Enable cache */
-	movec	%d0, %ACR1			/* Enable cache */
-	moveq	#0, %d0
-icache_state_access_2:
-	move.l	%d0, icache_state
-	rts
-
-	.globl	icache_status
-icache_status:
-icache_state_access_3:
-	move.l	#(icache_state), %a0
-	move.l	(%a0), %d0
-	rts
-
-	.data
-icache_state:
-	.long	0	/* cache is diabled on inirialization */
-
-	.globl	dcache_enable
-dcache_enable:
-	/* dummy function */
-	rts
-
-	.globl	dcache_disable
-dcache_disable:
-	/* dummy function */
-	rts
-
-	.globl	dcache_status
-dcache_status:
-	/* dummy function */
-	rts
-
-/*------------------------------------------------------------------------------*/
 
 	.globl	version_string
 version_string:
diff --git a/cpu/mcf532x/start.S b/cpu/mcf532x/start.S
index 5abd944..a80b0a9 100644
--- a/cpu/mcf532x/start.S
+++ b/cpu/mcf532x/start.S
@@ -27,6 +27,7 @@
 #include <config.h>
 #include <timestamp.h>
 #include "version.h"
+#include <asm/cache.h>
 
 #ifndef	 CONFIG_IDENT_STRING
 #define	 CONFIG_IDENT_STRING ""
@@ -142,7 +143,7 @@ _start:
 	movec	%d0, %RAMBAR1
 
 	/* invalidate and disable cache */
-	move.l	#0x01000000, %d0		/* Invalidate cache cmd */
+	move.l	#CF_CACR_CINVA, %d0		/* Invalidate cache cmd */
 	movec	%d0, %CACR			/* Invalidate cache */
 	move.l	#0, %d0
 	movec	%d0, %ACR0
@@ -158,8 +159,8 @@ _start:
 
 	/* initialize general use internal ram */
 	move.l #0, %d0
-	move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-8), %a1
-	move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-4), %a2
+	move.l #(ICACHE_STATUS), %a1	/* icache */
+	move.l #(DCACHE_STATUS), %a2	/* icache */
 	move.l %d0, (%a1)
 	move.l %d0, (%a2)
 
@@ -279,71 +280,6 @@ _int_handler:
 	RESTORE_ALL
 
 /*------------------------------------------------------------------------------*/
-/* cache functions */
-	.globl	icache_enable
-icache_enable:
-	move.l	#0x01000000, %d0		/* Invalidate cache cmd */
-	movec	%d0, %CACR			/* Invalidate cache */
-	move.l  #(CONFIG_SYS_SDRAM_BASE + 0xc000 + ((CONFIG_SYS_SDRAM_SIZE & 0x1fe0 - 1) << 16)), %d0
-	movec	%d0, %ACR0			/* Enable cache */
-
-	move.l	#0x80000200, %d0		/* Setup cache mask */
-	movec	%d0, %CACR			/* Enable cache */
-	nop
-
-	move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-8), %a1
-	moveq	#1, %d0
-	move.l	%d0, (%a1)
-	rts
-
-	.globl	icache_disable
-icache_disable:
-	move.l	#0x01000000, %d0		/* Setup cache mask */
-	movec	%d0, %CACR			/* Disable cache */
-	clr.l	%d0				/* Setup cache mask */
-	movec	%d0, %ACR0
-	movec	%d0, %ACR1
-
-	move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-8), %a1
-	moveq	#0, %d0
-	move.l	%d0, (%a1)
-	rts
-
-	.globl	icache_status
-icache_status:
-	move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-8), %a1
-	move.l	(%a1), %d0
-	rts
-
-	.globl	icache_invalid
-icache_invalid:
-	move.l	#0x81000200, %d0		/* Setup cache mask */
-	movec	%d0, %CACR			/* Enable cache */
-	rts
-
-	.globl	dcache_enable
-dcache_enable:
-	move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-4), %a1
-	moveq	#1, %d0
-	move.l	%d0, (%a1)
-	rts
-
-    /* No dcache, just a dummy function */
-	.globl	dcache_disable
-dcache_disable:
-	move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-4), %a1
-	moveq	#0, %d0
-	move.l	%d0, (%a1)
-	rts
-
-	.globl	dcache_status
-dcache_status:
-	move.l #(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-4), %a1
-	move.l	(%a1), %d0
-	rts
-
-/*------------------------------------------------------------------------------*/
-
 	.globl	version_string
 version_string:
 	.ascii U_BOOT_VERSION
diff --git a/cpu/mcf5445x/start.S b/cpu/mcf5445x/start.S
index d2d4439..738e4a7 100644
--- a/cpu/mcf5445x/start.S
+++ b/cpu/mcf5445x/start.S
@@ -24,16 +24,12 @@
 #include <config.h>
 #include <timestamp.h>
 #include "version.h"
+#include <asm/cache.h>
 
 #ifndef	 CONFIG_IDENT_STRING
 #define	 CONFIG_IDENT_STRING ""
 #endif
 
-/* last three long word reserved for cache status */
-#define CACR_STATUS	(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-12)
-#define ICACHE_STATUS	(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END- 8)
-#define DCACHE_STATUS	(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END- 4)
-
 #define _START	_start
 #define _FAULT	_fault
 
@@ -160,15 +156,13 @@ asm_dram_init:
 
 	/* initialize general use internal ram */
 	move.l #0, %d0
-	move.l #(CACR_STATUS), %a1	/* CACR */
-	move.l #(ICACHE_STATUS), %a2	/* icache */
-	move.l #(DCACHE_STATUS), %a3	/* dcache */
+	move.l #(ICACHE_STATUS), %a1	/* icache */
+	move.l #(DCACHE_STATUS), %a2	/* dcache */
 	move.l %d0, (%a1)
 	move.l %d0, (%a2)
-	move.l %d0, (%a3)
 
 	/* invalidate and disable cache */
-	move.l	#0x01004100, %d0	/* Invalidate cache cmd */
+	move.l	#(CONFIG_SYS_ICACHE_INV + CONFIG_SYS_DCACHE_INV), %d0
 	movec	%d0, %CACR		/* Invalidate cache */
 	move.l	#0, %d0
 	movec	%d0, %ACR0
@@ -411,15 +405,13 @@ _start:
 
 	/* initialize general use internal ram */
 	move.l #0, %d0
-	move.l #(CACR_STATUS), %a1	/* CACR */
-	move.l #(ICACHE_STATUS), %a2	/* icache */
-	move.l #(DCACHE_STATUS), %a3	/* dcache */
+	move.l #(ICACHE_STATUS), %a1	/* icache */
+	move.l #(DCACHE_STATUS), %a2	/* dcache */
 	move.l %d0, (%a1)
 	move.l %d0, (%a2)
-	move.l %d0, (%a3)
 
 	/* invalidate and disable cache */
-	move.l	#0x01004100, %d0	/* Invalidate cache cmd */
+	move.l	#(CONFIG_SYS_ICACHE_INV + CONFIG_SYS_DCACHE_INV), %d0
 	movec	%d0, %CACR		/* Invalidate cache */
 	move.l	#0, %d0
 	movec	%d0, %ACR0
@@ -544,107 +536,6 @@ _int_handler:
 	RESTORE_ALL
 
 /*------------------------------------------------------------------------------*/
-/* cache functions */
-	.globl	icache_enable
-icache_enable:
-	move.l #(CACR_STATUS), %a1	/* read CACR Status */
-	move.l	(%a1), %d1
-
-	move.l	#0x00040100, %d0	/* Invalidate icache */
-	movec	%d0, %CACR
-
-	move.l	#(CONFIG_SYS_SDRAM_BASE + 0xC000), %d0	/* Setup icache */
-	movec	%d0, %ACR2
-
-	move.l	#0x04088020, %d0	/* Enable bcache and icache */
-	movec	%d0, %CACR
-
-	move.l #(ICACHE_STATUS), %a1
-	moveq	#1, %d0
-	move.l	%d0, (%a1)
-	rts
-
-	.globl	icache_disable
-icache_disable:
-	move.l #(CACR_STATUS), %a1	/* read CACR Status */
-	move.l	(%a1), %d0
-
-	move.l	#0xFFF77BFF, %d0
-	or.l	#0x00040100, %d0	/* Setup cache mask */
-	movec	%d0, %CACR		/* Invalidate icache */
-	clr.l	%d0
-	movec	%d0, %ACR2
-	movec	%d0, %ACR3
-
-	move.l #(ICACHE_STATUS), %a1
-	moveq	#0, %d0
-	move.l	%d0, (%a1)
-	rts
-
-	.globl	icache_status
-icache_status:
-	move.l #(ICACHE_STATUS), %a1
-	move.l	(%a1), %d0
-	rts
-
-	.globl	icache_invalid
-icache_invalid:
-	move.l #(CACR_STATUS), %a1	/* read CACR Status */
-	move.l	(%a1), %d0
-
-	move.l	#0x00040100, %d0	/* Invalidate icache */
-	movec	%d0, %CACR		/* Enable and invalidate cache */
-	rts
-
-	.globl	dcache_enable
-dcache_enable:
-	move.l #(CACR_STATUS), %a1	/* read CACR Status */
-	move.l	(%a1), %d1
-
-	move.l	#0x01040100, %d0
-	movec	%d0, %CACR		/* Invalidate dcache */
-
-	move.l	#0x80088020, %d0	/* Enable bcache and icache */
-	movec	%d0, %CACR
-
-	move.l #(DCACHE_STATUS), %a1
-	moveq	#1, %d0
-	move.l	%d0, (%a1)
-	rts
-
-	.globl	dcache_disable
-dcache_disable:
-	move.l #(CACR_STATUS), %a1	/* read CACR Status */
-	move.l	(%a1), %d0
-
-	and.l	#0x7FFFFFFF, %d0
-	or.l	#0x01000000, %d0	/* Setup cache mask */
-	movec	%d0, %CACR		/* Disable dcache */
-	clr.l	%d0
-	movec	%d0, %ACR0
-	movec	%d0, %ACR1
-
-	move.l #(DCACHE_STATUS), %a1
-	moveq	#0, %d0
-	move.l	%d0, (%a1)
-	rts
-
-	.globl	dcache_invalid
-dcache_invalid:
-	move.l #(CACR_STATUS), %a1	/* read CACR Status */
-	move.l	(%a1), %d0
-
-	move.l	#0x81088020, %d0	/* Setup cache mask */
-	movec	%d0, %CACR		/* Enable and invalidate cache */
-	rts
-
-	.globl	dcache_status
-dcache_status:
-	move.l #(DCACHE_STATUS), %a1
-	move.l	(%a1), %d0
-	rts
-
-/*------------------------------------------------------------------------------*/
 
 	.globl	version_string
 version_string:
diff --git a/cpu/mcf547x_8x/start.S b/cpu/mcf547x_8x/start.S
index 94ef14b..8411862 100644
--- a/cpu/mcf547x_8x/start.S
+++ b/cpu/mcf547x_8x/start.S
@@ -24,16 +24,12 @@
 #include <config.h>
 #include <timestamp.h>
 #include "version.h"
+#include <asm/cache.h>
 
 #ifndef	 CONFIG_IDENT_STRING
 #define	 CONFIG_IDENT_STRING ""
 #endif
 
-/* last three long word reserved for cache status */
-#define ICACHE_STATUS	(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END- 4)
-#define DCACHE_STATUS	(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END- 8)
-#define CACR_STATUS	(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-12)
-
 #define _START	_start
 #define _FAULT	_fault
 
@@ -158,10 +154,8 @@ _start:
 	move.l #0, %d0
 	move.l #(ICACHE_STATUS), %a1	/* icache */
 	move.l #(DCACHE_STATUS), %a2	/* icache */
-	move.l #(CACR_STATUS), %a3	/* CACR */
 	move.l %d0, (%a1)
 	move.l %d0, (%a2)
-	move.l %d0, (%a3)
 
 	/* set stackpointer to end of internal ram to get some stackspace for the
 	   first c-code */
@@ -279,81 +273,6 @@ _int_handler:
 	RESTORE_ALL
 
 /*------------------------------------------------------------------------------*/
-/* cache functions */
-	.globl	icache_enable
-icache_enable:
-	move.l	#(CONFIG_SYS_SDRAM_BASE + 0x1c000), %d0
-	movec	%d0, %ACR2			/* Enable cache */
-
-	move.l	#0x020C8100, %d0		/* Setup cache mask */
-	movec	%d0, %CACR			/* Enable cache */
-	nop
-
-	move.l #(ICACHE_STATUS), %a1
-	moveq	#1, %d0
-	move.l	%d0, (%a1)
-	rts
-
-	.globl	icache_disable
-icache_disable:
-	move.l	#0x000C8100, %d0		/* Setup cache mask */
-	movec	%d0, %CACR			/* Disable cache */
-	clr.l	%d0				/* Setup cache mask */
-	movec	%d0, %ACR2
-	movec	%d0, %ACR3
-
-	move.l #(ICACHE_STATUS), %a1
-	moveq	#0, %d0
-	move.l	%d0, (%a1)
-	rts
-
-	.globl	icache_invalid
-icache_invalid:
-	move.l	#0x000C8100, %d0		/* Setup cache mask */
-	movec	%d0, %CACR			/* Enable cache */
-	rts
-
-	.globl	icache_status
-icache_status:
-	move.l #(ICACHE_STATUS), %a1
-	move.l	(%a1), %d0
-	rts
-
-	.globl	dcache_enable
-dcache_enable:
-	bsr	icache_disable
-
-	move.l	#(CONFIG_SYS_SDRAM_BASE + 0xc000), %d0
-	movec	%d0, %ACR0			/* Enable cache */
-
-	move.l	#0xA30C8100, %d0		/* Invalidate cache cmd */
-	movec	%d0, %CACR			/* Invalidate cache */
-
-	move.l #(DCACHE_STATUS), %a1
-	moveq	#1, %d0
-	move.l	%d0, (%a1)
-	rts
-
-	.globl	dcache_disable
-dcache_disable:
-	move.l	#0xA30C8100, %d0		/* Setup cache mask */
-	movec	%d0, %CACR			/* Disable cache */
-	clr.l	%d0				/* Setup cache mask */
-	movec	%d0, %ACR0
-	movec	%d0, %ACR1
-
-	move.l #(DCACHE_STATUS), %a1
-	moveq	#0, %d0
-	move.l	%d0, (%a1)
-	rts
-
-	.globl	dcache_status
-dcache_status:
-	move.l #(DCACHE_STATUS), %a1
-	move.l	(%a1), %d0
-	rts
-
-/*------------------------------------------------------------------------------*/
 
 	.globl	version_string
 version_string:
diff --git a/include/asm-m68k/cache.h b/include/asm-m68k/cache.h
new file mode 100644
index 0000000..7c84e48
--- /dev/null
+++ b/include/asm-m68k/cache.h
@@ -0,0 +1,210 @@
+/*
+ * ColdFire cache
+ *
+ * Copyright (C) 2004-2010 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CACHE_H
+#define __CACHE_H
+
+#if defined(CONFIG_MCF520x) || defined(CONFIG_MCF523x) || \
+    defined(CONFIG_MCF52x2) || defined(CONFIG_MCF5227x)
+#define CONFIG_CF_V2
+#endif
+
+#if defined(CONFIG_MCF532x) || defined(CONFIG_MCF5301x)
+#define CONFIG_CF_V3
+#endif
+
+#if defined(CONFIG_MCF547x_8x) || defined(CONFIG_MCF5445x)
+#define CONFIG_CF_V4
+#if defined(CONFIG_MCF5441x)
+#define CONFIG_CF_V4E		/* Four Extra ACRn */
+#endif
+#endif
+
+/* ***** CACR ***** */
+/* V2 Core */
+#ifdef CONFIG_CF_V2
+
+#define CF_CACR_CENB		(1 << 31)
+#define CF_CACR_CPD		(1 << 28)
+#define CF_CACR_CFRZ		(1 << 27)
+#define CF_CACR_CEIB		(1 << 10)
+#define CF_CACR_DCM		(1 << 9)
+#define CF_CACR_DBWE		(1 << 8)
+
+#if defined(CONFIG_MCF5249) || defined(CONFIG_MCF5253)
+#define CF_CACR_DWP		(1 << 6)
+#else
+#define CF_CACR_CINV		(1 << 24)
+#define CF_CACR_DISI		(1 << 23)
+#define CF_CACR_DISD		(1 << 22)
+#define CF_CACR_INVI		(1 << 21)
+#define CF_CACR_INVD		(1 << 20)
+#define CF_CACR_DWP		(1 << 5)
+#define CF_CACR_EUSP		(1 << 4)
+#endif				/* CONFIG_MCF5249 || CONFIG_MCF5253 */
+
+#endif				/* CONFIG_CF_V2 */
+
+/* V3 Core */
+#ifdef CONFIG_CF_V3
+
+#define CF_CACR_EC		(1 << 31)
+#define CF_CACR_ESB		(1 << 29)
+#define CF_CACR_DPI		(1 << 28)
+#define CF_CACR_HLCK		(1 << 27)
+#define CF_CACR_CINVA		(1 << 24)
+#define CF_CACR_DNFB		(1 << 10)
+#define CF_CACR_DCM_UNMASK	0xFFFFFCFF
+#define CF_CACR_DCM_WT		(0 << 8)
+#define CF_CACR_DCM_CB		(1 << 8)
+#define CF_CACR_DCM_P		(2 << 8)
+#define CF_CACR_DCM_IP		(3 << 8)
+#define CF_CACR_DW		(1 << 5)
+#define CF_CACR_EUSP		(1 << 4)
+
+#endif				/* CONFIG_CF_V3 */
+
+/* V4 Core */
+#ifdef CONFIG_CF_V4
+
+#define CF_CACR_DEC		(1 << 31)
+#define CF_CACR_DW		(1 << 30)
+#define CF_CACR_DESB		(1 << 29)
+#define CF_CACR_DDPI		(1 << 28)
+#define CF_CACR_DHLCK		(1 << 27)
+#define CF_CACR_DDCM_UNMASK	(0xF9FFFFFF)
+#define CF_CACR_DDCM_WT		(0 << 25)
+#define CF_CACR_DDCM_CB		(1 << 25)
+#define CF_CACR_DDCM_P		(2 << 25)
+#define CF_CACR_DDCM_IP		(3 << 25)
+#define CF_CACR_DCINVA		(1 << 24)
+
+#define CF_CACR_DDSP		(1 << 23)
+#define CF_CACR_BEC		(1 << 19)
+#define CF_CACR_BCINVA		(1 << 18)
+#define CF_CACR_IEC		(1 << 15)
+#define CF_CACR_DNFB		(1 << 13)
+#define CF_CACR_IDPI		(1 << 12)
+#define CF_CACR_IHLCK		(1 << 11)
+#define CF_CACR_IDCM		(1 << 10)
+#define CF_CACR_ICINVA		(1 << 8)
+#define CF_CACR_IDSP		(1 << 7)
+#define CF_CACR_EUSP		(1 << 5)
+
+#ifdef CONFIG_MCF5445x
+#define CF_CACR_IVO		(1 << 20)
+#define CF_CACR_SPA		(1 << 14)
+#else
+#define CF_CACR_DF		(1 << 4)
+#endif
+
+#endif				/* CONFIG_CF_V4 */
+
+/* ***** ACR ***** */
+#define CF_ACR_ADR_UNMASK	(0x00FFFFFF)
+#define CF_ACR_ADR(x)		((x & 0xFF) << 24)
+#define CF_ACR_ADRMSK_UNMASK	(0xFF00FFFF)
+#define CF_ACR_ADRMSK(x)	((x & 0xFF) << 16)
+#define CF_ACR_EN		(1 << 15)
+#define CF_ACR_SM_UNMASK	(0xFFFF9FFF)
+#define CF_ACR_SM_UM		(0 << 13)
+#define CF_ACR_SM_SM		(1 << 13)
+#define CF_ACR_SM_ALL		(3 << 13)
+#define CF_ACR_WP		(1 << 2)
+
+/* V2 Core */
+#ifdef CONFIG_CF_V2
+#define CF_ACR_CM		(1 << 6)
+#define CF_ACR_BWE		(1 << 5)
+#else
+/* V3 & V4 */
+#define CF_ACR_CM_UNMASK	(0xFFFFFF9F)
+#define CF_ACR_CM_WT		(0 << 5)
+#define CF_ACR_CM_CB		(1 << 5)
+#define CF_ACR_CM_P		(2 << 5)
+#define CF_ACR_CM_IP		(3 << 5)
+#endif				/* CONFIG_CF_V2 */
+
+/* V4 Core */
+#ifdef CONFIG_CF_V4
+#define CF_ACR_AMM		(1 << 10)
+#define CF_ACR_SP		(1 << 3)
+#endif				/* CONFIG_CF_V4 */
+
+
+#ifndef CONFIG_SYS_CACHE_ICACR
+#define CONFIG_SYS_CACHE_ICACR	0
+#endif
+
+#ifndef CONFIG_SYS_CACHE_DCACR
+#ifdef CONFIG_SYS_CACHE_ICACR
+#define CONFIG_SYS_CACHE_DCACR	CONFIG_SYS_CACHE_ICACR
+#else
+#define CONFIG_SYS_CACHE_DCACR	0
+#endif
+#endif
+
+#ifndef CONFIG_SYS_CACHE_ACR0
+#define CONFIG_SYS_CACHE_ACR0	0
+#endif
+
+#ifndef CONFIG_SYS_CACHE_ACR1
+#define CONFIG_SYS_CACHE_ACR1	0
+#endif
+
+#ifndef CONFIG_SYS_CACHE_ACR2
+#define CONFIG_SYS_CACHE_ACR2	0
+#endif
+
+#ifndef CONFIG_SYS_CACHE_ACR3
+#define CONFIG_SYS_CACHE_ACR3	0
+#endif
+
+#ifndef CONFIG_SYS_CACHE_ACR4
+#define CONFIG_SYS_CACHE_ACR4	0
+#endif
+
+#ifndef CONFIG_SYS_CACHE_ACR5
+#define CONFIG_SYS_CACHE_ACR5	0
+#endif
+
+#ifndef CONFIG_SYS_CACHE_ACR6
+#define CONFIG_SYS_CACHE_ACR6	0
+#endif
+
+#ifndef CONFIG_SYS_CACHE_ACR7
+#define CONFIG_SYS_CACHE_ACR7	0
+#endif
+
+#define CF_ADDRMASK(x)		(((x > 0x10) ? ((x >> 4) - 1) : (x)) << 16)
+
+#ifndef __ASSEMBLY__		/* put C only stuff in this section */
+
+void icache_invalid(void);
+void dcache_invalid(void);
+
+#endif
+
+#endif				/* __CACHE_H */
diff --git a/include/configs/EB+MCF-EV123.h b/include/configs/EB+MCF-EV123.h
index a0b27a8..880cb4e 100644
--- a/include/configs/EB+MCF-EV123.h
+++ b/include/configs/EB+MCF-EV123.h
@@ -208,6 +208,18 @@
  */
 #define CONFIG_SYS_CACHELINE_SIZE	16
 
+#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 8)
+#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 4)
+#define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINV + CF_CACR_DCM)
+#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_DISD | \
+					 CF_CACR_CEIB | CF_CACR_DBWE | \
+					 CF_CACR_EUSP)
+
 /*-----------------------------------------------------------------------
  * Memory bank definitions
  */
diff --git a/include/configs/M5208EVBE.h b/include/configs/M5208EVBE.h
index 3cc259f..e6632ac 100644
--- a/include/configs/M5208EVBE.h
+++ b/include/configs/M5208EVBE.h
@@ -207,6 +207,19 @@
 /* Cache Configuration */
 #define CONFIG_SYS_CACHELINE_SIZE	16
 
+#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 8)
+#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 4)
+#define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINV | CF_CACR_INVI)
+#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_CINV | \
+					 CF_CACR_DISD | CF_CACR_INVI | \
+					 CF_CACR_CEIB | CF_CACR_DCM | \
+					 CF_CACR_EUSP)
+
 /* Chipselect bank definitions */
 /*
  * CS0 - NOR Flash
diff --git a/include/configs/M52277EVB.h b/include/configs/M52277EVB.h
index 1801d9d..6c6b5d6 100644
--- a/include/configs/M52277EVB.h
+++ b/include/configs/M52277EVB.h
@@ -302,6 +302,19 @@
  */
 #define CONFIG_SYS_CACHELINE_SIZE	16
 
+#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 8)
+#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 4)
+#define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINV | CF_CACR_INVI)
+#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_CINV | \
+					 CF_CACR_DISD | CF_CACR_INVI | \
+					 CF_CACR_CEIB | CF_CACR_DCM | \
+					 CF_CACR_EUSP)
+
 /*-----------------------------------------------------------------------
  * Memory bank definitions
  */
diff --git a/include/configs/M5235EVB.h b/include/configs/M5235EVB.h
index 2b816ce..5c0dc84 100644
--- a/include/configs/M5235EVB.h
+++ b/include/configs/M5235EVB.h
@@ -237,6 +237,18 @@
  */
 #define CONFIG_SYS_CACHELINE_SIZE	16
 
+#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 8)
+#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 4)
+#define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINV)
+#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_DISD | \
+					 CF_CACR_CEIB | CF_CACR_DCM | \
+					 CF_CACR_EUSP)
+
 /*-----------------------------------------------------------------------
  * Chipselect bank definitions
  */
diff --git a/include/configs/M5249EVB.h b/include/configs/M5249EVB.h
index e3830e5..33ac285 100644
--- a/include/configs/M5249EVB.h
+++ b/include/configs/M5249EVB.h
@@ -60,6 +60,7 @@
  * Command line configuration.
  */
 #include <config_cmd_default.h>
+#define CONFIG_CMD_CACHE
 #undef CONFIG_CMD_NET
 
 #define CONFIG_SYS_PROMPT		"=> "
@@ -165,6 +166,20 @@
  */
 #define CONFIG_SYS_CACHELINE_SIZE	16
 
+#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 8)
+#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 4)
+#define CONFIG_SYS_ICACHE_INV		(CF_CACR_DCM)
+#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_FLASH_BASE | \
+					 CF_ADDRMASK(2) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ACR1		(CONFIG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_CEIB | \
+					 CF_CACR_DBWE)
+
 /*-----------------------------------------------------------------------
  * Memory bank definitions
  */
diff --git a/include/configs/M5253DEMO.h b/include/configs/M5253DEMO.h
index f813f88..9944e12 100644
--- a/include/configs/M5253DEMO.h
+++ b/include/configs/M5253DEMO.h
@@ -57,6 +57,7 @@
  */
 #include <config_cmd_default.h>
 
+#define CONFIG_CMD_CACHE
 #define CONFIG_CMD_LOADB
 #define CONFIG_CMD_LOADS
 #define CONFIG_CMD_EXT2
@@ -226,6 +227,20 @@
 /* Cache Configuration */
 #define CONFIG_SYS_CACHELINE_SIZE	16
 
+#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 8)
+#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 4)
+#define CONFIG_SYS_ICACHE_INV		(CF_CACR_DCM)
+#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_FLASH_BASE | \
+					 CF_ADDRMASK(8) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ACR1		(CONFIG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_CEIB | \
+					 CF_CACR_DBWE)
+
 /* Port configuration */
 #define CONFIG_SYS_FECI2C		0xF0
 
diff --git a/include/configs/M5253EVBE.h b/include/configs/M5253EVBE.h
index df6970c..206d115 100644
--- a/include/configs/M5253EVBE.h
+++ b/include/configs/M5253EVBE.h
@@ -64,6 +64,7 @@
  * Command line configuration.
  */
 #include <config_cmd_default.h>
+#define CONFIG_CMD_CACHE
 #undef CONFIG_CMD_NET
 #define CONFIG_CMD_LOADB
 #define CONFIG_CMD_LOADS
@@ -179,6 +180,20 @@
 /* Cache Configuration */
 #define CONFIG_SYS_CACHELINE_SIZE	16
 
+#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 8)
+#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 4)
+#define CONFIG_SYS_ICACHE_INV		(CF_CACR_DCM)
+#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_FLASH_BASE | \
+					 CF_ADDRMASK(2) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ACR1		(CONFIG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_CEIB | \
+					 CF_CACR_DBWE)
+
 /* Port configuration */
 #define CONFIG_SYS_FECI2C		0xF0
 
diff --git a/include/configs/M5271EVB.h b/include/configs/M5271EVB.h
index 50b3ab2..798949c 100644
--- a/include/configs/M5271EVB.h
+++ b/include/configs/M5271EVB.h
@@ -72,6 +72,7 @@
  */
 #include <config_cmd_default.h>
 
+#define CONFIG_CMD_CACHE
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_NET
 #define CONFIG_CMD_MII
@@ -229,6 +230,19 @@
 /* Cache Configuration */
 #define CONFIG_SYS_CACHELINE_SIZE	16
 
+#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 8)
+#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 4)
+#define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINV | CF_CACR_INVI)
+#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_CINV | \
+					 CF_CACR_DISD | CF_CACR_INVI | \
+					 CF_CACR_CEIB | CF_CACR_DCM | \
+					 CF_CACR_EUSP)
+
 /* Chip Select 0  : Boot Flash */
 #define CONFIG_SYS_CS0_BASE	0xFFE00000
 #define CONFIG_SYS_CS0_MASK	0x001F0001
diff --git a/include/configs/M5272C3.h b/include/configs/M5272C3.h
index f824158..f704bb3 100644
--- a/include/configs/M5272C3.h
+++ b/include/configs/M5272C3.h
@@ -74,6 +74,7 @@
  */
 #include <config_cmd_default.h>
 
+#define CONFIG_CMD_CACHE
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_NET
 #define CONFIG_CMD_PING
@@ -211,6 +212,19 @@
  */
 #define CONFIG_SYS_CACHELINE_SIZE	16
 
+#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 8)
+#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 4)
+#define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINV | CF_CACR_INVI)
+#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_CINV | \
+					 CF_CACR_DISD | CF_CACR_INVI | \
+					 CF_CACR_CEIB | CF_CACR_DCM | \
+					 CF_CACR_EUSP)
+
 /*-----------------------------------------------------------------------
  * Memory bank definitions
  */
diff --git a/include/configs/M5275EVB.h b/include/configs/M5275EVB.h
index f8d43f0..981670a 100644
--- a/include/configs/M5275EVB.h
+++ b/include/configs/M5275EVB.h
@@ -72,6 +72,7 @@
 /* Available command configuration */
 #include <config_cmd_default.h>
 
+#define CONFIG_CMD_CACHE
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_NET
@@ -220,6 +221,19 @@
  */
 #define CONFIG_SYS_CACHELINE_SIZE	16
 
+#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 8)
+#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 4)
+#define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINV | CF_CACR_INVI)
+#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_CINV | \
+					 CF_CACR_DISD | CF_CACR_INVI | \
+					 CF_CACR_CEIB | CF_CACR_DCM | \
+					 CF_CACR_EUSP)
+
 /*-----------------------------------------------------------------------
  * Memory bank definitions
  */
diff --git a/include/configs/M5282EVB.h b/include/configs/M5282EVB.h
index 15590cf..6e0aa14 100644
--- a/include/configs/M5282EVB.h
+++ b/include/configs/M5282EVB.h
@@ -64,6 +64,7 @@
  * Command line configuration.
  */
 #include <config_cmd_default.h>
+#define CONFIG_CMD_CACHE
 #define CONFIG_CMD_NET
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_MII
@@ -209,6 +210,18 @@
  */
 #define CONFIG_SYS_CACHELINE_SIZE	16
 
+#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 8)
+#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 4)
+#define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINV + CF_CACR_DCM)
+#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_DISD | \
+					 CF_CACR_CEIB | CF_CACR_DBWE | \
+					 CF_CACR_EUSP)
+
 /*-----------------------------------------------------------------------
  * Memory bank definitions
  */
diff --git a/include/configs/M53017EVB.h b/include/configs/M53017EVB.h
index c351d41..d983a8f 100644
--- a/include/configs/M53017EVB.h
+++ b/include/configs/M53017EVB.h
@@ -233,6 +233,17 @@
  */
 #define CONFIG_SYS_CACHELINE_SIZE	16
 
+#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 8)
+#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 4)
+#define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINVA)
+#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_EC | CF_CACR_CINVA | \
+					 CF_CACR_DCM_P)
+
 /*-----------------------------------------------------------------------
  * Chipselect bank definitions
  */
diff --git a/include/configs/M5329EVB.h b/include/configs/M5329EVB.h
index 8180c05..159b178 100644
--- a/include/configs/M5329EVB.h
+++ b/include/configs/M5329EVB.h
@@ -237,6 +237,17 @@
  */
 #define CONFIG_SYS_CACHELINE_SIZE	16
 
+#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 8)
+#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 4)
+#define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINVA)
+#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_EC | CF_CACR_CINVA | \
+					 CF_CACR_DCM_P)
+
 /*-----------------------------------------------------------------------
  * Chipselect bank definitions
  */
diff --git a/include/configs/M5373EVB.h b/include/configs/M5373EVB.h
index 8652a80..af1988c 100644
--- a/include/configs/M5373EVB.h
+++ b/include/configs/M5373EVB.h
@@ -237,6 +237,17 @@
  */
 #define CONFIG_SYS_CACHELINE_SIZE	16
 
+#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 8)
+#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 4)
+#define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINVA)
+#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_EC | CF_CACR_CINVA | \
+					 CF_CACR_DCM_P)
+
 /*-----------------------------------------------------------------------
  * Chipselect bank definitions
  */
diff --git a/include/configs/M54451EVB.h b/include/configs/M54451EVB.h
index a5acfd2..a80d330 100644
--- a/include/configs/M54451EVB.h
+++ b/include/configs/M54451EVB.h
@@ -309,6 +309,21 @@
 /* Cache Configuration */
 #define CONFIG_SYS_CACHELINE_SIZE		16
 
+#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 8)
+#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 4)
+#define CONFIG_SYS_ICACHE_INV		(CF_CACR_BCINVA + CF_CACR_ICINVA)
+#define CONFIG_SYS_DCACHE_INV		(CF_CACR_DCINVA)
+#define CONFIG_SYS_CACHE_ACR2		(CONFIG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_BEC | CF_CACR_IEC | \
+					 CF_CACR_ICINVA | CF_CACR_EUSP)
+#define CONFIG_SYS_CACHE_DCACR		((CONFIG_SYS_CACHE_ICACR | \
+					 CF_CACR_DEC | CF_CACR_DDCM_P | \
+					 CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
+
 /*-----------------------------------------------------------------------
  * Memory bank definitions
  */
diff --git a/include/configs/M54455EVB.h b/include/configs/M54455EVB.h
index 7737284..5b4bba8 100644
--- a/include/configs/M54455EVB.h
+++ b/include/configs/M54455EVB.h
@@ -279,7 +279,7 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	0x80000000
-#define CONFIG_SYS_INIT_RAM_END	0x8000	/* End of used area in internal SRAM */
+#define CONFIG_SYS_INIT_RAM_END		0x8000	/* End of used area in internal SRAM */
 #define CONFIG_SYS_INIT_RAM_CTRL	0x221
 #define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
 #define CONFIG_SYS_GBL_DATA_OFFSET	((CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) - 32)
@@ -408,6 +408,21 @@
  */
 #define CONFIG_SYS_CACHELINE_SIZE		16
 
+#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 8)
+#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 4)
+#define CONFIG_SYS_ICACHE_INV		(CF_CACR_BCINVA + CF_CACR_ICINVA)
+#define CONFIG_SYS_DCACHE_INV		(CF_CACR_DCINVA)
+#define CONFIG_SYS_CACHE_ACR2		(CONFIG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_BEC | CF_CACR_IEC | \
+					 CF_CACR_ICINVA | CF_CACR_EUSP)
+#define CONFIG_SYS_CACHE_DCACR		((CONFIG_SYS_CACHE_ICACR | \
+					 CF_CACR_DEC | CF_CACR_DDCM_P | \
+					 CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
+
 /*-----------------------------------------------------------------------
  * Memory bank definitions
  */
diff --git a/include/configs/M5475EVB.h b/include/configs/M5475EVB.h
index 4534002..d007766 100644
--- a/include/configs/M5475EVB.h
+++ b/include/configs/M5475EVB.h
@@ -286,6 +286,22 @@
  */
 #define CONFIG_SYS_CACHELINE_SIZE	16
 
+#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 8)
+#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 4)
+#define CONFIG_SYS_ICACHE_INV		(CF_CACR_BCINVA + CF_CACR_ICINVA + \
+					 CF_CACR_IDCM)
+#define CONFIG_SYS_DCACHE_INV		(CF_CACR_DCINVA)
+#define CONFIG_SYS_CACHE_ACR2		(CONFIG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_BEC | CF_CACR_BCINVA | \
+					 CF_CACR_IEC | CF_CACR_ICINVA)
+#define CONFIG_SYS_CACHE_DCACR		((CONFIG_SYS_CACHE_ICACR | \
+					 CF_CACR_DEC | CF_CACR_DDCM_P | \
+					 CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
+
 /*-----------------------------------------------------------------------
  * Chipselect bank definitions
  */
diff --git a/include/configs/M5485EVB.h b/include/configs/M5485EVB.h
index 971cb67..f23b8b0 100644
--- a/include/configs/M5485EVB.h
+++ b/include/configs/M5485EVB.h
@@ -272,6 +272,22 @@
  */
 #define CONFIG_SYS_CACHELINE_SIZE	16
 
+#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 8)
+#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 4)
+#define CONFIG_SYS_ICACHE_INV		(CF_CACR_BCINVA + CF_CACR_ICINVA + \
+					 CF_CACR_IDCM)
+#define CONFIG_SYS_DCACHE_INV		(CF_CACR_DCINVA)
+#define CONFIG_SYS_CACHE_ACR2		(CONFIG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_BEC | CF_CACR_BCINVA | \
+					 CF_CACR_IEC | CF_CACR_ICINVA)
+#define CONFIG_SYS_CACHE_DCACR		((CONFIG_SYS_CACHE_ICACR | \
+					 CF_CACR_DEC | CF_CACR_DDCM_P | \
+					 CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
+
 /*-----------------------------------------------------------------------
  * Chipselect bank definitions
  */
diff --git a/include/configs/TASREG.h b/include/configs/TASREG.h
index 25f3a26..b69f015 100644
--- a/include/configs/TASREG.h
+++ b/include/configs/TASREG.h
@@ -252,6 +252,17 @@
  */
 #define CONFIG_SYS_CACHELINE_SIZE	16
 
+#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 8)
+#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 4)
+#define CONFIG_SYS_ICACHE_INV		(CF_CACR_DCM)
+#define CONFIG_SYS_CACHE_ACR1		(CONFIG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_CEIB | \
+					 CF_CACR_DBWE)
+
 /*-----------------------------------------------------------------------
  * Memory bank definitions
  */
diff --git a/include/configs/astro_mcf5373l.h b/include/configs/astro_mcf5373l.h
index 1fe42f6..7c8281c 100644
--- a/include/configs/astro_mcf5373l.h
+++ b/include/configs/astro_mcf5373l.h
@@ -386,4 +386,15 @@
 /* Cache Configuration */
 #define CONFIG_SYS_CACHELINE_SIZE	16
 
+#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 8)
+#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 4)
+#define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINVA)
+#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_EC | CF_CACR_CINVA | \
+					 CF_CACR_DCM_P)
+
 #endif	/* _CONFIG_ASTRO_MCF5373L_H */
diff --git a/include/configs/cobra5272.h b/include/configs/cobra5272.h
index 1c3ea23..330e3ac 100644
--- a/include/configs/cobra5272.h
+++ b/include/configs/cobra5272.h
@@ -331,6 +331,19 @@ from which user programs will be started */
  */
 #define CONFIG_SYS_CACHELINE_SIZE	16
 
+#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 8)
+#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 4)
+#define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINV | CF_CACR_INVI)
+#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_CINV | \
+					 CF_CACR_DISD | CF_CACR_INVI | \
+					 CF_CACR_CEIB | CF_CACR_DCM | \
+					 CF_CACR_EUSP)
+
 /*-----------------------------------------------------------------------
  * Memory bank definitions
  *
diff --git a/include/configs/idmr.h b/include/configs/idmr.h
index 841affb..61e3bad 100644
--- a/include/configs/idmr.h
+++ b/include/configs/idmr.h
@@ -224,6 +224,19 @@
 /* Cache Configuration */
 #define CONFIG_SYS_CACHELINE_SIZE	16
 
+#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 8)
+#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 4)
+#define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINV | CF_CACR_INVI)
+#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_CINV | \
+					 CF_CACR_DISD | CF_CACR_INVI | \
+					 CF_CACR_CEIB | CF_CACR_DCM | \
+					 CF_CACR_EUSP)
+
 /* Port configuration */
 #define CONFIG_SYS_FECI2C		0xF0
 
diff --git a/lib_m68k/cache.c b/lib_m68k/cache.c
index 84fb6c2..ed88178 100644
--- a/lib_m68k/cache.c
+++ b/lib_m68k/cache.c
@@ -22,8 +22,129 @@
  */
 
 #include <common.h>
+#include <asm/immap.h>
+#include <asm/cache.h>
 
-void flush_cache (ulong start_addr, ulong size)
+volatile int *cf_icache_status = (int *)ICACHE_STATUS;
+volatile int *cf_dcache_status = (int *)DCACHE_STATUS;
+
+void flush_cache(ulong start_addr, ulong size)
 {
 	/* Must be implemented for all M68k processors with copy-back data cache */
 }
+
+int icache_status(void)
+{
+	return *cf_icache_status;
+}
+
+int dcache_status(void)
+{
+	return *cf_dcache_status;
+}
+
+void icache_enable(void)
+{
+	icache_invalid();
+
+	*cf_icache_status = 1;
+
+#ifdef CONFIG_CF_V4
+	__asm__ __volatile__("movec %0, %%acr2"::"r"(CONFIG_SYS_CACHE_ACR2));
+	__asm__ __volatile__("movec %0, %%acr3"::"r"(CONFIG_SYS_CACHE_ACR3));
+#elif defined(CONFIG_CF_V4e)
+	__asm__ __volatile__("movec %0, %%acr6"::"r"(CONFIG_SYS_CACHE_ACR6));
+	__asm__ __volatile__("movec %0, %%acr7"::"r"(CONFIG_SYS_CACHE_ACR7));
+#else
+	__asm__ __volatile__("movec %0, %%acr0"::"r"(CONFIG_SYS_CACHE_ACR0));
+	__asm__ __volatile__("movec %0, %%acr1"::"r"(CONFIG_SYS_CACHE_ACR1));
+#endif
+
+	__asm__ __volatile__("movec %0, %%cacr"::"r"(CONFIG_SYS_CACHE_ICACR));
+}
+
+void icache_disable(void)
+{
+	u32 temp = 0;
+
+	*cf_icache_status = 0;
+	icache_invalid();
+
+#ifdef CONFIG_CF_V4
+	__asm__ __volatile__("movec %0, %%acr2"::"r"(temp));
+	__asm__ __volatile__("movec %0, %%acr3"::"r"(temp));
+#elif defined(CONFIG_CF_V4e)
+	__asm__ __volatile__("movec %0, %%acr6"::"r"(temp));
+	__asm__ __volatile__("movec %0, %%acr7"::"r"(temp));
+#else
+	__asm__ __volatile__("movec %0, %%acr0"::"r"(temp));
+	__asm__ __volatile__("movec %0, %%acr1"::"r"(temp));
+
+#endif
+}
+
+void icache_invalid(void)
+{
+	u32 temp;
+
+	temp = CONFIG_SYS_ICACHE_INV;
+	if (*cf_icache_status)
+		temp |= CONFIG_SYS_CACHE_ICACR;
+
+	__asm__ __volatile__("movec %0, %%cacr"::"r"(temp));
+}
+
+/*
+ * data cache only for ColdFire V4 such as MCF547x_8x, MCF5445x
+ * the dcache will be dummy in ColdFire V2 and V3
+ */
+void dcache_enable(void)
+{
+	dcache_invalid();
+	*cf_dcache_status = 1;
+
+#ifdef CONFIG_CF_V4
+	__asm__ __volatile__("movec %0, %%acr0"::"r"(CONFIG_SYS_CACHE_ACR0));
+	__asm__ __volatile__("movec %0, %%acr1"::"r"(CONFIG_SYS_CACHE_ACR1));
+#elif defined(CONFIG_CF_V4e)
+	__asm__ __volatile__("movec %0, %%acr4"::"r"(CONFIG_SYS_CACHE_ACR4));
+	__asm__ __volatile__("movec %0, %%acr5"::"r"(CONFIG_SYS_CACHE_ACR5));
+
+#endif
+
+	__asm__ __volatile__("movec %0, %%cacr"::"r"(CONFIG_SYS_CACHE_DCACR));
+}
+
+void dcache_disable(void)
+{
+	u32 temp = 0;
+
+	*cf_dcache_status = 0;
+	dcache_invalid();
+
+	__asm__ __volatile__("movec %0, %%cacr"::"r"(temp));
+
+#ifdef CONFIG_CF_V4
+	__asm__ __volatile__("movec %0, %%acr0"::"r"(temp));
+	__asm__ __volatile__("movec %0, %%acr1"::"r"(temp));
+#elif defined(CONFIG_CF_V4e)
+	__asm__ __volatile__("movec %0, %%acr4"::"r"(temp));
+	__asm__ __volatile__("movec %0, %%acr5"::"r"(temp));
+
+#endif
+}
+
+void dcache_invalid(void)
+{
+#ifdef CONFIG_CF_V4
+	u32 temp;
+
+	temp = CONFIG_SYS_DCACHE_INV;
+	if (*cf_dcache_status)
+		temp |= CONFIG_SYS_CACHE_DCACR;
+	if (*cf_icache_status)
+		temp |= CONFIG_SYS_CACHE_ICACR;
+
+	__asm__ __volatile__("movec %0, %%cacr"::"r"(temp));
+#endif
+}