SoC overviews are getting repeated across board folders. So, Organize SoC overview at common location i.e. fsl-layerscape/doc Also move README.lsch2 and README.lsch3 in same folder. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>master
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SoC overview |
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1. LS1043A |
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2. LS2080A |
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LS1043A |
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--------- |
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The LS1043A integrated multicore processor combines four ARM Cortex-A53 |
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processor cores with datapath acceleration optimized for L2/3 packet |
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processing, single pass security offload and robust traffic management |
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and quality of service. |
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The LS1043A SoC includes the following function and features: |
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- Four 64-bit ARM Cortex-A53 CPUs |
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- 1 MB unified L2 Cache |
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- One 32-bit DDR3L/DDR4 SDRAM memory controllers with ECC and interleaving |
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support |
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- Data Path Acceleration Architecture (DPAA) incorporating acceleration the |
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the following functions: |
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- Packet parsing, classification, and distribution (FMan) |
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- Queue management for scheduling, packet sequencing, and congestion |
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management (QMan) |
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- Hardware buffer management for buffer allocation and de-allocation (BMan) |
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- Cryptography acceleration (SEC) |
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- Ethernet interfaces by FMan |
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- Up to 1 x XFI supporting 10G interface |
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- Up to 1 x QSGMII |
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- Up to 4 x SGMII supporting 1000Mbps |
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- Up to 2 x SGMII supporting 2500Mbps |
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- Up to 2 x RGMII supporting 1000Mbps |
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- High-speed peripheral interfaces |
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- Three PCIe 2.0 controllers, one supporting x4 operation |
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- One serial ATA (SATA 3.0) controllers |
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- Additional peripheral interfaces |
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- Three high-speed USB 3.0 controllers with integrated PHY |
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- Enhanced secure digital host controller (eSDXC/eMMC) |
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- Quad Serial Peripheral Interface (QSPI) Controller |
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- Serial peripheral interface (SPI) controller |
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- Four I2C controllers |
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- Two DUARTs |
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- Integrated flash controller supporting NAND and NOR flash |
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- QorIQ platform's trust architecture 2.1 |
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LS2080A |
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-------- |
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The LS2080A integrated multicore processor combines eight ARM Cortex-A57 |
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processor cores with high-performance data path acceleration logic and network |
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and peripheral bus interfaces required for networking, telecom/datacom, |
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wireless infrastructure, and mil/aerospace applications. |
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|
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The LS2080A SoC includes the following function and features: |
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|
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- Eight 64-bit ARM Cortex-A57 CPUs |
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- 1 MB platform cache with ECC |
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- Two 64-bit DDR4 SDRAM memory controllers with ECC and interleaving support |
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- One secondary 32-bit DDR4 SDRAM memory controller, intended for use by |
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the AIOP |
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- Data path acceleration architecture (DPAA2) incorporating acceleration for |
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the following functions: |
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- Packet parsing, classification, and distribution (WRIOP) |
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- Queue and Hardware buffer management for scheduling, packet sequencing, and |
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congestion management, buffer allocation and de-allocation (QBMan) |
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- Cryptography acceleration (SEC) at up to 10 Gbps |
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- RegEx pattern matching acceleration (PME) at up to 10 Gbps |
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- Decompression/compression acceleration (DCE) at up to 20 Gbps |
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- Accelerated I/O processing (AIOP) at up to 20 Gbps |
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- QDMA engine |
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- 16 SerDes lanes at up to 10.3125 GHz |
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- Ethernet interfaces |
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- Up to eight 10 Gbps Ethernet MACs |
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- Up to eight 1 / 2.5 Gbps Ethernet MACs |
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- High-speed peripheral interfaces |
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- Four PCIe 3.0 controllers, one supporting SR-IOV |
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- Additional peripheral interfaces |
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- Two serial ATA (SATA 3.0) controllers |
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- Two high-speed USB 3.0 controllers with integrated PHY |
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- Enhanced secure digital host controller (eSDXC/eMMC) |
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- Serial peripheral interface (SPI) controller |
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- Quad Serial Peripheral Interface (QSPI) Controller |
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- Four I2C controllers |
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- Two DUARTs |
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- Integrated flash controller (IFC 2.0) supporting NAND and NOR flash |
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- Support for hardware virtualization and partitioning enforcement |
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- QorIQ platform's trust architecture 3.0 |
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- Service processor (SP) provides pre-boot initialization and secure-boot |
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capabilities |
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