Wolfgang Denk
16 years ago
commit
dfc91c3395
@ -1,343 +0,0 @@ |
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/*
|
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* (C) Copyright 2002 |
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
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* Alex Zuepke <azu@sysgo.de> |
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* |
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* (C) Copyright 2005 |
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* 2N Telekomunikace, a.s. <www.2n.cz> |
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* Ladislav Michl <michl@2n.cz> |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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|
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#include <common.h> |
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/*#if 0 */ |
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#if (PHYS_SDRAM_1_SIZE != SZ_32M) |
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#include "crcek.h" |
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#if (CONFIG_SYS_MAX_FLASH_BANKS > 1) |
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#error There is always only _one_ flash chip |
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#endif |
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flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; |
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#define CMD_READ_ARRAY 0x000000f0 |
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#define CMD_UNLOCK1 0x000000aa |
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#define CMD_UNLOCK2 0x00000055 |
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#define CMD_ERASE_SETUP 0x00000080 |
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#define CMD_ERASE_CONFIRM 0x00000030 |
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#define CMD_PROGRAM 0x000000a0 |
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#define CMD_UNLOCK_BYPASS 0x00000020 |
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#define MEM_FLASH_ADDR1 (*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x00000555 << 1))) |
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#define MEM_FLASH_ADDR2 (*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x000002aa << 1))) |
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|
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#define BIT_ERASE_DONE 0x00000080 |
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#define BIT_RDY_MASK 0x00000080 |
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#define BIT_PROGRAM_ERROR 0x00000020 |
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#define BIT_TIMEOUT 0x80000000 /* our flag */ |
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|
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/*-----------------------------------------------------------------------
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*/ |
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ulong flash_init(void) |
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{ |
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int i; |
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flash_info[0].flash_id = (AMD_MANUFACT & FLASH_VENDMASK) | |
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(AMD_ID_LV800B & FLASH_TYPEMASK); |
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flash_info[0].size = PHYS_FLASH_1_SIZE; |
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flash_info[0].sector_count = CONFIG_SYS_MAX_FLASH_SECT; |
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memset(flash_info[0].protect, 0, CONFIG_SYS_MAX_FLASH_SECT); |
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for (i = 0; i < flash_info[0].sector_count; i++) { |
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switch (i) { |
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case 0: /* 16kB */ |
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flash_info[0].start[0] = CONFIG_SYS_FLASH_BASE; |
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break; |
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case 1: /* 8kB */ |
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flash_info[0].start[1] = CONFIG_SYS_FLASH_BASE + 0x4000; |
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break; |
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case 2: /* 8kB */ |
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flash_info[0].start[2] = CONFIG_SYS_FLASH_BASE + 0x4000 + |
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0x2000; |
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break; |
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case 3: /* 32 KB */ |
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flash_info[0].start[3] = CONFIG_SYS_FLASH_BASE + 0x4000 + |
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2 * 0x2000; |
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break; |
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case 4: |
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flash_info[0].start[4] = CONFIG_SYS_FLASH_BASE + 0x4000 + |
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2 * 0x2000 + 0x8000; |
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break; |
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default: /* 64kB */ |
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flash_info[0].start[i] = flash_info[0].start[i-1] + |
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0x10000; |
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break; |
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} |
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} |
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|
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/* U-Boot */ |
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flash_protect(FLAG_PROTECT_SET, |
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LOADER1_OFFSET, |
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LOADER1_OFFSET + LOADER_SIZE - 1, flash_info); |
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/* Protect crcek, env and r_env as well */ |
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flash_protect(FLAG_PROTECT_SET, 0, 0x8000 - 1, flash_info); |
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return flash_info[0].size; |
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} |
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|
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/*-----------------------------------------------------------------------
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*/ |
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void flash_print_info(flash_info_t *info) |
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{ |
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int i; |
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switch (info->flash_id & FLASH_VENDMASK) { |
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case (AMD_MANUFACT & FLASH_VENDMASK): |
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puts("AMD: "); |
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break; |
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default: |
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puts("Unknown vendor "); |
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break; |
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} |
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switch (info->flash_id & FLASH_TYPEMASK) { |
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case (AMD_ID_LV800B & FLASH_TYPEMASK): |
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puts("AM29LV800BB (8Mb)\n"); |
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break; |
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default: |
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puts("Unknown chip type\n"); |
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return; |
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} |
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printf(" Size: %ld MB in %d sectors\n", |
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info->size >> 20, info->sector_count); |
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puts(" Sector start addresses:"); |
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for (i = 0; i < info->sector_count; i++) { |
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if ((i % 5) == 0) |
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puts("\n "); |
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printf(" %08lX%s", info->start[i], |
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info->protect[i] ? " (RO)" : " "); |
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} |
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puts("\n"); |
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} |
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/*-----------------------------------------------------------------------
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*/ |
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int flash_erase(flash_info_t *info, int s_first, int s_last) |
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{ |
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ushort result; |
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int prot, sect; |
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int rc = ERR_OK; |
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/* first look for protection bits */ |
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if (info->flash_id == FLASH_UNKNOWN) |
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return ERR_UNKNOWN_FLASH_TYPE; |
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if ((s_first < 0) || (s_first > s_last)) |
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return ERR_INVAL; |
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if ((info->flash_id & FLASH_VENDMASK) != |
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(AMD_MANUFACT & FLASH_VENDMASK)) |
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return ERR_UNKNOWN_FLASH_VENDOR; |
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prot = 0; |
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for (sect = s_first; sect <= s_last; ++sect) |
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if (info->protect[sect]) |
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prot++; |
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if (prot) |
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printf("- Warning: %d protected sectors will not be erased!\n", |
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prot); |
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else |
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putc('\n'); |
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/* Start erase on unprotected sectors */ |
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for (sect = s_first; sect <= s_last && !ctrlc (); sect++) { |
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if (info->protect[sect] == 0) { /* not protected */ |
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vu_short *addr = (vu_short *) (info->start[sect]); |
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/* arm simple, non interrupt dependent timer */ |
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reset_timer_masked(); |
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MEM_FLASH_ADDR1 = CMD_UNLOCK1; |
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MEM_FLASH_ADDR2 = CMD_UNLOCK2; |
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MEM_FLASH_ADDR1 = CMD_ERASE_SETUP; |
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MEM_FLASH_ADDR1 = CMD_UNLOCK1; |
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MEM_FLASH_ADDR2 = CMD_UNLOCK2; |
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*addr = CMD_ERASE_CONFIRM; |
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/* wait until flash is ready */ |
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while (1) { |
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result = *addr; |
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/* check timeout */ |
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if (get_timer_masked() > CONFIG_SYS_FLASH_ERASE_TOUT) { |
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MEM_FLASH_ADDR1 = CMD_READ_ARRAY; |
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rc = ERR_TIMOUT; |
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break; |
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} |
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if ((result & 0xfff) & BIT_ERASE_DONE) |
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break; |
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if ((result & 0xffff) & BIT_PROGRAM_ERROR) { |
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rc = ERR_PROG_ERROR; |
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break; |
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} |
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} |
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MEM_FLASH_ADDR1 = CMD_READ_ARRAY; |
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if (rc != ERR_OK) |
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goto out; |
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putc('.'); |
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} |
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} |
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out: |
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/* allow flash to settle - wait 10 ms */ |
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udelay_masked(10000); |
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return rc; |
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} |
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/*-----------------------------------------------------------------------
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* Copy memory to flash |
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*/ |
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static int write_hword(flash_info_t *info, ulong dest, ushort data) |
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{ |
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vu_short *addr = (vu_short *) dest; |
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ushort result; |
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int rc = ERR_OK; |
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/* check if flash is (sufficiently) erased */ |
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result = *addr; |
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if ((result & data) != data) |
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return ERR_NOT_ERASED; |
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MEM_FLASH_ADDR1 = CMD_UNLOCK1; |
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MEM_FLASH_ADDR2 = CMD_UNLOCK2; |
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MEM_FLASH_ADDR1 = CMD_PROGRAM; |
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*addr = data; |
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/* arm simple, non interrupt dependent timer */ |
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reset_timer_masked(); |
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/* wait until flash is ready */ |
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while (1) { |
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result = *addr; |
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/* check timeout */ |
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if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) { |
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rc = ERR_TIMOUT; |
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break; |
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} |
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if ((result & 0x80) == (data & 0x80)) |
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break; |
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if ((result & 0xffff) & BIT_PROGRAM_ERROR) { |
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result = *addr; |
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if ((result & 0x80) != (data & 0x80)) |
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rc = ERR_PROG_ERROR; |
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} |
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} |
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*addr = CMD_READ_ARRAY; |
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if (*addr != data) |
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rc = ERR_PROG_ERROR; |
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return rc; |
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} |
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/*-----------------------------------------------------------------------
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* Copy memory to flash. |
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*/ |
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int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt) |
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{ |
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ulong cp, wp; |
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int l; |
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int i, rc; |
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ushort data; |
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wp = (addr & ~1); /* get lower word aligned address */ |
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/*
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* handle unaligned start bytes |
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*/ |
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if ((l = addr - wp) != 0) { |
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data = 0; |
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for (i = 0, cp = wp; i < l; ++i, ++cp) |
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data = (data >> 8) | (*(uchar *) cp << 8); |
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for (; i < 2 && cnt > 0; ++i) { |
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data = (data >> 8) | (*src++ << 8); |
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--cnt; |
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++cp; |
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} |
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for (; cnt == 0 && i < 2; ++i, ++cp) |
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data = (data >> 8) | (*(uchar *) cp << 8); |
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if ((rc = write_hword(info, wp, data)) != 0) |
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return (rc); |
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wp += 2; |
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} |
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/*
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* handle word aligned part |
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*/ |
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while (cnt >= 2) { |
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data = *((vu_short *) src); |
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if ((rc = write_hword(info, wp, data)) != 0) |
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return (rc); |
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src += 2; |
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wp += 2; |
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cnt -= 2; |
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} |
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if (cnt == 0) |
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return ERR_OK; |
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/*
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* handle unaligned tail bytes |
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*/ |
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data = 0; |
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for (i = 0, cp = wp; i < 2 && cnt > 0; ++i, ++cp) { |
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data = (data >> 8) | (*src++ << 8); |
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--cnt; |
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} |
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for (; i < 2; ++i, ++cp) |
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data = (data >> 8) | (*(uchar *) cp << 8); |
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return write_hword(info, wp, data); |
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} |
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#endif |
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@ -1,62 +0,0 @@ |
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/*
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* (C) Copyright 2005 2N TELEKOMUNIKACE, Ladislav Michl |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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#include <asm/io.h> |
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#if defined(CONFIG_CMD_NAND) |
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#include <nand.h> |
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/*
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* hardware specific access to control-lines |
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*/ |
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#define MASK_CLE 0x02 |
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#define MASK_ALE 0x04 |
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static void netstar_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) |
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{ |
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struct nand_chip *this = mtd->priv; |
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ulong IO_ADDR_W = (ulong) this->IO_ADDR_W; |
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IO_ADDR_W &= ~(MASK_ALE|MASK_CLE); |
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if (ctrl & NAND_CTRL_CHANGE) { |
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if ( ctrl & NAND_CLE ) |
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IO_ADDR_W |= MASK_CLE; |
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if ( ctrl & NAND_ALE ) |
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IO_ADDR_W |= MASK_ALE; |
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} |
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this->IO_ADDR_W = (void __iomem *) IO_ADDR_W; |
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if (cmd != NAND_CMD_NONE) |
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writeb(cmd, this->IO_ADDR_W); |
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} |
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int board_nand_init(struct nand_chip *nand) |
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{ |
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nand->options = NAND_SAMSUNG_LP_OPTIONS; |
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nand->ecc.mode = NAND_ECC_SOFT; |
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nand->cmd_ctrl = netstar_nand_hwcontrol; |
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nand->chip_delay = 400; |
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return 0; |
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} |
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#endif |
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@ -0,0 +1,46 @@ |
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#
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# (C) Copyright 2000-2008
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
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#
|
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# See file CREDITS for list of people who contributed to this
|
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# project.
|
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#
|
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# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
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#
|
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# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
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# MA 02111-1307 USA
|
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#
|
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|
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include $(TOPDIR)/config.mk |
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|
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LIB = $(obj)lib$(SOC).a
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|
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COBJS-y += cache.o
|
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|
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SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
|
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OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y))
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|
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all: $(obj).depend $(LIB) |
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|
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$(LIB): $(OBJS) |
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$(AR) $(ARFLAGS) $@ $(OBJS)
|
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|
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#########################################################################
|
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|
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk |
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|
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sinclude $(obj).depend |
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|
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#########################################################################
|
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|
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@ -0,0 +1,86 @@ |
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/*
|
||||
* (C) Copyright 2002 |
||||
* Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
||||
* Marius Groeger <mgroeger@sysgo.de> |
||||
* |
||||
* (C) Copyright 2002 |
||||
* Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
||||
* Alex Zuepke <azu@sysgo.de> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
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#include <common.h> |
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#include <asm/hardware.h> |
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|
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void icache_enable (void) |
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{ |
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s32 i; |
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|
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/* disable all cache bits */ |
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CLR_REG( REG_SYSCFG, 0x3F); |
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|
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/* 8KB cache, write enable */ |
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SET_REG( REG_SYSCFG, CACHE_WRITE_BUFF | CACHE_MODE_01); |
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|
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/* clear TAG RAM bits */ |
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for ( i = 0; i < 256; i++) |
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PUT_REG( CACHE_TAG_RAM + 4*i, 0x00000000); |
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|
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/* clear SET0 RAM */ |
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for(i=0; i < 1024; i++) |
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PUT_REG( CACHE_SET0_RAM + 4*i, 0x00000000); |
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|
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/* clear SET1 RAM */ |
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for(i=0; i < 1024; i++) |
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PUT_REG( CACHE_SET1_RAM + 4*i, 0x00000000); |
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|
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/* enable cache */ |
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SET_REG( REG_SYSCFG, CACHE_ENABLE); |
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|
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} |
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|
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void icache_disable (void) |
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{ |
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/* disable all cache bits */ |
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CLR_REG( REG_SYSCFG, 0x3F); |
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} |
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|
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int icache_status (void) |
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{ |
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return GET_REG( REG_SYSCFG) & CACHE_ENABLE; |
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} |
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|
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void dcache_enable (void) |
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{ |
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/* we don't have seperate instruction/data caches */ |
||||
icache_enable(); |
||||
} |
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|
||||
void dcache_disable (void) |
||||
{ |
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/* we don't have seperate instruction/data caches */ |
||||
icache_disable(); |
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} |
||||
|
||||
int dcache_status (void) |
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{ |
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/* we don't have seperate instruction/data caches */ |
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return icache_status(); |
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} |
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@ -0,0 +1,91 @@ |
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/*
|
||||
* (C) Copyright 2004 |
||||
* DAVE Srl |
||||
* http://www.dave-tech.it
|
||||
* http://www.wawnet.biz
|
||||
* mailto:info@wawnet.biz |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <command.h> |
||||
#include <asm/hardware.h> |
||||
|
||||
static void s3c44b0_flush_cache(void) |
||||
{ |
||||
volatile int i; |
||||
/* flush cycle */ |
||||
for(i=0x10002000;i<0x10004800;i+=16) |
||||
{ |
||||
*((int *)i)=0x0; |
||||
} |
||||
} |
||||
|
||||
void icache_enable (void) |
||||
{ |
||||
ulong reg; |
||||
|
||||
s3c44b0_flush_cache(); |
||||
|
||||
/*
|
||||
Init cache |
||||
Non-cacheable area (everything outside RAM) |
||||
0x0000:0000 - 0x0C00:0000 |
||||
*/ |
||||
NCACHBE0 = 0xC0000000; |
||||
NCACHBE1 = 0x00000000; |
||||
|
||||
/*
|
||||
Enable chache |
||||
*/ |
||||
reg = SYSCFG; |
||||
reg |= 0x00000006; /* 8kB */ |
||||
SYSCFG = reg; |
||||
} |
||||
|
||||
void icache_disable (void) |
||||
{ |
||||
ulong reg; |
||||
|
||||
reg = SYSCFG; |
||||
reg &= ~0x00000006; /* 8kB */ |
||||
SYSCFG = reg; |
||||
} |
||||
|
||||
int icache_status (void) |
||||
{ |
||||
return 0; |
||||
} |
||||
|
||||
void dcache_enable (void) |
||||
{ |
||||
icache_enable(); |
||||
} |
||||
|
||||
void dcache_disable (void) |
||||
{ |
||||
icache_disable(); |
||||
} |
||||
|
||||
int dcache_status (void) |
||||
{ |
||||
return dcache_status(); |
||||
} |
||||
|
||||
@ -0,0 +1,315 @@ |
||||
/*
|
||||
* (C) Copyright 2004 |
||||
* DAVE Srl |
||||
* http://www.dave-tech.it
|
||||
* http://www.wawnet.biz
|
||||
* mailto:info@wawnet.biz |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <command.h> |
||||
#include <asm/hardware.h> |
||||
|
||||
/*
|
||||
* Initialization, must be called once on start up, may be called |
||||
* repeatedly to change the speed and slave addresses. |
||||
*/ |
||||
void i2c_init(int speed, int slaveaddr) |
||||
{ |
||||
/*
|
||||
setting up I2C support |
||||
*/ |
||||
unsigned int save_F,save_PF,rIICCON,rPCONA,rPDATA,rPCONF,rPUPF; |
||||
|
||||
save_F = PCONF; |
||||
save_PF = PUPF; |
||||
|
||||
rPCONF = ((save_F & ~(0xF))| 0xa); |
||||
rPUPF = (save_PF | 0x3); |
||||
PCONF = rPCONF; /*PF0:IICSCL, PF1:IICSDA*/ |
||||
PUPF = rPUPF; /* Disable pull-up */ |
||||
|
||||
/* Configuring pin for WC pin of EEprom */ |
||||
rPCONA = PCONA; |
||||
rPCONA &= ~(1<<9); |
||||
PCONA = rPCONA; |
||||
|
||||
rPDATA = PDATA; |
||||
rPDATA &= ~(1<<9); |
||||
PDATA = rPDATA; |
||||
|
||||
/*
|
||||
Enable ACK, IICCLK=MCLK/16, enable interrupt |
||||
75MHz/16/(12+1) = 390625 Hz |
||||
*/ |
||||
rIICCON=(1<<7)|(0<<6)|(1<<5)|(0xC); |
||||
IICCON = rIICCON; |
||||
|
||||
IICADD = slaveaddr; |
||||
} |
||||
|
||||
/*
|
||||
* Probe the given I2C chip address. Returns 0 if a chip responded, |
||||
* not 0 on failure. |
||||
*/ |
||||
int i2c_probe(uchar chip) |
||||
{ |
||||
/*
|
||||
not implemented |
||||
*/ |
||||
|
||||
printf("i2c_probe chip %d\n", (int) chip); |
||||
return -1; |
||||
} |
||||
|
||||
/*
|
||||
* Read/Write interface: |
||||
* chip: I2C chip address, range 0..127 |
||||
* addr: Memory (register) address within the chip |
||||
* alen: Number of bytes to use for addr (typically 1, 2 for larger |
||||
* memories, 0 for register type devices with only one |
||||
* register) |
||||
* buffer: Where to read/write the data |
||||
* len: How many bytes to read/write |
||||
* |
||||
* Returns: 0 on success, not 0 on failure |
||||
*/ |
||||
|
||||
#define S3C44B0X_rIIC_INTPEND (1<<4) |
||||
#define S3C44B0X_rIIC_LAST_RECEIV_BIT (1<<0) |
||||
#define S3C44B0X_rIIC_INTERRUPT_ENABLE (1<<5) |
||||
#define S3C44B0_IIC_TIMEOUT 100 |
||||
|
||||
int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) |
||||
{ |
||||
|
||||
int k, j, temp; |
||||
u32 rIICSTAT; |
||||
|
||||
/*
|
||||
send the device offset |
||||
*/ |
||||
|
||||
rIICSTAT = 0xD0; |
||||
IICSTAT = rIICSTAT; |
||||
|
||||
IICDS = chip; /* this is a write operation... */ |
||||
|
||||
rIICSTAT |= (1<<5); |
||||
IICSTAT = rIICSTAT; |
||||
|
||||
for(k=0; k<S3C44B0_IIC_TIMEOUT; k++) { |
||||
temp = IICCON; |
||||
if( (temp & S3C44B0X_rIIC_INTPEND) == S3C44B0X_rIIC_INTPEND) |
||||
break; |
||||
udelay(2000); |
||||
} |
||||
if (k==S3C44B0_IIC_TIMEOUT) |
||||
return -1; |
||||
|
||||
/* wait and check ACK */ |
||||
temp = IICSTAT; |
||||
if ((temp & S3C44B0X_rIIC_LAST_RECEIV_BIT) == S3C44B0X_rIIC_LAST_RECEIV_BIT ) |
||||
return -1; |
||||
|
||||
IICDS = addr; |
||||
IICCON = IICCON & ~(S3C44B0X_rIIC_INTPEND); |
||||
|
||||
/* wait and check ACK */ |
||||
for(k=0; k<S3C44B0_IIC_TIMEOUT; k++) { |
||||
temp = IICCON; |
||||
if( (temp & S3C44B0X_rIIC_INTPEND) == S3C44B0X_rIIC_INTPEND) |
||||
break; |
||||
udelay(2000); |
||||
} |
||||
if (k==S3C44B0_IIC_TIMEOUT) |
||||
return -1; |
||||
|
||||
temp = IICSTAT; |
||||
if ((temp & S3C44B0X_rIIC_LAST_RECEIV_BIT) == S3C44B0X_rIIC_LAST_RECEIV_BIT ) |
||||
return -1; |
||||
|
||||
/*
|
||||
now we can start with the read operation... |
||||
*/ |
||||
|
||||
IICDS = chip | 0x01; /* this is a read operation... */ |
||||
|
||||
rIICSTAT = 0x90; /*master recv*/ |
||||
rIICSTAT |= (1<<5); |
||||
IICSTAT = rIICSTAT; |
||||
|
||||
IICCON = IICCON & ~(S3C44B0X_rIIC_INTPEND); |
||||
|
||||
/* wait and check ACK */ |
||||
for(k=0; k<S3C44B0_IIC_TIMEOUT; k++) { |
||||
temp = IICCON; |
||||
if( (temp & S3C44B0X_rIIC_INTPEND) == S3C44B0X_rIIC_INTPEND) |
||||
break; |
||||
udelay(2000); |
||||
} |
||||
if (k==S3C44B0_IIC_TIMEOUT) |
||||
return -1; |
||||
|
||||
temp = IICSTAT; |
||||
if ((temp & S3C44B0X_rIIC_LAST_RECEIV_BIT) == S3C44B0X_rIIC_LAST_RECEIV_BIT ) |
||||
return -1; |
||||
|
||||
for (j=0; j<len-1; j++) { |
||||
|
||||
/*clear pending bit to resume */ |
||||
|
||||
temp = IICCON & ~(S3C44B0X_rIIC_INTPEND); |
||||
IICCON = temp; |
||||
|
||||
/* wait and check ACK */ |
||||
for(k=0; k<S3C44B0_IIC_TIMEOUT; k++) { |
||||
temp = IICCON; |
||||
if( (temp & S3C44B0X_rIIC_INTPEND) == S3C44B0X_rIIC_INTPEND) |
||||
break; |
||||
udelay(2000); |
||||
} |
||||
if (k==S3C44B0_IIC_TIMEOUT) |
||||
return -1; |
||||
|
||||
|
||||
buffer[j] = IICDS; /*save readed data*/ |
||||
|
||||
} /*end for(j)*/ |
||||
|
||||
/*
|
||||
reading the last data |
||||
unset ACK generation |
||||
*/ |
||||
temp = IICCON & ~(S3C44B0X_rIIC_INTPEND | (1<<7)); |
||||
IICCON = temp; |
||||
|
||||
/* wait but NOT check ACK */ |
||||
for(k=0; k<S3C44B0_IIC_TIMEOUT; k++) { |
||||
temp = IICCON; |
||||
if( (temp & S3C44B0X_rIIC_INTPEND) == S3C44B0X_rIIC_INTPEND) |
||||
break; |
||||
udelay(2000); |
||||
} |
||||
if (k==S3C44B0_IIC_TIMEOUT) |
||||
return -1; |
||||
|
||||
buffer[j] = IICDS; /*save readed data*/ |
||||
|
||||
rIICSTAT = 0x90; /*master recv*/ |
||||
|
||||
/* Write operation Terminate sending STOP */ |
||||
IICSTAT = rIICSTAT; |
||||
/*Clear Int Pending Bit to RESUME*/ |
||||
temp = IICCON; |
||||
IICCON = temp & (~S3C44B0X_rIIC_INTPEND); |
||||
|
||||
IICCON = IICCON | (1<<7); /*restore ACK generation*/ |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) |
||||
{ |
||||
int j, k; |
||||
u32 rIICSTAT, temp; |
||||
|
||||
|
||||
/*
|
||||
send the device offset |
||||
*/ |
||||
|
||||
rIICSTAT = 0xD0; |
||||
IICSTAT = rIICSTAT; |
||||
|
||||
IICDS = chip; /* this is a write operation... */ |
||||
|
||||
rIICSTAT |= (1<<5); |
||||
IICSTAT = rIICSTAT; |
||||
|
||||
IICCON = IICCON & ~(S3C44B0X_rIIC_INTPEND); |
||||
|
||||
/* wait and check ACK */ |
||||
for(k=0; k<S3C44B0_IIC_TIMEOUT; k++) { |
||||
temp = IICCON; |
||||
if( (temp & S3C44B0X_rIIC_INTPEND) == S3C44B0X_rIIC_INTPEND) |
||||
break; |
||||
udelay(2000); |
||||
} |
||||
if (k==S3C44B0_IIC_TIMEOUT) |
||||
return -1; |
||||
|
||||
temp = IICSTAT; |
||||
if ((temp & S3C44B0X_rIIC_LAST_RECEIV_BIT) == S3C44B0X_rIIC_LAST_RECEIV_BIT ) |
||||
return -1; |
||||
|
||||
IICDS = addr; |
||||
IICCON = IICCON & ~(S3C44B0X_rIIC_INTPEND); |
||||
|
||||
/* wait and check ACK */ |
||||
for(k=0; k<S3C44B0_IIC_TIMEOUT; k++) { |
||||
temp = IICCON; |
||||
if( (temp & S3C44B0X_rIIC_INTPEND) == S3C44B0X_rIIC_INTPEND) |
||||
break; |
||||
udelay(2000); |
||||
} |
||||
if (k==S3C44B0_IIC_TIMEOUT) |
||||
return -1; |
||||
|
||||
temp = IICSTAT; |
||||
if ((temp & S3C44B0X_rIIC_LAST_RECEIV_BIT) == S3C44B0X_rIIC_LAST_RECEIV_BIT ) |
||||
return -1; |
||||
|
||||
/*
|
||||
now we can start with the read write operation |
||||
*/ |
||||
for (j=0; j<len; j++) { |
||||
|
||||
IICDS = buffer[j]; /*prerare data to write*/ |
||||
|
||||
/*clear pending bit to resume*/ |
||||
|
||||
temp = IICCON & ~(S3C44B0X_rIIC_INTPEND); |
||||
IICCON = temp; |
||||
|
||||
/* wait but NOT check ACK */ |
||||
for(k=0; k<S3C44B0_IIC_TIMEOUT; k++) { |
||||
temp = IICCON; |
||||
if( (temp & S3C44B0X_rIIC_INTPEND) == S3C44B0X_rIIC_INTPEND) |
||||
break; |
||||
|
||||
udelay(2000); |
||||
} |
||||
|
||||
if (k==S3C44B0_IIC_TIMEOUT) |
||||
return -1; |
||||
|
||||
} /* end for(j) */ |
||||
|
||||
/* sending stop to terminate */ |
||||
rIICSTAT = 0xD0; /*master send*/ |
||||
IICSTAT = rIICSTAT; |
||||
/*Clear Int Pending Bit to RESUME*/ |
||||
temp = IICCON; |
||||
IICCON = temp & (~S3C44B0X_rIIC_INTPEND); |
||||
|
||||
return 0; |
||||
} |
||||
@ -0,0 +1,102 @@ |
||||
/*
|
||||
* (C) Copyright 2004 |
||||
* DAVE Srl |
||||
* http://www.dave-tech.it
|
||||
* http://www.wawnet.biz
|
||||
* mailto:info@wawnet.biz |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
/*
|
||||
* S3C44B0 CPU specific code |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <command.h> |
||||
#include <asm/hardware.h> |
||||
#include <rtc.h> |
||||
#include <bcd.h> |
||||
|
||||
int rtc_get (struct rtc_time* tm) |
||||
{ |
||||
RTCCON |= 1; |
||||
tm->tm_year = BCD2BIN(BCDYEAR); |
||||
tm->tm_mon = BCD2BIN(BCDMON); |
||||
tm->tm_wday = BCD2BIN(BCDDATE); |
||||
tm->tm_mday = BCD2BIN(BCDDAY); |
||||
tm->tm_hour = BCD2BIN(BCDHOUR); |
||||
tm->tm_min = BCD2BIN(BCDMIN); |
||||
tm->tm_sec = BCD2BIN(BCDSEC); |
||||
|
||||
if (tm->tm_sec==0) { |
||||
/* we have to re-read the rtc data because of the "one second deviation" problem */ |
||||
/* see RTC datasheet for more info about it */ |
||||
tm->tm_year = BCD2BIN(BCDYEAR); |
||||
tm->tm_mon = BCD2BIN(BCDMON); |
||||
tm->tm_mday = BCD2BIN(BCDDAY); |
||||
tm->tm_wday = BCD2BIN(BCDDATE); |
||||
tm->tm_hour = BCD2BIN(BCDHOUR); |
||||
tm->tm_min = BCD2BIN(BCDMIN); |
||||
tm->tm_sec = BCD2BIN(BCDSEC); |
||||
} |
||||
|
||||
RTCCON &= ~1; |
||||
|
||||
if(tm->tm_year >= 70) |
||||
tm->tm_year += 1900; |
||||
else |
||||
tm->tm_year += 2000; |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int rtc_set (struct rtc_time* tm) |
||||
{ |
||||
if(tm->tm_year < 2000) |
||||
tm->tm_year -= 1900; |
||||
else |
||||
tm->tm_year -= 2000; |
||||
|
||||
RTCCON |= 1; |
||||
BCDYEAR = BIN2BCD(tm->tm_year); |
||||
BCDMON = BIN2BCD(tm->tm_mon); |
||||
BCDDAY = BIN2BCD(tm->tm_mday); |
||||
BCDDATE = BIN2BCD(tm->tm_wday); |
||||
BCDHOUR = BIN2BCD(tm->tm_hour); |
||||
BCDMIN = BIN2BCD(tm->tm_min); |
||||
BCDSEC = BIN2BCD(tm->tm_sec); |
||||
RTCCON &= 1; |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
void rtc_reset (void) |
||||
{ |
||||
RTCCON |= 1; |
||||
BCDYEAR = 0; |
||||
BCDMON = 0; |
||||
BCDDAY = 0; |
||||
BCDDATE = 0; |
||||
BCDHOUR = 0; |
||||
BCDMIN = 0; |
||||
BCDSEC = 0; |
||||
RTCCON &= 1; |
||||
} |
||||
|
||||
@ -0,0 +1,105 @@ |
||||
/*
|
||||
* (C) Copyright 2002-2004 |
||||
* Wolfgang Denk, DENX Software Engineering, <wd@denx.de> |
||||
* |
||||
* (C) Copyright 2002 |
||||
* Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
||||
* Marius Groeger <mgroeger@sysgo.de> |
||||
* |
||||
* (C) Copyright 2002 |
||||
* Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
||||
* Alex Zuepke <azu@sysgo.de> |
||||
* |
||||
* Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License as published by |
||||
* the Free Software Foundation; either version 2 of the License, or |
||||
* (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
||||
* |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/arch/hardware.h> |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
void serial_setbrg (void) |
||||
{ |
||||
unsigned short divisor = 0; |
||||
|
||||
switch (gd->baudrate) { |
||||
case 1200: divisor = 3072; break; |
||||
case 9600: divisor = 384; break; |
||||
case 19200: divisor = 192; break; |
||||
case 38400: divisor = 96; break; |
||||
case 57600: divisor = 64; break; |
||||
case 115200: divisor = 32; break; |
||||
default: hang (); break; |
||||
} |
||||
|
||||
/* init serial UART0 */ |
||||
PUT8(U0LCR, 0); |
||||
PUT8(U0IER, 0); |
||||
PUT8(U0LCR, 0x80); /* DLAB=1 */ |
||||
PUT8(U0DLL, (unsigned char)(divisor & 0x00FF)); |
||||
PUT8(U0DLM, (unsigned char)(divisor >> 8)); |
||||
PUT8(U0LCR, 0x03); /* 8N1, DLAB=0 */ |
||||
PUT8(U0FCR, 1); /* Enable RX and TX FIFOs */ |
||||
} |
||||
|
||||
int serial_init (void) |
||||
{ |
||||
unsigned long pinsel0; |
||||
|
||||
serial_setbrg (); |
||||
|
||||
pinsel0 = GET32(PINSEL0); |
||||
pinsel0 &= ~(0x00000003); |
||||
pinsel0 |= 5; |
||||
PUT32(PINSEL0, pinsel0); |
||||
|
||||
return (0); |
||||
} |
||||
|
||||
void serial_putc (const char c) |
||||
{ |
||||
if (c == '\n') |
||||
{ |
||||
while((GET8(U0LSR) & (1<<5)) == 0); /* Wait for empty U0THR */ |
||||
PUT8(U0THR, '\r'); |
||||
} |
||||
|
||||
while((GET8(U0LSR) & (1<<5)) == 0); /* Wait for empty U0THR */ |
||||
PUT8(U0THR, c); |
||||
} |
||||
|
||||
int serial_getc (void) |
||||
{ |
||||
while((GET8(U0LSR) & 1) == 0); |
||||
return GET8(U0RBR); |
||||
} |
||||
|
||||
void |
||||
serial_puts (const char *s) |
||||
{ |
||||
while (*s) { |
||||
serial_putc (*s++); |
||||
} |
||||
} |
||||
|
||||
/* Test if there is a byte to read */ |
||||
int serial_tstc (void) |
||||
{ |
||||
return (GET8(U0LSR) & 1); |
||||
} |
||||
|
||||
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Reference in new issue