Salvator-x is an entry level development board based on R-Car H3 SoC (R8A7795). This commit supports SCIF only. Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>master
Nobuhiro Iwamatsu
9 years ago
parent
ee8f0cb3b0
commit
e525d34b47
@ -1,12 +1,28 @@ |
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if RCAR_GEN3 |
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config R8A7795 |
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bool |
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choice |
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prompt "Renesus ARM64 SoCs board select" |
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optional |
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config TARGET_SALVATOR_X |
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bool "Salvator-X board" |
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select R8A7795 |
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help |
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Support for Renesas R-Car Gen3 R8a7795 platform |
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endchoice |
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config SYS_SOC |
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default "rmobile" |
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config RCAR_GEN3_EXTRAM_BOOT |
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bool "Enable boot from RAM" |
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depends on TARGET_SALVATOR_X |
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default n |
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source "board/renesas/salvator-x/Kconfig" |
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endif |
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@ -0,0 +1,15 @@ |
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if TARGET_SALVATOR_X |
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config SYS_SOC |
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default "rmobile" |
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config SYS_BOARD |
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default "salvator-x" |
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config SYS_VENDOR |
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default "renesas" |
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config SYS_CONFIG_NAME |
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default "salvator-x" |
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endif |
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@ -0,0 +1,6 @@ |
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SALVATOR_X BOARD |
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M: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> |
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S: Maintained |
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F: board/renesas/salvator-x/ |
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F: include/configs/salvator-x.h |
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F: configs/salvator-x_defconfig |
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#
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# board/renesas/salvator-x/Makefile
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#
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# Copyright (C) 2015 Renesas Electronics Corporation
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y := salvator-x.o ../rcar-common/common.o
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@ -0,0 +1,120 @@ |
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/*
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* board/renesas/salvator-x/salvator-x.c |
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* This file is Salvator-X board support. |
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* |
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* Copyright (C) 2015 Renesas Electronics Corporation |
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* Copyright (C) 2015 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <malloc.h> |
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#include <netdev.h> |
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#include <dm.h> |
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#include <dm/platform_data/serial_sh.h> |
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#include <asm/processor.h> |
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#include <asm/mach-types.h> |
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#include <asm/io.h> |
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#include <asm/errno.h> |
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#include <asm/arch/sys_proto.h> |
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#include <asm/gpio.h> |
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#include <asm/arch/gpio.h> |
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#include <asm/arch/rmobile.h> |
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#include <asm/arch/rcar-mstp.h> |
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#include <i2c.h> |
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#include <mmc.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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#define CPGWPCR 0xE6150904 |
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#define CPGWPR 0xE615090C |
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#define CLK2MHZ(clk) (clk / 1000 / 1000) |
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void s_init(void) |
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{ |
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struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE; |
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struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE; |
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/* Watchdog init */ |
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writel(0xA5A5A500, &rwdt->rwtcsra); |
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writel(0xA5A5A500, &swdt->swtcsra); |
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writel(0xA5A50000, CPGWPCR); |
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writel(0xFFFFFFFF, CPGWPR); |
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} |
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#define GSX_MSTP112 (1 << 12) /* 3DG */ |
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#define TMU0_MSTP125 (1 << 25) /* secure */ |
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#define TMU1_MSTP124 (1 << 24) /* non-secure */ |
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#define SCIF2_MSTP310 (1 << 10) /* SCIF2 */ |
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int board_early_init_f(void) |
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{ |
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/* TMU0,1 */ /* which use ? */ |
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mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125 | TMU1_MSTP124); |
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/* SCIF2 */ |
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mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SCIF2_MSTP310); |
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return 0; |
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} |
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/* SYSC */ |
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/* R/- 32 Power status register 2(3DG) */ |
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#define SYSC_PWRSR2 0xE6180100 |
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/* -/W 32 Power resume control register 2 (3DG) */ |
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#define SYSC_PWRONCR2 0xE618010C |
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DECLARE_GLOBAL_DATA_PTR; |
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int board_init(void) |
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{ |
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/* adress of boot parameters */ |
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gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000; |
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/* Init PFC controller */ |
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r8a7795_pinmux_init(); |
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/* GSX: force power and clock supply */ |
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writel(0x0000001F, SYSC_PWRONCR2); |
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while (readl(SYSC_PWRSR2) != 0x000003E0) |
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mdelay(20); |
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mstp_clrbits_le32(MSTPSR1, SMSTPCR1, GSX_MSTP112); |
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return 0; |
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} |
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int dram_init(void) |
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{ |
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gd->ram_size = CONFIG_SYS_SDRAM_SIZE; |
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return 0; |
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} |
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const struct rmobile_sysinfo sysinfo = { |
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CONFIG_RCAR_BOARD_STRING |
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}; |
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#define RST_BASE 0xE6160000 |
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#define RST_CA57RESCNT (RST_BASE + 0x40) |
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#define RST_CA53RESCNT (RST_BASE + 0x44) |
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#define RST_RSTOUTCR (RST_BASE + 0x58) |
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#define RST_CODE 0xA5A5000F |
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void reset_cpu(ulong addr) |
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{ |
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/* only CA57 ? */ |
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writel(RST_CODE, RST_CA57RESCNT); |
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} |
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static const struct sh_serial_platdata serial_platdata = { |
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.base = SCIF2_BASE, |
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.type = PORT_SCIF, |
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.clk = 14745600, /* 0xE10000 */ |
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.clk_mode = EXT_CLK, |
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}; |
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U_BOOT_DEVICE(salvator_x_scif2) = { |
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.name = "serial_sh", |
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.platdata = &serial_platdata, |
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}; |
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@ -0,0 +1,4 @@ |
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CONFIG_ARM=y |
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CONFIG_RCAR_GEN3=y |
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CONFIG_TARGET_SALVATOR_X=y |
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CONFIG_SPL=y |
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@ -0,0 +1,105 @@ |
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/*
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* include/configs/rcar-gen3-common.h |
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* This file is R-Car Gen3 common configuration file. |
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* |
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* Copyright (C) 2015 Renesas Electronics Corporation |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef __RCAR_GEN3_COMMON_H |
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#define __RCAR_GEN3_COMMON_H |
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#include <asm/arch/rmobile.h> |
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#define CONFIG_CMD_BOOTI |
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#define CONFIG_CMD_EDITENV |
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#define CONFIG_CMD_SAVEENV |
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#define CONFIG_CMD_MEMORY |
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#define CONFIG_CMD_DFL |
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#define CONFIG_CMD_SDRAM |
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#define CONFIG_CMD_RUN |
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#define CONFIG_CMD_LOADS |
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#define CONFIG_CMD_BOOTZ |
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#define CONFIG_CMD_FAT |
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#define CONFIG_CMD_EXT2 |
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#define CONFIG_CMD_EXT4 |
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#define CONFIG_CMD_EXT4_WRITE |
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#define CONFIG_REMAKE_ELF |
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/* boot option */ |
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#define CONFIG_SUPPORT_RAW_INITRD |
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/* Support File sytems */ |
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#define CONFIG_FAT_WRITE |
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#define CONFIG_DOS_PARTITION |
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#define CONFIG_SUPPORT_VFAT |
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#define CONFIG_FS_EXT4 |
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#define CONFIG_EXT4_WRITE |
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#define CONFIG_CMDLINE_TAG |
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#define CONFIG_SETUP_MEMORY_TAGS |
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#define CONFIG_INITRD_TAG |
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#define CONFIG_CMDLINE_EDITING |
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#define CONFIG_OF_LIBFDT |
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#define CONFIG_BAUDRATE 115200 |
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#define CONFIG_BOOTDELAY 3 |
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#define CONFIG_VERSION_VARIABLE |
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#undef CONFIG_SHOW_BOOT_PROGRESS |
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#define CONFIG_ARCH_CPU_INIT |
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#define CONFIG_DISPLAY_CPUINFO |
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#define CONFIG_DISPLAY_BOARDINFO |
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#define CONFIG_BOARD_EARLY_INIT_F |
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#define CONFIG_SH_GPIO_PFC |
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/* console */ |
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#undef CONFIG_SYS_CONSOLE_INFO_QUIET |
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#undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE |
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#undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE |
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#define CONFIG_SYS_LONGHELP |
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#define CONFIG_SYS_CBSIZE 256 |
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#define CONFIG_SYS_PBSIZE 256 |
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#define CONFIG_SYS_MAXARGS 16 |
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#define CONFIG_SYS_BARGSIZE 512 |
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#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400 } |
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/* MEMORY */ |
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#define CONFIG_SYS_TEXT_BASE 0x49000000 |
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#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + 0x7fff0) |
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#define CONFIG_SYS_SDRAM_BASE (0x48000000) |
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#define CONFIG_SYS_SDRAM_SIZE (1024u * 1024 * 1024 - 0x08000000) |
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#define CONFIG_SYS_LOAD_ADDR (0x48080000) |
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#define CONFIG_NR_DRAM_BANKS 1 |
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#define CONFIG_SYS_MONITOR_BASE 0x00000000 |
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#define CONFIG_SYS_MONITOR_LEN (256 * 1024) |
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#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024) |
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#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) |
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/* ENV setting */ |
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#define CONFIG_ENV_OVERWRITE |
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#define CONFIG_ENV_SECT_SIZE (128 * 1024) |
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#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) |
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#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) |
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#define CONFIG_EXTRA_ENV_SETTINGS \ |
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"fdt_high=0xffffffffffffffff\0" \
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"initrd_high=0xffffffffffffffff\0" |
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#define CONFIG_BOOTARGS \ |
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"console=ttySC0,115200 rw root=/dev/nfs " \
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"nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20" |
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#define CONFIG_BOOTCOMMAND \ |
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"tftp 0x48080000 Image; " \
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"tftp 0x48000000 Image-r8a7795-salvator-x.dtb; " \
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"booti 0x48080000 - 0x48000000" |
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#endif /* __RCAR_GEN3_COMMON_H */ |
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@ -0,0 +1,54 @@ |
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/*
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* include/configs/salvator-x.h |
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* This file is Salvator-X board configuration. |
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* |
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* Copyright (C) 2015 Renesas Electronics Corporation |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef __SALVATOR_X_H |
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#define __SALVATOR_X_H |
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#undef DEBUG |
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#define CONFIG_RCAR_BOARD_STRING "Salvator-X" |
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#include "rcar-gen3-common.h" |
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/* SCIF */ |
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#define CONFIG_SCIF_CONSOLE |
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#define CONFIG_CONS_SCIF2 |
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#define CONFIG_CONS_INDEX 2 |
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#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ |
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/* [A] Hyper Flash */ |
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/* use to RPC(SPI Multi I/O Bus Controller) */ |
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#define CONFIG_SYS_NO_FLASH |
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#define CONFIG_ENV_IS_NOWHERE |
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/* Board Clock */ |
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/* XTAL_CLK : 33.33MHz */ |
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#define RCAR_XTAL_CLK 33333333u |
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#define CONFIG_SYS_CLK_FREQ RCAR_XTAL_CLK |
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/* ch0to2 CPclk, ch3to11 S3D2_PEREclk, ch12to14 S3D2_RTclk */ |
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/* CPclk 16.66MHz, S3D2 133.33MHz */ |
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#define CONFIG_CP_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) |
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#define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 192 / 2) |
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#define CONFIG_S3D2_CLK_FREQ (266666666u/2) |
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/* Generic Timer Definitions (use in assembler source) */ |
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#define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */ |
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/* Generic Interrupt Controller Definitions */ |
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#define CONFIG_GICV2 |
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#define GICD_BASE 0xF1010000 |
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#define GICC_BASE 0xF1020000 |
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/* Module stop status bits */ |
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/* MFIS, SCIF1 */ |
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#define CONFIG_SMSTP2_ENA 0x00002040 |
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/* INTC-AP, IRQC */ |
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#define CONFIG_SMSTP4_ENA 0x00000180 |
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#endif /* __SALVATOR_X_H */ |
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