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@ -38,6 +38,18 @@ |
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#define CONFIG_PPCHAMELEON_MODULE_MODEL CONFIG_PPCHAMELEON_MODULE_BA |
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#endif |
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/* Only one of the following two symbols must be defined (default is 25 MHz)
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* CONFIG_PPCHAMELEON_CLK_25 |
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* CONFIG_PPCHAMELEON_CLK_33 |
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*/ |
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#if (defined(CONFIG_PPCHAMELEON_CLK_25) && defined(CONFIG_PPCHAMELEON_CLK_33)) |
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#error "* Two external frequencies (SysClk) are defined! *" |
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#endif |
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#undef CONFIG_PPCHAMELEON_SMI712 |
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/*
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* Debug stuff |
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*/ |
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@ -60,7 +72,14 @@ |
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#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ |
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#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ |
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#ifdef CONFIG_PPCHAMELEON_CLK_25 |
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#define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */ |
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#elif (defined (CONFIG_PPCHAMELEON_CLK_33)) |
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#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ |
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#else |
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#error "* External frequency (SysClk) not defined! *" |
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#endif |
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#define CONFIG_BAUDRATE 115200 |
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#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ |
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@ -75,7 +94,6 @@ |
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
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#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
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#undef CONFIG_EXT_PHY |
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#define CONFIG_NET_MULTI 1 |
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@ -184,7 +202,6 @@ |
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#define CFG_NAND1_ALE (0x80000000 >> 16) /* our ALE is GPIO16 */ |
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#define CFG_NAND1_RDY (0x80000000 >> 31) /* our RDY is GPIO31 */ |
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#define NAND_DISABLE_CE(nand) do \ |
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{ \
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switch((unsigned long)(((struct nand_chip *)nand)->IO_ADDR)) \
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@ -211,7 +228,6 @@ |
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} \
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} while(0) |
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#define NAND_CTL_CLRALE(nandptr) do \ |
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{ \
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switch((unsigned long)nandptr) \
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@ -292,9 +308,10 @@ |
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#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ |
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#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ |
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#define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */ |
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#define CFG_PCI_SUBSYS_VENDORID 0x1014 /* PCI Vendor ID: IBM */ |
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#define CFG_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: --- */ |
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#define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ |
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#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ |
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#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */ |
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#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ |
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@ -349,12 +366,23 @@ |
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/*-----------------------------------------------------------------------
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* Environment Variable setup |
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*/ |
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#ifdef ENVIRONMENT_IN_EEPROM |
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#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ |
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#define CFG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */ |
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#define CFG_ENV_SIZE 0x700 /* 2048-256 bytes may be used for env vars (total size of a CAT24WC16 is 2048 bytes)*/ |
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#else /* DEFAULT: environment in flash, using redundand flash sectors */ |
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#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ |
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#define CFG_ENV_ADDR 0xFFFF8000 /* environment starts at the first small sector */ |
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#define CFG_ENV_SECT_SIZE 0x2000 /* 8196 bytes may be used for env vars*/ |
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#define CFG_ENV_ADDR_REDUND 0xFFFFA000 |
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#define CFG_ENV_SIZE_REDUND 0x2000 |
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#endif /* ENVIRONMENT_IN_EEPROM */ |
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#define CFG_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */ |
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#define CFG_NVRAM_SIZE 242 /* NVRAM size */ |
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@ -414,23 +442,21 @@ |
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#define CFG_EBC_PB3AP 0x92015480 |
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#define CFG_EBC_PB3CR 0xFF058000 /* BAS=0xFF0,BS=4MB,BU=R/W,BW=8bit */ |
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#if 0 /* Roese */
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/* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization */ |
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#define CFG_EBC_PB1AP 0x92015480 |
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#define CFG_EBC_PB1CR 0xFF858000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=8bit */ |
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/* Memory Bank 2 (CAN0, 1) initialization */ |
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#define CFG_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ |
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#define CFG_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ |
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/* Memory Bank 3 (CompactFlash IDE) initialization */ |
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#define CFG_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ |
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#define CFG_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */ |
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/* Memory Bank 4 (NVRAM/RTC) initialization */ |
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#define CFG_EBC_PB4AP 0x01005280 /* TWT=2,WBN=1,WBF=1,TH=1,SOR=1 */ |
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#define CFG_EBC_PB4CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */ |
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#ifdef CONFIG_PPCHAMELEON_SMI712 |
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/*
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* Video console (graphic: SMI LynxEM) |
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*/ |
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#define CONFIG_VIDEO |
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#define CONFIG_CFB_CONSOLE |
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#define CONFIG_VIDEO_SMI_LYNXEM |
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#define CONFIG_VIDEO_LOGO |
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/*#define CONFIG_VIDEO_BMP_LOGO*/ |
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#define CONFIG_CONSOLE_EXTRA_INFO |
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#define CONFIG_VGA_AS_SINGLE_DEVICE |
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/* This is the base address (on 405EP-side) used to generate I/O accesses on PCI bus */ |
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#define CFG_ISA_IO 0xE8000000 |
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/* see also drivers/videomodes.c */ |
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#define CFG_DEFAULT_VIDEO_MODE 0x303 |
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#endif |
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/*-----------------------------------------------------------------------
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@ -485,6 +511,7 @@ |
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#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */ |
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#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */ |
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#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ |
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
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#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET |
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@ -525,7 +552,6 @@ |
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/*--------------------------------------------------------------------*/ |
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#ifdef CONFIG_NO_SERIAL_EEPROM |
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/*
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!----------------------------------------------------------------------- |
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! Defines for entry options. |
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@ -537,7 +563,6 @@ |
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#define DIMM_READ_ADDR 0xAB |
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#define DIMM_WRITE_ADDR 0xAA |
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#define CPC0_PLLMR0 (CNTRL_DCR_BASE+0x0) /* PLL mode 0 register */ |
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#define CPC0_BOOT (CNTRL_DCR_BASE+0x1) /* Chip Clock Status register */ |
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#define CPC0_CR1 (CNTRL_DCR_BASE+0x2) /* Chip Control 1 register */ |
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@ -649,50 +674,92 @@ |
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#define PLL_PCIDIV_3 0x00000002 |
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#define PLL_PCIDIV_4 0x00000003 |
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#ifdef CONFIG_PPCHAMELEON_CLK_25 |
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/* CPU - PLB/SDRAM - EBC - OPB - PCI (assuming a 25.0 MHz input clock to the 405EP) */ |
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#define PPCHAMELEON_PLLMR0_133_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \ |
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PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
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PLL_MALDIV_1 | PLL_PCIDIV_4) |
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#define PPCHAMELEON_PLLMR1_133_133_33_66_33 (PLL_FBKDIV_8 | \ |
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PLL_FWDDIVA_6 | PLL_FWDDIVB_4 | \
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PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) |
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#define PPCHAMELEON_PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ |
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PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
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PLL_MALDIV_1 | PLL_PCIDIV_4) |
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#define PPCHAMELEON_PLLMR1_200_100_50_33 (PLL_FBKDIV_8 | \ |
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PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \
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PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) |
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#define PPCHAMELEON_PLLMR0_266_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ |
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PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
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PLL_MALDIV_1 | PLL_PCIDIV_4) |
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#define PPCHAMELEON_PLLMR1_266_133_33_66_33 (PLL_FBKDIV_8 | \ |
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PLL_FWDDIVA_3 | PLL_FWDDIVB_4 | \
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PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) |
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#define PPCHAMELEON_PLLMR0_333_111_37_55_55 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \ |
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PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
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PLL_MALDIV_1 | PLL_PCIDIV_2) |
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#define PPCHAMELEON_PLLMR1_333_111_37_55_55 (PLL_FBKDIV_10 | \ |
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PLL_FWDDIVA_3 | PLL_FWDDIVB_4 | \
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PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI) |
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#elif (defined (CONFIG_PPCHAMELEON_CLK_33)) |
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/* CPU - PLB/SDRAM - EBC - OPB - PCI (assuming a 33.3MHz input clock to the 405EP) */ |
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#define PLLMR0_133_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \ |
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#define PPCHAMELEON_PLLMR0_133_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \ |
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PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
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PLL_MALDIV_1 | PLL_PCIDIV_4) |
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#define PLLMR1_133_133_33_66_33 (PLL_FBKDIV_4 | \ |
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#define PPCHAMELEON_PLLMR1_133_133_33_66_33 (PLL_FBKDIV_4 | \ |
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PLL_FWDDIVA_6 | PLL_FWDDIVB_6 | \
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PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) |
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#define PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ |
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#define PPCHAMELEON_PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ |
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PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
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PLL_MALDIV_1 | PLL_PCIDIV_4) |
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#define PLLMR1_200_100_50_33 (PLL_FBKDIV_6 | \ |
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#define PPCHAMELEON_PLLMR1_200_100_50_33 (PLL_FBKDIV_6 | \ |
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PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \
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PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) |
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#define PLLMR0_266_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ |
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#define PPCHAMELEON_PLLMR0_266_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ |
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PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
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PLL_MALDIV_1 | PLL_PCIDIV_4) |
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#define PLLMR1_266_133_33_66_33 (PLL_FBKDIV_8 | \ |
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#define PPCHAMELEON_PLLMR1_266_133_33_66_33 (PLL_FBKDIV_8 | \ |
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PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
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PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) |
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#define PLLMR0_333_111_37_55_55 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \ |
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#define PPCHAMELEON_PLLMR0_333_111_37_55_55 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \ |
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PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
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PLL_MALDIV_1 | PLL_PCIDIV_2) |
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#define PLLMR1_333_111_37_55_55 (PLL_FBKDIV_10 | \ |
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#define PPCHAMELEON_PLLMR1_333_111_37_55_55 (PLL_FBKDIV_10 | \ |
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PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
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PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI) |
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#else |
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#error "* External frequency (SysClk) not defined! *" |
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#endif |
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#if (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_HI) |
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/* Model HI */ |
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#define PLLMR0_DEFAULT PLLMR0_333_111_37_55_55 |
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#define PLLMR1_DEFAULT PLLMR1_333_111_37_55_55 |
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#define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_333_111_37_55_55 |
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#define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_333_111_37_55_55 |
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#define CFG_OPB_FREQ 55555555 |
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/* Model ME */ |
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#elif (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_ME) |
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#define PLLMR0_DEFAULT PLLMR0_266_133_33_66_33 |
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#define PLLMR1_DEFAULT PLLMR1_266_133_33_66_33 |
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#define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_266_133_33_66_33 |
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#define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_266_133_33_66_33 |
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#define CFG_OPB_FREQ 66666666 |
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#else |
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/* Model BA (default) */ |
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#define PLLMR0_DEFAULT PLLMR0_133_133_33_66_33 |
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#define PLLMR1_DEFAULT PLLMR1_133_133_33_66_33 |
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#define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_133_133_33_66_33 |
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#define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_133_133_33_66_33 |
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#define CFG_OPB_FREQ 66666666 |
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#endif |
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#endif /* CONFIG_NO_SERIAL_EEPROM */ |
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#endif |
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#define CONFIG_JFFS2_NAND 1 /* jffs2 on nand support */ |
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#define CONFIG_JFFS2_NAND 0 /* jffs2 on nand support */ |
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#define CONFIG_JFFS2_NAND_DEV 0 /* nand device jffs2 lives on */ |
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#define CONFIG_JFFS2_NAND_OFF 0 /* start of jffs2 partition */ |
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#define CONFIG_JFFS2_NAND_SIZE 2*1024*1024 /* size of jffs2 partition */ |
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