Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net> Acked-by: Stefano Babic <sbabic@denx.de>master
parent
af5b9b1f78
commit
e570aca947
@ -1,16 +0,0 @@ |
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#
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# board/mx1ads/Makefile
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#
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# (C) Copyright 2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# (c) Copyright 2004
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# Techware Information Technology, Inc.
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# http://www.techware.com.tw/
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#
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# Ming-Len Wu <minglen_wu@techware.com.tw>
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#
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# SPDX-License-Identifier: GPL-2.0+
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obj-y := mx1ads.o syncflash.o
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obj-y += lowlevel_init.o
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@ -1,68 +0,0 @@ |
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/* |
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* board/mx1ads/lowlevel_init.S |
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* |
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* (c) Copyright 2004 |
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* Techware Information Technology, Inc. |
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* http://www.techware.com.tw/ |
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* |
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* Ming-Len Wu <minglen_wu@techware.com.tw>
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <config.h> |
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#include <version.h> |
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#define SDCTL0 0x221000 |
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#define SDCTL1 0x221004 |
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_TEXT_BASE: |
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.word CONFIG_SYS_TEXT_BASE
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.globl lowlevel_init
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lowlevel_init: |
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/* memory controller init */ |
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ldr r1, =SDCTL0 |
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/* Set Precharge Command */ |
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ldr r3, =0x92120200 |
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/* ldr r3, =0x92120251 |
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*/ |
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str r3, [r1] |
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/* Issue Precharge All Commad */ |
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ldr r3, =0x8200000 |
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ldr r2, [r3] |
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/* Set AutoRefresh Command */ |
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ldr r3, =0xA2120200 |
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str r3, [r1] |
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/* Issue AutoRefresh Command */ |
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ldr r3, =0x8000000 |
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ldr r2, [r3] |
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ldr r2, [r3] |
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ldr r2, [r3] |
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ldr r2, [r3] |
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ldr r2, [r3] |
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ldr r2, [r3] |
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ldr r2, [r3] |
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ldr r2, [r3] |
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/* Set Mode Register */ |
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ldr r3, =0xB2120200 |
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str r3, [r1] |
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/* Issue Mode Register Command */ |
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ldr r3, =0x08111800 /* Mode Register Value */ |
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ldr r2, [r3] |
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/* Set Normal Mode */ |
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ldr r3, =0x82124200 |
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str r3, [r1] |
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/* everything is fine now */ |
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mov pc, lr |
@ -1,178 +0,0 @@ |
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/*
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* board/mx1ads/mx1ads.c |
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* |
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* (c) Copyright 2004 |
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* Techware Information Technology, Inc. |
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* http://www.techware.com.tw/
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* |
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* Ming-Len Wu <minglen_wu@techware.com.tw> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <netdev.h> |
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/*#include <mc9328.h>*/ |
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#include <asm/arch/imx-regs.h> |
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#include <asm/io.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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#define FCLK_SPEED 1 |
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#if FCLK_SPEED==0 /* Fout = 203MHz, Fin = 12MHz for Audio */ |
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#define M_MDIV 0xC3 |
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#define M_PDIV 0x4 |
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#define M_SDIV 0x1 |
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#elif FCLK_SPEED==1 /* Fout = 202.8MHz */ |
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#define M_MDIV 0xA1 |
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#define M_PDIV 0x3 |
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#define M_SDIV 0x1 |
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#endif |
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#define USB_CLOCK 1 |
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#if USB_CLOCK==0 |
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#define U_M_MDIV 0xA1 |
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#define U_M_PDIV 0x3 |
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#define U_M_SDIV 0x1 |
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#elif USB_CLOCK==1 |
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#define U_M_MDIV 0x48 |
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#define U_M_PDIV 0x3 |
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#define U_M_SDIV 0x2 |
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#endif |
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#if 0 |
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static inline void delay (unsigned long loops) |
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{ |
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__asm__ volatile ("1:\n" |
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"subs %0, %1, #1\n" |
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"bne 1b":"=r" (loops):"0" (loops)); |
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} |
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#endif |
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/*
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* Miscellaneous platform dependent initialisations |
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*/ |
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void SetAsynchMode (void) |
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{ |
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__asm__ ("mrc p15,0,r0,c1,c0,0 \n" |
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"mov r2, #0xC0000000 \n" |
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"orr r0,r2,r0 \n" "mcr p15,0,r0,c1,c0,0 \n"); |
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} |
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static u32 mc9328sid; |
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int board_early_init_f(void) |
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{ |
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mc9328sid = SIDR; |
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GPCR = 0x000003AB; /* I/O pad driving strength */ |
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/* MX1_CS1U = 0x00000A00; */ /* SRAM initialization */ |
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/* MX1_CS1L = 0x11110601; */ |
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MPCTL0 = 0x04632410; /* setting for 150 MHz MCU PLL CLK */ |
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/* set FCLK divider 1 (i.e. FCLK to MCU PLL CLK) and
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* BCLK divider to 2 (i.e. BCLK to 48 MHz) |
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*/ |
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CSCR = 0xAF000403; |
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CSCR |= 0x00200000; /* Trigger the restart bit(bit 21) */ |
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CSCR &= 0xFFFF7FFF; /* Program PRESC bit(bit 15) to 0 to divide-by-1 */ |
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/* setup cs4 for cs8900 ethernet */ |
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CS4U = 0x00000F00; /* Initialize CS4 for CS8900 ethernet */ |
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CS4L = 0x00001501; |
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GIUS (0) &= 0xFF3FFFFF; |
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GPR (0) &= 0xFF3FFFFF; |
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readl(0x1500000C); |
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readl(0x1500000C); |
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SetAsynchMode (); |
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icache_enable (); |
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dcache_enable (); |
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/* set PERCLKs */ |
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PCDR = 0x00000055; /* set PERCLKS */ |
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/* PERCLK3 is only used by SSI so the SSI driver can set it any value it likes
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* PERCLK1 and PERCLK2 are shared so DO NOT change it in any other place |
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* all sources selected as normal interrupt |
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*/ |
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/* MX1_INTTYPEH = 0;
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MX1_INTTYPEL = 0; |
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*/ |
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return 0; |
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} |
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int board_init(void) |
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{ |
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gd->bd->bi_arch_number = MACH_TYPE_MX1ADS; |
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gd->bd->bi_boot_params = 0x08000100; /* adress of boot parameters */ |
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return 0; |
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} |
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int board_late_init (void) |
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{ |
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setenv ("stdout", "serial"); |
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setenv ("stderr", "serial"); |
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switch (mc9328sid) { |
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case 0x0005901d: |
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printf ("MX1ADS board with MC9328 MX1 (0L44N), Silicon ID 0x%08x \n\n", |
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mc9328sid); |
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break; |
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case 0x04d4c01d: |
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printf ("MX1ADS board with MC9328 MXL (1L45N), Silicon ID 0x%08x \n\n", |
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mc9328sid); |
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break; |
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case 0x00d4c01d: |
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printf ("MX1ADS board with MC9328 MXL (2L45N), Silicon ID 0x%08x \n\n", |
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mc9328sid); |
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break; |
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default: |
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printf ("MX1ADS board with UNKNOWN MC9328 cpu, Silicon ID 0x%08x \n", |
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mc9328sid); |
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break; |
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} |
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return 0; |
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} |
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int dram_init(void) |
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{ |
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/* dram_init must store complete ramsize in gd->ram_size */ |
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gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1, |
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PHYS_SDRAM_1_SIZE); |
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return 0; |
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} |
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void dram_init_banksize(void) |
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{ |
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gd->bd->bi_dram[0].start = PHYS_SDRAM_1; |
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gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; |
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} |
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#ifdef CONFIG_CMD_NET |
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int board_eth_init(bd_t *bis) |
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{ |
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int rc = 0; |
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#ifdef CONFIG_CS8900 |
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rc = cs8900_initialize(0, CONFIG_CS8900_BASE); |
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#endif |
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return rc; |
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} |
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#endif |
@ -1,307 +0,0 @@ |
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/*
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* board/mx1ads/syncflash.c |
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* |
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* (c) Copyright 2004 |
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* Techware Information Technology, Inc. |
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* http://www.techware.com.tw/
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* |
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* Ming-Len Wu <minglen_wu@techware.com.tw> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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/*#include <mc9328.h>*/ |
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#include <asm/arch/imx-regs.h> |
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typedef unsigned long * p_u32; |
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/* 4Mx16x2 IAM=0 CSD1 */ |
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flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ |
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/* Following Setting is for CSD1 */ |
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#define SFCTL 0x00221004 |
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#define reg_SFCTL __REG(SFCTL) |
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#define SYNCFLASH_A10 (0x00100000) |
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#define CMD_NORMAL (0x81020300) /* Normal Mode */ |
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#define CMD_PREC (CMD_NORMAL + 0x10000000) /* Precharge Command */ |
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#define CMD_AUTO (CMD_NORMAL + 0x20000000) /* Auto Refresh Command */ |
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#define CMD_LMR (CMD_NORMAL + 0x30000000) /* Load Mode Register Command */ |
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#define CMD_LCR (CMD_NORMAL + 0x60000000) /* LCR Command */ |
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#define CMD_PROGRAM (CMD_NORMAL + 0x70000000) |
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#define MODE_REG_VAL (CONFIG_SYS_FLASH_BASE+0x0008CC00) /* Cas Latency 3 */ |
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/* LCR Command */ |
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#define LCR_READSTATUS (0x0001C000) /* 0x70 */ |
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#define LCR_ERASE_CONFIRM (0x00008000) /* 0x20 */ |
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#define LCR_ERASE_NVMODE (0x0000C000) /* 0x30 */ |
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#define LCR_PROG_NVMODE (0x00028000) /* 0xA0 */ |
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#define LCR_SR_CLEAR (0x00014000) /* 0x50 */ |
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/* Get Status register */ |
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u32 SF_SR(void) { |
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u32 tmp; |
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reg_SFCTL = CMD_PROGRAM; |
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tmp = __REG(CONFIG_SYS_FLASH_BASE); |
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reg_SFCTL = CMD_NORMAL; |
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reg_SFCTL = CMD_LCR; /* Activate LCR Mode */ |
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__REG(CONFIG_SYS_FLASH_BASE + LCR_SR_CLEAR); |
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return tmp; |
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} |
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/* check if SyncFlash is ready */ |
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u8 SF_Ready(void) { |
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u32 tmp; |
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tmp = SF_SR(); |
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if ((tmp & 0x00800000) && (tmp & 0x001C0000)) { |
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printf ("SyncFlash Error code %08x\n",tmp); |
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}; |
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if ((tmp & 0x00000080) && (tmp & 0x0000001C)) { |
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printf ("SyncFlash Error code %08x\n",tmp); |
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}; |
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if (tmp == 0x00800080) /* Test Bit 7 of SR */ |
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return 1; |
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else |
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return 0; |
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} |
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/* Issue the precharge all command */ |
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void SF_PrechargeAll(void) { |
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/* Set Precharge Command */ |
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reg_SFCTL = CMD_PREC; |
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/* Issue Precharge All Command */ |
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__REG(CONFIG_SYS_FLASH_BASE + SYNCFLASH_A10); |
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} |
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/* set SyncFlash to normal mode */ |
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void SF_Normal(void) { |
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SF_PrechargeAll(); |
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reg_SFCTL = CMD_NORMAL; |
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} |
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/* Erase SyncFlash */ |
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void SF_Erase(u32 RowAddress) { |
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reg_SFCTL = CMD_NORMAL; |
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__REG(RowAddress); |
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reg_SFCTL = CMD_PREC; |
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__REG(RowAddress); |
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reg_SFCTL = CMD_LCR; /* Set LCR mode */ |
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__REG(RowAddress + LCR_ERASE_CONFIRM) = 0; /* Issue Erase Setup Command */ |
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reg_SFCTL = CMD_NORMAL; /* return to Normal mode */ |
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__REG(RowAddress) = 0xD0D0D0D0; /* Confirm */ |
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while(!SF_Ready()); |
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} |
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void SF_NvmodeErase(void) { |
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SF_PrechargeAll(); |
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reg_SFCTL = CMD_LCR; /* Set to LCR mode */ |
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__REG(CONFIG_SYS_FLASH_BASE + LCR_ERASE_NVMODE) = 0; /* Issue Erase Nvmode Reg Command */ |
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reg_SFCTL = CMD_NORMAL; /* Return to Normal mode */ |
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__REG(CONFIG_SYS_FLASH_BASE + LCR_ERASE_NVMODE) = 0xC0C0C0C0; /* Confirm */ |
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while(!SF_Ready()); |
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} |
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void SF_NvmodeWrite(void) { |
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SF_PrechargeAll(); |
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reg_SFCTL = CMD_LCR; /* Set to LCR mode */ |
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__REG(CONFIG_SYS_FLASH_BASE+LCR_PROG_NVMODE) = 0; /* Issue Program Nvmode reg command */ |
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reg_SFCTL = CMD_NORMAL; /* Return to Normal mode */ |
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__REG(CONFIG_SYS_FLASH_BASE+LCR_PROG_NVMODE) = 0xC0C0C0C0; /* Confirm not needed */ |
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} |
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/****************************************************************************************/ |
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ulong flash_init(void) { |
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int i, j; |
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/* Turn on CSD1 for negating RESETSF of SyncFLash */ |
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reg_SFCTL |= 0x80000000; /* enable CSD1 for SyncFlash */ |
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udelay(200); |
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reg_SFCTL = CMD_LMR; /* Set Load Mode Register Command */ |
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__REG(MODE_REG_VAL); /* Issue Load Mode Register Command */ |
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SF_Normal(); |
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i = 0; |
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flash_info[i].flash_id = FLASH_MAN_MT | FLASH_MT28S4M16LC; |
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flash_info[i].size = FLASH_BANK_SIZE; |
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flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT; |
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memset(flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT); |
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for (j = 0; j < flash_info[i].sector_count; j++) { |
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flash_info[i].start[j] = CONFIG_SYS_FLASH_BASE + j * 0x00100000; |
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} |
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flash_protect(FLAG_PROTECT_SET, |
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CONFIG_SYS_FLASH_BASE, |
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CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1, |
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&flash_info[0]); |
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flash_protect(FLAG_PROTECT_SET, |
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CONFIG_ENV_ADDR, |
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CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, |
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&flash_info[0]); |
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return FLASH_BANK_SIZE; |
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} |
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void flash_print_info (flash_info_t *info) { |
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int i; |
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switch (info->flash_id & FLASH_VENDMASK) { |
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case (FLASH_MAN_MT & FLASH_VENDMASK): |
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printf("Micron: "); |
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break; |
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default: |
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printf("Unknown Vendor "); |
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break; |
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} |
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switch (info->flash_id & FLASH_TYPEMASK) { |
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case (FLASH_MT28S4M16LC & FLASH_TYPEMASK): |
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printf("2x FLASH_MT28S4M16LC (16MB Total)\n"); |
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break; |
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default: |
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printf("Unknown Chip Type\n"); |
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return; |
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break; |
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} |
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printf(" Size: %ld MB in %d Sectors\n", |
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info->size >> 20, info->sector_count); |
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printf(" Sector Start Addresses: "); |
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for (i = 0; i < info->sector_count; i++) { |
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if ((i % 5) == 0) |
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printf ("\n "); |
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printf (" %08lX%s", info->start[i], |
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info->protect[i] ? " (RO)" : " "); |
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} |
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printf ("\n"); |
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} |
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/*-----------------------------------------------------------------------*/ |
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int flash_erase (flash_info_t *info, int s_first, int s_last) { |
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int iflag, cflag, prot, sect; |
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int rc = ERR_OK; |
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/* first look for protection bits */ |
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if (info->flash_id == FLASH_UNKNOWN) |
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return ERR_UNKNOWN_FLASH_TYPE; |
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if ((s_first < 0) || (s_first > s_last)) |
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return ERR_INVAL; |
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if ((info->flash_id & FLASH_VENDMASK) != (FLASH_MAN_MT & FLASH_VENDMASK)) |
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return ERR_UNKNOWN_FLASH_VENDOR; |
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prot = 0; |
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for (sect = s_first; sect <= s_last; ++sect) { |
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if (info->protect[sect]) |
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prot++; |
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} |
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if (prot) { |
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printf("protected!\n"); |
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return ERR_PROTECTED; |
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} |
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/*
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* Disable interrupts which might cause a timeout |
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* here. Remember that our exception vectors are |
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* at address 0 in the flash, and we don't want a |
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* (ticker) exception to happen while the flash |
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* chip is in programming mode. |
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*/ |
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cflag = icache_status(); |
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icache_disable(); |
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iflag = disable_interrupts(); |
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/* Start erase on unprotected sectors */ |
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for (sect = s_first; sect <= s_last && !ctrlc(); sect++) { |
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printf("Erasing sector %2d ... ", sect); |
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/* arm simple, non interrupt dependent timer */ |
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get_timer(0); |
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SF_NvmodeErase(); |
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SF_NvmodeWrite(); |
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SF_Erase(CONFIG_SYS_FLASH_BASE + (0x0100000 * sect)); |
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SF_Normal(); |
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printf("ok.\n"); |
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} |
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if (ctrlc()) |
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printf("User Interrupt!\n"); |
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if (iflag) |
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enable_interrupts(); |
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if (cflag) |
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icache_enable(); |
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return rc; |
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} |
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/*-----------------------------------------------------------------------
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* Copy memory to flash. |
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*/ |
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int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) { |
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int i; |
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for(i = 0; i < cnt; i += 4) { |
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SF_PrechargeAll(); |
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|
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reg_SFCTL = CMD_PROGRAM; /* Enter SyncFlash Program mode */ |
||||
__REG(addr + i) = __REG((u32)src + i); |
||||
|
||||
while(!SF_Ready()); |
||||
} |
||||
|
||||
SF_Normal(); |
||||
|
||||
return ERR_OK; |
||||
} |
@ -1,163 +0,0 @@ |
||||
/*
|
||||
* include/configs/mx1ads.h |
||||
* |
||||
* (c) Copyright 2004 |
||||
* Techware Information Technology, Inc. |
||||
* http://www.techware.com.tw/
|
||||
* |
||||
* Ming-Len Wu <minglen_wu@techware.com.tw> |
||||
* |
||||
* This is the Configuration setting for Motorola MX1ADS board |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
/*
|
||||
* High Level Configuration Options |
||||
* (easy to change) |
||||
*/ |
||||
#define CONFIG_ARM920T 1 /* This is an ARM920T Core */ |
||||
#define CONFIG_IMX 1 /* It's a Motorola MC9328 SoC */ |
||||
#define CONFIG_MX1ADS 1 /* on a Motorola MX1ADS Board */ |
||||
|
||||
/*
|
||||
* Select serial console configuration |
||||
*/ |
||||
#define CONFIG_IMX_SERIAL |
||||
#define CONFIG_IMX_SERIAL1 /* internal uart 1 */ |
||||
/* #define _CONFIG_UART2 */ /* internal uart 2 */ |
||||
/* #define CONFIG_SILENT_CONSOLE */ /* use this to disable output */ |
||||
|
||||
#define CONFIG_BOARD_LATE_INIT |
||||
#define USE_920T_MMU 1 |
||||
|
||||
#if 0 |
||||
#define CONFIG_SYS_MX1_GPCR 0x000003AB /* for MX1ADS 0L44N */ |
||||
#define CONFIG_SYS_MX1_GPCR 0x000003AB /* for MX1ADS 0L44N */ |
||||
#define CONFIG_SYS_MX1_GPCR 0x000003AB /* for MX1ADS 0L44N */ |
||||
#endif |
||||
|
||||
/*
|
||||
* Size of malloc() pool |
||||
*/ |
||||
|
||||
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) |
||||
|
||||
/*
|
||||
* CS8900 Ethernet drivers |
||||
*/ |
||||
#define CONFIG_CS8900 /* we have a CS8900 on-board */ |
||||
#define CONFIG_CS8900_BASE 0x15000300 |
||||
#define CONFIG_CS8900_BUS16 /* the Linux driver does accesses as shorts */ |
||||
|
||||
/*
|
||||
* select serial console configuration |
||||
*/ |
||||
|
||||
/* #define CONFIG_UART1 */ |
||||
/* #define CONFIG_UART2 1 */ |
||||
|
||||
#define CONFIG_BAUDRATE 115200 |
||||
|
||||
/*
|
||||
* BOOTP options |
||||
*/ |
||||
#define CONFIG_BOOTP_BOOTFILESIZE |
||||
#define CONFIG_BOOTP_BOOTPATH |
||||
#define CONFIG_BOOTP_GATEWAY |
||||
#define CONFIG_BOOTP_HOSTNAME |
||||
|
||||
/*
|
||||
* Command line configuration. |
||||
*/ |
||||
#include <config_cmd_default.h> |
||||
|
||||
#define CONFIG_CMD_CACHE |
||||
#define CONFIG_CMD_REGINFO |
||||
#define CONFIG_CMD_ELF |
||||
|
||||
#define CONFIG_BOOTDELAY 3 |
||||
#define CONFIG_BOOTARGS "root=/dev/msdk mem=48M" |
||||
#define CONFIG_BOOTFILE "mx1ads" |
||||
#define CONFIG_BOOTCOMMAND "tftp; bootm" |
||||
|
||||
#if defined(CONFIG_CMD_KGDB) |
||||
#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ |
||||
#endif |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
|
||||
#define CONFIG_SYS_HUSH_PARSER 1 |
||||
|
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */ |
||||
|
||||
#ifdef CONFIG_SYS_HUSH_PARSER |
||||
#define CONFIG_SYS_PROMPT "MX1ADS$ " /* Monitor Command Prompt */ |
||||
#else |
||||
#define CONFIG_SYS_PROMPT "MX1ADS=> " /* Monitor Command Prompt */ |
||||
#endif |
||||
|
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) |
||||
/* Print Buffer Size */ |
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x09000000 /* memtest works on */ |
||||
#define CONFIG_SYS_MEMTEST_END 0x0AF00000 /* 63 MB in DRAM */ |
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x08800000 /* default load address */ |
||||
#define CONFIG_SYS_HZ 3686400 |
||||
#define CONFIG_SYS_CPUSPEED 0x141 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Physical Memory Map |
||||
*/ |
||||
|
||||
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of SDRAM */ |
||||
#define PHYS_SDRAM_1 0x08000000 /* SDRAM on CSD0 */ |
||||
#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ |
||||
|
||||
#define CONFIG_SYS_TEXT_BASE 0x10000000 |
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 |
||||
#define CONFIG_SYS_INIT_RAM_ADDR 0x00300000 |
||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x000FFFFF |
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ |
||||
GENERATED_GBL_DATA_SIZE) |
||||
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ |
||||
CONFIG_SYS_GBL_DATA_OFFSET) |
||||
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* 1 bank of SyncFlash */ |
||||
#define CONFIG_SYS_FLASH_BASE 0x0C000000 /* SyncFlash on CSD1 */ |
||||
#define FLASH_BANK_SIZE 0x01000000 /* 16 MB Total */ |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH and environment organization |
||||
*/ |
||||
|
||||
#define CONFIG_SYNCFLASH 1 |
||||
#define PHYS_FLASH_SIZE 0x01000000 |
||||
#define CONFIG_SYS_MAX_FLASH_SECT (16) |
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+0x00ff8000) |
||||
|
||||
#define CONFIG_ENV_IS_IN_FLASH 1 |
||||
#define CONFIG_ENV_SIZE 0x04000 /* Total Size of Environment Sector */ |
||||
#define CONFIG_ENV_SECT_SIZE 0x100000 |
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Enable passing ATAGS |
||||
*/ |
||||
|
||||
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ |
||||
#define CONFIG_SETUP_MEMORY_TAGS 1 |
||||
|
||||
#define CONFIG_SYS_CLK_FREQ 16780000 |
||||
#define CONFIG_SYSPLL_CLK_FREQ 16000000 |
||||
|
||||
#endif /* __CONFIG_H */ |
Loading…
Reference in new issue