x86: braswell: Add microcode for B0/C0/D0 stepping SoC

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This adds microcode device tree fragment for Braswell B0 (406C2),
C0 (406C3) and D0 (406C4) stepping SoC.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

master

Bin Meng 7 years ago

parent de9ac9a1b9

commit e61a2687b3

3 changed files with 12924 additions and 0 deletions

Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL

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1. 4308
     arch/x86/dts/microcode/m01406c2220.dtsi
2. 4308
     arch/x86/dts/microcode/m01406c3363.dtsi
3. 4308
     arch/x86/dts/microcode/m01406c440a.dtsi

4308

arch/x86/dts/microcode/m01406c2220.dtsi

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4308

arch/x86/dts/microcode/m01406c3363.dtsi

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4308

arch/x86/dts/microcode/m01406c440a.dtsi

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