ARM64: zynqmp: Add SPL support support

Support RAM and MMC boot mode in SPL also with SPL_FIT images.

In MMC boot mode two boot options are available:
1) Boot flow with ATF(EL3) and full U-Boot(EL2):
 aarch64-linux-gnu-objcopy -O binary bl31.elf bl31.bin
 mkimage -A arm64 -O linux -T kernel -C none -a 0xfffe5000 -e 0xfffe5000
 -d bl31.bin atf.ub
 cp spl/boot.bin <sdcard fat partition>
 cp atf.ub <sdcard fat partition>
 cp u-boot.bin <sdcard fat partition>

2) Boot flow with full U-Boot(EL3):
 cp spl/boot.bin <sdcard>
 cp u-boot*.img <sdcard>

3) emmc boot mode
 dd if=/dev/zero of=sd.img bs=1024 count=1024
 parted sd.img mktable msdos
 parted sd.img mkpart p fat32 0% 100%
 kpartx -a sd.img
 mkfs.vfat /dev/mapper/loop0p1
 mount /dev/mapper/loop0p1 /mnt/
 cp spl/boot.bin /mnt
 cp u-boot.img /mnt
 cp u-boot.bin /mnt
 cp atf.ub /mnt
 umount /dev/mapper/loop0p1
 kpartx -d sd.img
 cp sd.img /tftpboot/

 and program it via u-boot
 tftpb 10000 sd.img
 mmcinfo
 mmc write 10000 0 $filesize
 mmc rescan
 mmc part
 ls mmc 0

psu_init() function contains low level SoC setup generated for every HW
design by Xilinx design tools. xil_io.h is only supporting file to fix
all dependencies from tools. The same solution was used on Xilinx Zynq.

The patch also change CONFIG_SYS_INIT_SP_ADDR to the end of OCM which
stays at the same location all the time.
Bootrom expects starting address to be at 0xfffc0000 that's why this
address is SPL_TEXT_BASE.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
master
Michal Simek 9 years ago
parent c9811e14cf
commit e6a9ed04e7
  1. 1
      arch/arm/Kconfig
  2. 1
      arch/arm/cpu/armv8/zynqmp/Makefile
  3. 107
      arch/arm/cpu/armv8/zynqmp/spl.c
  4. 2
      arch/arm/include/asm/arch-zynqmp/sys_proto.h
  5. 23
      board/xilinx/zynqmp/Makefile
  6. 35
      board/xilinx/zynqmp/xil_io.h
  7. 43
      include/configs/xilinx_zynqmp.h

@ -594,6 +594,7 @@ config ARCH_ZYNQMP
select DM
select OF_CONTROL
select DM_SERIAL
select SUPPORT_SPL
config TEGRA
bool "NVIDIA Tegra"

@ -9,3 +9,4 @@ obj-y += clk.o
obj-y += cpu.o
obj-$(CONFIG_MP) += mp.o
obj-y += slcr.o
obj-$(CONFIG_SPL_BUILD) += spl.o

@ -0,0 +1,107 @@
/*
* Copyright 2015 - 2016 Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <debug_uart.h>
#include <spl.h>
#include <asm/io.h>
#include <asm/spl.h>
#include <asm/arch/hardware.h>
#include <asm/arch/sys_proto.h>
void board_init_f(ulong dummy)
{
psu_init();
board_early_init_r();
#ifdef CONFIG_DEBUG_UART
/* Uart debug for sure */
debug_uart_init();
puts("Debug uart enabled\n"); /* or printch() */
#endif
/* Delay is required for clocks to be propagated */
udelay(1000000);
/* Clear the BSS */
memset(__bss_start, 0, __bss_end - __bss_start);
/* No need to call timer init - it is empty for ZynqMP */
board_init_r(NULL, 0);
}
#ifdef CONFIG_SPL_BOARD_INIT
void spl_board_init(void)
{
preloader_console_init();
board_init();
}
#endif
u32 spl_boot_device(void)
{
u32 reg = 0;
u8 bootmode;
reg = readl(&crlapb_base->boot_mode);
bootmode = reg & BOOT_MODES_MASK;
switch (bootmode) {
case JTAG_MODE:
return BOOT_DEVICE_RAM;
#ifdef CONFIG_SPL_MMC_SUPPORT
case EMMC_MODE:
case SD_MODE:
case SD_MODE1:
return BOOT_DEVICE_MMC1;
#endif
default:
printf("Invalid Boot Mode:0x%x\n", bootmode);
break;
}
return 0;
}
u32 spl_boot_mode(void)
{
switch (spl_boot_device()) {
case BOOT_DEVICE_RAM:
return 0;
case BOOT_DEVICE_MMC1:
return MMCSD_MODE_FS;
default:
puts("spl: error: unsupported device\n");
hang();
}
}
__weak void psu_init(void)
{
/*
* This function is overridden by the one in
* board/xilinx/zynqmp/(platform)/psu_init_gpl.c, if it exists.
*/
}
#ifdef CONFIG_SPL_OS_BOOT
int spl_start_uboot(void)
{
return 0;
}
#endif
#ifdef CONFIG_SPL_LOAD_FIT
int board_fit_config_name_match(const char *name)
{
/* Just empty function now - can't decide what to choose */
debug("%s: %s\n", __func__, name);
return 0;
}
#endif

@ -17,4 +17,6 @@ int zynq_slcr_get_mio_pin_status(const char *periph);
unsigned int zynqmp_get_silicon_version(void);
void psu_init(void);
#endif /* _ASM_ARCH_SYS_PROTO_H */

@ -1,8 +1,29 @@
#
# (C) Copyright 2014 - 2015 Xilinx, Inc.
# (C) Copyright 2014 - 2016 Xilinx, Inc.
# Michal Simek <michal.simek@xilinx.com>
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y := zynqmp.o
hw-platform-y :=$(shell echo $(CONFIG_SYS_CONFIG_NAME))
init-objs := $(if $(wildcard $(srctree)/$(src)/$(hw-platform-y)/psu_init_gpl.c),\
$(hw-platform-y)/psu_init_gpl.o)
ifeq ($(init-objs),)
ifneq ($(wildcard $(srctree)/$(src)/psu_init_gpl.c),)
init-objs := psu_init_gpl.o
$(if $(CONFIG_SPL_BUILD),\
$(warning Put custom psu_init_gpl.c/h to board/xilinx/zynqmp/custom_hw_platform/))
endif
endif
obj-$(CONFIG_SPL_BUILD) += $(init-objs)
# Suppress "warning: function declaration isn't a prototype"
CFLAGS_REMOVE_psu_init_gpl.o := -Wstrict-prototypes
# To include xil_io.h
CFLAGS_psu_init_gpl.o := -I$(srctree)/$(src)

@ -0,0 +1,35 @@
/*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef XIL_IO_H /* prevent circular inclusions */
#define XIL_IO_H
/* FIXME remove this when vivado is fixed */
#include <asm/io.h>
#define xil_printf(...)
void Xil_ICacheEnable(void)
{}
void Xil_DCacheEnable(void)
{}
void Xil_ICacheDisable(void)
{}
void Xil_DCacheDisable(void)
{}
void Xil_Out32(unsigned long addr, unsigned long val)
{
writel(val, addr);
}
int Xil_In32(unsigned long addr)
{
return readl(addr);
}
#endif /* XIL_IO_H */

@ -41,7 +41,7 @@
# define CONFIG_IDENT_STRING " Xilinx ZynqMP"
#endif
#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_INIT_SP_ADDR 0xfffffffc
/* Generic Timer Definitions - setup in EL3. Setup by ATF for other cases */
#if !defined(COUNTER_FREQUENCY)
@ -65,7 +65,9 @@
#define CONFIG_CMD_ENV
#define CONFIG_DOS_PARTITION
#define CONFIG_EFI_PARTITION
#define CONFIG_ISO_PARTITION
#ifndef CONFIG_SPL_BUILD
# define CONFIG_ISO_PARTITION
#endif
#define CONFIG_MP
/* BOOTP options */
@ -228,4 +230,41 @@
#define CONFIG_BOARD_EARLY_INIT_R
#define CONFIG_CLOCKS
#define CONFIG_SPL_TEXT_BASE 0xfffc0000
#define CONFIG_SPL_MAX_SIZE 0x20000
/* Just random location in OCM */
#define CONFIG_SPL_BSS_START_ADDR 0x1000000
#define CONFIG_SPL_BSS_MAX_SIZE 0x2000000
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SPL_RAM_DEVICE
#define CONFIG_SPL_OS_BOOT
/* u-boot is like dtb */
#define CONFIG_SPL_FS_LOAD_ARGS_NAME "u-boot.bin"
#define CONFIG_SYS_SPL_ARGS_ADDR 0x8000000
/* ATF is my kernel image */
#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "atf.ub"
/* FIT load address for RAM boot */
#define CONFIG_SPL_LOAD_FIT_ADDRESS 0x10000000
/* MMC support */
#ifdef CONFIG_ZYNQ_SDHCI
# define CONFIG_SPL_MMC_SUPPORT
# define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
# define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0 /* unused */
# define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0 /* unused */
# define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0 /* unused */
# define CONFIG_SPL_LIBDISK_SUPPORT
# define CONFIG_SPL_FAT_SUPPORT
# define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
#endif
#endif /* __XILINX_ZYNQMP_H */

Loading…
Cancel
Save