x86: Update microcode for secondary CPUs

Each CPU needs to have its microcode loaded. Add support for this so that
all CPUs will have the same version.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

arch/x86/cpu/cpu.c

@@ -27,6 +27,7 @@
 #include <asm/control_regs.h>
 #include <asm/cpu.h>
 #include <asm/lapic.h>
+#include <asm/microcode.h>
 #include <asm/mp.h>
 #include <asm/msr.h>
 #include <asm/mtrr.h>

arch/x86/cpu/intel_common/car.S

@@ -237,5 +237,7 @@ mtrr_table_end:
 	.align 4
 _dt_ucode_base_size:
 	/* These next two fields are filled in by ifdtool */
+.globl ucode_base
+ucode_base:	/* Declared in microcode.h */
 	.long	0			/* microcode base */
 	.long	0			/* microcode size */

arch/x86/cpu/mp_init.c

@@ -248,8 +248,10 @@ static int load_sipi_vector(atomic_t **ap_countp, int num_cpus)
 	if (!stack)
 		return -ENOMEM;
 	params->stack_top = (u32)(stack + size);
-
+#if !defined(CONFIG_QEMU) && !defined(CONFIG_HAVE_FSP)
-	params->microcode_ptr = 0;
+	params->microcode_ptr = ucode_base;
+	debug("Microcode at %x\n", params->microcode_ptr);
+#endif
 	params->msr_table_ptr = (u32)msr_save;
 	ret = save_bsp_msrs(msr_save, sizeof(msr_save));
 	if (ret < 0)

arch/x86/include/asm/microcode.h

@@ -9,6 +9,9 @@
 
 #ifndef __ASSEMBLY__
 
+/* This is a declaration for ucode_base in start.S */
+extern u32 ucode_base;
+
 /**
  * microcode_update_intel() - Apply microcode updates
  *

arch/x86/lib/fsp/fsp_car.S

@@ -102,6 +102,8 @@ temp_ram_init_romstack:
 temp_ram_init_params:
 _dt_ucode_base_size:
 	/* These next two fields are filled in by ifdtool */
+.globl ucode_base
+ucode_base:	/* Declared in micrcode.h */
 	.long	0			/* microcode base */
 	.long	0			/* microcode size */
 	.long	CONFIG_SYS_MONITOR_BASE	/* code region base */