Connect up the clocks and the eDP driver to make these displays work with Tegra124-based devices. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Anatolij Gustschin <agust@denx.de> Signed-off-by: Tom Warren <twarren@nvidia.com>master
parent
59dd5aa8fa
commit
e7e8823c7c
@ -0,0 +1,58 @@ |
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/*
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* (C) Copyright 2010 |
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* NVIDIA Corporation <www.nvidia.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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|
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#ifndef __ASM_ARCH_TEGRA_DISPLAY_H |
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#define __ASM_ARCH_TEGRA_DISPLAY_H |
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/**
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* Register a new display based on device tree configuration. |
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* |
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* The frame buffer can be positioned by U-Boot or overriden by the fdt. |
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* You should pass in the U-Boot address here, and check the contents of |
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* struct fdt_disp_config to see what was actually chosen. |
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* |
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* @param blob Device tree blob |
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* @param default_lcd_base Default address of LCD frame buffer |
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* @return 0 if ok, -1 on error (unsupported bits per pixel) |
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*/ |
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int tegra_display_probe(const void *blob, void *default_lcd_base); |
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/**
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* Return the current display configuration |
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* |
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* @return pointer to display configuration, or NULL if there is no valid |
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* config |
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*/ |
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struct fdt_disp_config *tegra_display_get_config(void); |
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/**
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* Perform the next stage of the LCD init if it is time to do so. |
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* |
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* LCD init can be time-consuming because of the number of delays we need |
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* while waiting for the backlight power supply, etc. This function can |
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* be called at various times during U-Boot operation to advance the |
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* initialization of the LCD to the next stage if sufficient time has |
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* passed since the last stage. It keeps track of what stage it is up to |
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* and the time that it is permitted to move to the next stage. |
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* |
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* The final call should have wait=1 to complete the init. |
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* |
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* @param blob fdt blob containing LCD information |
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* @param wait 1 to wait until all init is complete, and then return |
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* 0 to return immediately, potentially doing nothing if it is |
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* not yet time for the next init. |
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*/ |
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int tegra_lcd_check_next_stage(const void *blob, int wait); |
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/**
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* Set up the maximum LCD size so we can size the frame buffer. |
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* |
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* @param blob fdt blob containing LCD information |
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*/ |
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void tegra_lcd_early_init(const void *blob); |
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#endif /*__ASM_ARCH_TEGRA_DISPLAY_H*/ |
@ -0,0 +1,358 @@ |
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/*
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* Copyright 2014 Google Inc. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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* |
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* Extracted from Chromium coreboot commit 3f59b13d |
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*/ |
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#include <common.h> |
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#include <dm.h> |
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#include <edid.h> |
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#include <errno.h> |
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#include <displayport.h> |
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#include <edid.h> |
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#include <fdtdec.h> |
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#include <lcd.h> |
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#include <asm/gpio.h> |
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#include <asm/io.h> |
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#include <asm/arch/clock.h> |
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#include <asm/arch/pwm.h> |
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#include <asm/arch-tegra/dc.h> |
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#include "displayport.h" |
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DECLARE_GLOBAL_DATA_PTR; |
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/* return in 1000ths of a Hertz */ |
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static int tegra_dc_calc_refresh(const struct display_timing *timing) |
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{ |
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int h_total, v_total, refresh; |
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int pclk = timing->pixelclock.typ; |
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h_total = timing->hactive.typ + timing->hfront_porch.typ + |
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timing->hback_porch.typ + timing->hsync_len.typ; |
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v_total = timing->vactive.typ + timing->vfront_porch.typ + |
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timing->vback_porch.typ + timing->vsync_len.typ; |
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if (!pclk || !h_total || !v_total) |
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return 0; |
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refresh = pclk / h_total; |
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refresh *= 1000; |
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refresh /= v_total; |
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return refresh; |
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} |
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static void print_mode(const struct display_timing *timing) |
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{ |
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int refresh = tegra_dc_calc_refresh(timing); |
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debug("MODE:%dx%d@%d.%03uHz pclk=%d\n", |
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timing->hactive.typ, timing->vactive.typ, refresh / 1000, |
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refresh % 1000, timing->pixelclock.typ); |
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} |
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static int update_display_mode(struct dc_ctlr *disp_ctrl, |
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const struct display_timing *timing, |
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int href_to_sync, int vref_to_sync) |
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{ |
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print_mode(timing); |
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writel(0x1, &disp_ctrl->disp.disp_timing_opt); |
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writel(vref_to_sync << 16 | href_to_sync, |
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&disp_ctrl->disp.ref_to_sync); |
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writel(timing->vsync_len.typ << 16 | timing->hsync_len.typ, |
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&disp_ctrl->disp.sync_width); |
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writel(((timing->vback_porch.typ - vref_to_sync) << 16) | |
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timing->hback_porch.typ, &disp_ctrl->disp.back_porch); |
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writel(((timing->vfront_porch.typ + vref_to_sync) << 16) | |
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timing->hfront_porch.typ, &disp_ctrl->disp.front_porch); |
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writel(timing->hactive.typ | (timing->vactive.typ << 16), |
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&disp_ctrl->disp.disp_active); |
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/**
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* We want to use PLLD_out0, which is PLLD / 2: |
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* PixelClock = (PLLD / 2) / ShiftClockDiv / PixelClockDiv. |
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* |
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* Currently most panels work inside clock range 50MHz~100MHz, and PLLD |
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* has some requirements to have VCO in range 500MHz~1000MHz (see |
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* clock.c for more detail). To simplify calculation, we set |
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* PixelClockDiv to 1 and ShiftClockDiv to 1. In future these values |
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* may be calculated by clock_display, to allow wider frequency range. |
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* |
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* Note ShiftClockDiv is a 7.1 format value. |
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*/ |
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const u32 shift_clock_div = 1; |
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writel((PIXEL_CLK_DIVIDER_PCD1 << PIXEL_CLK_DIVIDER_SHIFT) | |
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((shift_clock_div - 1) * 2) << SHIFT_CLK_DIVIDER_SHIFT, |
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&disp_ctrl->disp.disp_clk_ctrl); |
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debug("%s: PixelClock=%u, ShiftClockDiv=%u\n", __func__, |
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timing->pixelclock.typ, shift_clock_div); |
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return 0; |
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} |
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static int tegra_depth_for_bpp(int bpp) |
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{ |
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switch (bpp) { |
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case 32: |
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return COLOR_DEPTH_R8G8B8A8; |
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case 16: |
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return COLOR_DEPTH_B5G6R5; |
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default: |
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debug("Unsupported LCD bit depth"); |
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return -1; |
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} |
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} |
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static int update_window(struct dc_ctlr *disp_ctrl, |
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u32 frame_buffer, int fb_bits_per_pixel, |
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const struct display_timing *timing) |
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{ |
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const u32 colour_white = 0xffffff; |
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int colour_depth; |
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u32 val; |
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writel(WINDOW_A_SELECT, &disp_ctrl->cmd.disp_win_header); |
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writel(((timing->vactive.typ << 16) | timing->hactive.typ), |
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&disp_ctrl->win.size); |
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writel(((timing->vactive.typ << 16) | |
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(timing->hactive.typ * fb_bits_per_pixel / 8)), |
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&disp_ctrl->win.prescaled_size); |
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writel(((timing->hactive.typ * fb_bits_per_pixel / 8 + 31) / |
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32 * 32), &disp_ctrl->win.line_stride); |
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colour_depth = tegra_depth_for_bpp(fb_bits_per_pixel); |
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if (colour_depth == -1) |
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return -EINVAL; |
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writel(colour_depth, &disp_ctrl->win.color_depth); |
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writel(frame_buffer, &disp_ctrl->winbuf.start_addr); |
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writel(0x1000 << V_DDA_INC_SHIFT | 0x1000 << H_DDA_INC_SHIFT, |
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&disp_ctrl->win.dda_increment); |
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writel(colour_white, &disp_ctrl->disp.blend_background_color); |
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writel(CTRL_MODE_C_DISPLAY << CTRL_MODE_SHIFT, |
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&disp_ctrl->cmd.disp_cmd); |
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writel(WRITE_MUX_ACTIVE, &disp_ctrl->cmd.state_access); |
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val = GENERAL_ACT_REQ | WIN_A_ACT_REQ; |
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val |= GENERAL_UPDATE | WIN_A_UPDATE; |
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writel(val, &disp_ctrl->cmd.state_ctrl); |
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/* Enable win_a */ |
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val = readl(&disp_ctrl->win.win_opt); |
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writel(val | WIN_ENABLE, &disp_ctrl->win.win_opt); |
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return 0; |
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} |
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static int tegra_dc_init(struct dc_ctlr *disp_ctrl) |
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{ |
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/* do not accept interrupts during initialization */ |
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writel(0x00000000, &disp_ctrl->cmd.int_mask); |
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writel(WRITE_MUX_ASSEMBLY | READ_MUX_ASSEMBLY, |
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&disp_ctrl->cmd.state_access); |
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writel(WINDOW_A_SELECT, &disp_ctrl->cmd.disp_win_header); |
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writel(0x00000000, &disp_ctrl->win.win_opt); |
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writel(0x00000000, &disp_ctrl->win.byte_swap); |
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writel(0x00000000, &disp_ctrl->win.buffer_ctrl); |
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writel(0x00000000, &disp_ctrl->win.pos); |
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writel(0x00000000, &disp_ctrl->win.h_initial_dda); |
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writel(0x00000000, &disp_ctrl->win.v_initial_dda); |
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writel(0x00000000, &disp_ctrl->win.dda_increment); |
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writel(0x00000000, &disp_ctrl->win.dv_ctrl); |
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writel(0x01000000, &disp_ctrl->win.blend_layer_ctrl); |
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writel(0x00000000, &disp_ctrl->win.blend_match_select); |
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writel(0x00000000, &disp_ctrl->win.blend_nomatch_select); |
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writel(0x00000000, &disp_ctrl->win.blend_alpha_1bit); |
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writel(0x00000000, &disp_ctrl->winbuf.start_addr_hi); |
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writel(0x00000000, &disp_ctrl->winbuf.addr_h_offset); |
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writel(0x00000000, &disp_ctrl->winbuf.addr_v_offset); |
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writel(0x00000000, &disp_ctrl->com.crc_checksum); |
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writel(0x00000000, &disp_ctrl->com.pin_output_enb[0]); |
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writel(0x00000000, &disp_ctrl->com.pin_output_enb[1]); |
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writel(0x00000000, &disp_ctrl->com.pin_output_enb[2]); |
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writel(0x00000000, &disp_ctrl->com.pin_output_enb[3]); |
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writel(0x00000000, &disp_ctrl->disp.disp_signal_opt0); |
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return 0; |
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} |
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static void dump_config(int panel_bpp, struct display_timing *timing) |
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{ |
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printf("timing->hactive.typ = %d\n", timing->hactive.typ); |
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printf("timing->vactive.typ = %d\n", timing->vactive.typ); |
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printf("timing->pixelclock.typ = %d\n", timing->pixelclock.typ); |
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printf("timing->hfront_porch.typ = %d\n", timing->hfront_porch.typ); |
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printf("timing->hsync_len.typ = %d\n", timing->hsync_len.typ); |
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printf("timing->hback_porch.typ = %d\n", timing->hback_porch.typ); |
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printf("timing->vfront_porch.typ %d\n", timing->vfront_porch.typ); |
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printf("timing->vsync_len.typ = %d\n", timing->vsync_len.typ); |
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printf("timing->vback_porch.typ = %d\n", timing->vback_porch.typ); |
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printf("panel_bits_per_pixel = %d\n", panel_bpp); |
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} |
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static int display_update_config_from_edid(struct udevice *dp_dev, |
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int *panel_bppp, |
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struct display_timing *timing) |
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{ |
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u8 buf[EDID_SIZE]; |
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int bpc, ret; |
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ret = display_port_read_edid(dp_dev, buf, sizeof(buf)); |
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if (ret < 0) |
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return ret; |
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ret = edid_get_timing(buf, ret, timing, &bpc); |
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if (ret) |
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return ret; |
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/* Use this information if valid */ |
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if (bpc != -1) |
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*panel_bppp = bpc * 3; |
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return 0; |
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} |
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/* Somewhat torturous method */ |
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static int get_backlight_info(const void *blob, struct gpio_desc *vdd, |
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struct gpio_desc *enable, int *pwmp) |
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{ |
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int sor, panel, backlight, power; |
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const u32 *prop; |
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int len; |
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int ret; |
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*pwmp = 0; |
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sor = fdtdec_next_compatible(blob, 0, COMPAT_NVIDIA_TEGRA124_SOR); |
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if (sor < 0) |
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return -ENOENT; |
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panel = fdtdec_lookup_phandle(blob, sor, "nvidia,panel"); |
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if (panel < 0) |
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return -ENOENT; |
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backlight = fdtdec_lookup_phandle(blob, panel, "backlight"); |
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if (backlight < 0) |
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return -ENOENT; |
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ret = gpio_request_by_name_nodev(blob, backlight, "enable-gpios", 0, |
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enable, GPIOD_IS_OUT); |
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if (ret) |
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return ret; |
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prop = fdt_getprop(blob, backlight, "pwms", &len); |
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if (!prop || len != 3 * sizeof(u32)) |
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return -EINVAL; |
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*pwmp = fdt32_to_cpu(prop[1]); |
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power = fdtdec_lookup_phandle(blob, backlight, "power-supply"); |
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if (power < 0) |
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return -ENOENT; |
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ret = gpio_request_by_name_nodev(blob, power, "gpio", 0, vdd, |
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GPIOD_IS_OUT); |
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if (ret) |
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goto err; |
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return 0; |
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err: |
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dm_gpio_free(NULL, enable); |
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return ret; |
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} |
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int display_init(void *lcdbase, int fb_bits_per_pixel, |
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struct display_timing *timing) |
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{ |
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struct dc_ctlr *dc_ctlr; |
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const void *blob = gd->fdt_blob; |
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struct udevice *dp_dev; |
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const int href_to_sync = 1, vref_to_sync = 1; |
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int panel_bpp = 18; /* default 18 bits per pixel */ |
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u32 plld_rate; |
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struct gpio_desc vdd_gpio, enable_gpio; |
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int pwm; |
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int node; |
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int ret; |
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ret = uclass_get_device(UCLASS_DISPLAY_PORT, 0, &dp_dev); |
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if (ret) |
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return ret; |
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node = fdtdec_next_compatible(blob, 0, COMPAT_NVIDIA_TEGRA124_DC); |
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if (node < 0) |
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return -ENOENT; |
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dc_ctlr = (struct dc_ctlr *)fdtdec_get_addr(blob, node, "reg"); |
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if (fdtdec_decode_display_timing(blob, node, 0, timing)) |
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return -EINVAL; |
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ret = display_update_config_from_edid(dp_dev, &panel_bpp, timing); |
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if (ret) { |
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debug("%s: Failed to decode EDID, using defaults\n", __func__); |
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dump_config(panel_bpp, timing); |
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} |
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if (!get_backlight_info(blob, &vdd_gpio, &enable_gpio, &pwm)) { |
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dm_gpio_set_value(&vdd_gpio, 1); |
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debug("%s: backlight vdd setting gpio %08x to %d\n", |
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__func__, gpio_get_number(&vdd_gpio), 1); |
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} |
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|
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/*
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* The plld is programmed with the assumption of the SHIFT_CLK_DIVIDER |
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* and PIXEL_CLK_DIVIDER are zero (divide by 1). See the |
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* update_display_mode() for detail. |
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*/ |
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plld_rate = clock_set_display_rate(timing->pixelclock.typ * 2); |
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if (plld_rate == 0) { |
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printf("dc: clock init failed\n"); |
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return -EIO; |
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} else if (plld_rate != timing->pixelclock.typ * 2) { |
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debug("dc: plld rounded to %u\n", plld_rate); |
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timing->pixelclock.typ = plld_rate / 2; |
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} |
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|
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/* Init dc */ |
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ret = tegra_dc_init(dc_ctlr); |
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if (ret) { |
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debug("dc: init failed\n"); |
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return ret; |
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} |
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|
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/* Configure dc mode */ |
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ret = update_display_mode(dc_ctlr, timing, href_to_sync, vref_to_sync); |
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if (ret) { |
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debug("dc: failed to configure display mode\n"); |
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return ret; |
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} |
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|
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/* Enable dp */ |
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ret = display_port_enable(dp_dev, panel_bpp, timing); |
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if (ret) |
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return ret; |
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ret = update_window(dc_ctlr, (ulong)lcdbase, fb_bits_per_pixel, timing); |
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if (ret) |
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return ret; |
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|
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/* Set up Tegra PWM to drive the panel backlight */ |
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pwm_enable(pwm, 0, 220, 0x2e); |
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udelay(10 * 1000); |
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if (dm_gpio_is_valid(&enable_gpio)) { |
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dm_gpio_set_value(&enable_gpio, 1); |
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debug("%s: backlight enable setting gpio %08x to %d\n", |
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__func__, gpio_get_number(&enable_gpio), 1); |
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} |
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return 0; |
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} |
@ -0,0 +1,97 @@ |
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/*
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* Copyright 2014 Google Inc. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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* |
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*/ |
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|
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#include <common.h> |
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#include <errno.h> |
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#include <fdtdec.h> |
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#include <lcd.h> |
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#include <asm/gpio.h> |
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#include <asm/arch-tegra/clk_rst.h> |
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#include <asm/arch/clock.h> |
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#include <asm/arch-tegra/dc.h> |
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#include <asm/io.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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enum { |
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/* Maximum LCD size we support */ |
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LCD_MAX_WIDTH = 1920, |
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LCD_MAX_HEIGHT = 1200, |
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LCD_MAX_LOG2_BPP = 4, /* 2^4 = 16 bpp */ |
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}; |
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|
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vidinfo_t panel_info = { |
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/* Insert a value here so that we don't end up in the BSS */ |
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.vl_col = -1, |
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}; |
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|
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int tegra_lcd_check_next_stage(const void *blob, int wait) |
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{ |
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return 0; |
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} |
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|
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void tegra_lcd_early_init(const void *blob) |
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{ |
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/*
|
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* Go with the maximum size for now. We will fix this up after |
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* relocation. These values are only used for memory alocation. |
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*/ |
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panel_info.vl_col = LCD_MAX_WIDTH; |
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panel_info.vl_row = LCD_MAX_HEIGHT; |
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panel_info.vl_bpix = LCD_MAX_LOG2_BPP; |
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} |
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|
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static int tegra124_lcd_init(void *lcdbase) |
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{ |
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struct display_timing timing; |
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int ret; |
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|
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clock_set_up_plldp(); |
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clock_adjust_periph_pll_div(PERIPH_ID_HOST1X, CLOCK_ID_PERIPH, |
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408000000, NULL); |
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|
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clock_enable(PERIPH_ID_HOST1X); |
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clock_enable(PERIPH_ID_DISP1); |
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clock_enable(PERIPH_ID_PWM); |
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clock_enable(PERIPH_ID_DPAUX); |
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clock_enable(PERIPH_ID_SOR0); |
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|
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udelay(2); |
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|
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reset_set_enable(PERIPH_ID_HOST1X, 0); |
||||
reset_set_enable(PERIPH_ID_DISP1, 0); |
||||
reset_set_enable(PERIPH_ID_PWM, 0); |
||||
reset_set_enable(PERIPH_ID_DPAUX, 0); |
||||
reset_set_enable(PERIPH_ID_SOR0, 0); |
||||
|
||||
ret = display_init(lcdbase, 1 << LCD_BPP, &timing); |
||||
if (ret) |
||||
return ret; |
||||
|
||||
panel_info.vl_col = roundup(timing.hactive.typ, 16); |
||||
panel_info.vl_row = timing.vactive.typ; |
||||
|
||||
lcd_set_flush_dcache(1); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
void lcd_ctrl_init(void *lcdbase) |
||||
{ |
||||
ulong start; |
||||
int ret; |
||||
|
||||
start = get_timer(0); |
||||
ret = tegra124_lcd_init(lcdbase); |
||||
debug("LCD init took %lu ms\n", get_timer(start)); |
||||
if (ret) |
||||
printf("%s: Error %d\n", __func__, ret); |
||||
} |
||||
|
||||
void lcd_enable(void) |
||||
{ |
||||
} |
Loading…
Reference in new issue