The implementation is borrowed from the sheevaplug board and the Marvell 1.1.4 code. Unsupported (or untested) is the SD card, PCIe and SATA. Signed-off-by: Simon Kagstrom <simon.kagstrom@netinsight.net>master
parent
a62e78fc44
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#
|
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# (C) Copyright 2009
|
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# Net Insight <www.netinsight.net>
|
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# Written-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
|
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#
|
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# Based on sheevaplug:
|
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# (C) Copyright 2009
|
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# Marvell Semiconductor <www.marvell.com>
|
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# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
|
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#
|
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# See file CREDITS for list of people who contributed to this
|
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# project.
|
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#
|
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# This program is free software; you can redistribute it and/or
|
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# modify it under the terms of the GNU General Public License as
|
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# published by the Free Software Foundation; either version 2 of
|
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# the License, or (at your option) any later version.
|
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#
|
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# This program is distributed in the hope that it will be useful,
|
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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# GNU General Public License for more details.
|
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#
|
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# You should have received a copy of the GNU General Public License
|
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# along with this program; if not, write to the Free Software
|
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# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
|
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# MA 02110-1301 USA
|
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#
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include $(TOPDIR)/config.mk |
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LIB = $(obj)lib$(BOARD).a
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COBJS := openrd_base.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS) $(SOBJS) |
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$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
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clean: |
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rm -f $(SOBJS) $(OBJS)
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distclean: clean |
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rm -f $(LIB) core *.bak .depend
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#########################################################################
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|
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk |
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sinclude $(obj).depend |
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#########################################################################
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@ -0,0 +1,33 @@ |
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#
|
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# (C) Copyright 2009
|
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# Net Insight <www.netinsight.net>
|
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# Written-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
|
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#
|
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# Based on sheevaplug:
|
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# (C) Copyright 2009
|
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# Marvell Semiconductor <www.marvell.com>
|
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# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
|
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#
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# See file CREDITS for list of people who contributed to this
|
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# project.
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#
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# This program is free software; you can redistribute it and/or
|
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# modify it under the terms of the GNU General Public License as
|
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# published by the Free Software Foundation; either version 2 of
|
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# the License, or (at your option) any later version.
|
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#
|
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# This program is distributed in the hope that it will be useful,
|
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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# GNU General Public License for more details.
|
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#
|
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# You should have received a copy of the GNU General Public License
|
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# along with this program; if not, write to the Free Software
|
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# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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# MA 02110-1301 USA
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#
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TEXT_BASE = 0x00600000
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# Kirkwood Boot Image configuration file
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KWD_CONFIG = $(SRCTREE)/board/$(BOARDDIR)/kwbimage.cfg
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@ -0,0 +1,168 @@ |
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# |
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# (C) Copyright 2009 |
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# Marvell Semiconductor <www.marvell.com> |
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# Written-by: Prafulla Wadaskar <prafulla@marvell.com> |
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# |
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# See file CREDITS for list of people who contributed to this |
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# project. |
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# |
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# This program is free software; you can redistribute it and/or |
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# modify it under the terms of the GNU General Public License as |
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# published by the Free Software Foundation; either version 2 of |
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# the License, or (at your option) any later version. |
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# |
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# This program is distributed in the hope that it will be useful, |
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# but WITHOUT ANY WARRANTY; without even the implied warranty of |
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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# GNU General Public License for more details. |
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# |
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# You should have received a copy of the GNU General Public License |
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# along with this program; if not, write to the Free Software |
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# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, |
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# MA 02110-1301 USA |
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# |
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# Refer docs/README.kwimage for more details about how-to configure |
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# and create kirkwood boot image |
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# |
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# Boot Media configurations |
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BOOT_FROM nand |
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NAND_ECC_MODE default |
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NAND_PAGE_SIZE 0x0800 |
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# SOC registers configuration using bootrom header extension |
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# Maximum KWBIMAGE_MAX_CONFIG configurations allowed |
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# Configure RGMII-0 interface pad voltage to 1.8V |
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DATA 0xFFD100e0 0x1b1b1b9b |
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#Dram initalization for SINGLE x16 CL=5 @ 400MHz |
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DATA 0xFFD01400 0x43000c30 # DDR Configuration register |
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# bit13-0: 0xc30 (3120 DDR2 clks refresh rate) |
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# bit23-14: zero |
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# bit24: 1= enable exit self refresh mode on DDR access |
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# bit25: 1 required |
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# bit29-26: zero |
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# bit31-30: 01 |
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DATA 0xFFD01404 0x37543000 # DDR Controller Control Low |
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# bit 4: 0=addr/cmd in smame cycle |
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# bit 5: 0=clk is driven during self refresh, we don't care for APX |
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# bit 6: 0=use recommended falling edge of clk for addr/cmd |
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# bit14: 0=input buffer always powered up |
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# bit18: 1=cpu lock transaction enabled |
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# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0 |
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# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM |
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# bit30-28: 3 required |
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# bit31: 0=no additional STARTBURST delay |
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DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1) |
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# bit3-0: TRAS lsbs |
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# bit7-4: TRCD |
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# bit11- 8: TRP |
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# bit15-12: TWR |
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# bit19-16: TWTR |
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# bit20: TRAS msb |
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# bit23-21: 0x0 |
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# bit27-24: TRRD |
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# bit31-28: TRTP |
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DATA 0xFFD0140C 0x00000a33 # DDR Timing (High) |
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# bit6-0: TRFC |
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# bit8-7: TR2R |
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# bit10-9: TR2W |
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# bit12-11: TW2W |
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# bit31-13: zero required |
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DATA 0xFFD01410 0x000000cc # DDR Address Control |
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# bit1-0: 00, Cs0width=x8 |
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# bit3-2: 11, Cs0size=1Gb |
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# bit5-4: 00, Cs1width=x8 |
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# bit7-6: 11, Cs1size=1Gb |
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# bit9-8: 00, Cs2width=nonexistent |
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# bit11-10: 00, Cs2size =nonexistent |
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# bit13-12: 00, Cs3width=nonexistent |
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# bit15-14: 00, Cs3size =nonexistent |
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# bit16: 0, Cs0AddrSel |
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# bit17: 0, Cs1AddrSel |
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# bit18: 0, Cs2AddrSel |
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# bit19: 0, Cs3AddrSel |
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# bit31-20: 0 required |
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DATA 0xFFD01414 0x00000000 # DDR Open Pages Control |
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# bit0: 0, OpenPage enabled |
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# bit31-1: 0 required |
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DATA 0xFFD01418 0x00000000 # DDR Operation |
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# bit3-0: 0x0, DDR cmd |
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# bit31-4: 0 required |
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DATA 0xFFD0141C 0x00000C52 # DDR Mode |
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# bit2-0: 2, BurstLen=2 required |
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# bit3: 0, BurstType=0 required |
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# bit6-4: 4, CL=5 |
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# bit7: 0, TestMode=0 normal |
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# bit8: 0, DLL reset=0 normal |
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# bit11-9: 6, auto-precharge write recovery ???????????? |
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# bit12: 0, PD must be zero |
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# bit31-13: 0 required |
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DATA 0xFFD01420 0x00000042 # DDR Extended Mode |
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# bit0: 0, DDR DLL enabled |
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# bit1: 1, DDR drive strength reduced |
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# bit2: 0, DDR ODT control lsd (disabled) |
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# bit5-3: 000, required |
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# bit6: 1, DDR ODT control msb, (disabled) |
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# bit9-7: 000, required |
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# bit10: 0, differential DQS enabled |
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# bit11: 0, required |
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# bit12: 0, DDR output buffer enabled |
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# bit31-13: 0 required |
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DATA 0xFFD01424 0x0000F17F # DDR Controller Control High |
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# bit2-0: 111, required |
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# bit3 : 1 , MBUS Burst Chop disabled |
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# bit6-4: 111, required |
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# bit7 : 0 |
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# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz |
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# bit9 : 0 , no half clock cycle addition to dataout |
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# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals |
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# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh |
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# bit15-12: 1111 required |
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# bit31-16: 0 required |
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DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values) |
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DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values) |
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DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0 |
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DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size |
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# bit0: 1, Window enabled |
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# bit1: 0, Write Protect disabled |
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# bit3-2: 00, CS0 hit selected |
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# bit23-4: ones, required |
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# bit31-24: 0x0F, Size (i.e. 256MB) |
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DATA 0xFFD01508 0x10000000 # CS[1]n Base address to 256Mb |
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DATA 0xFFD0150C 0x0FFFFFF5 # CS[1]n Size 256Mb Window enabled for CS1 |
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DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled |
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DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled |
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DATA 0xFFD01494 0x00120012 # DDR ODT Control (Low) |
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# bit3-0: 0010, (read) M_ODT[0] is asserted during read from DRAM CS1 |
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# bit7-4: 0001, (read) M_ODT[1] is asserted during read from DRAM CS0 |
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# bit19-16: 0010, (write) M_ODT[0] is asserted during write to DRAM CS1. |
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# bit23-20: 0001, (write) M_ODT[1] is asserted during write to DRAM CS0. |
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DATA 0xFFD01498 0x00000000 # DDR ODT Control (High) |
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DATA 0xFFD0149C 0x0000E40f # CPU ODT Control |
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# bit3-0: 1111, internal ODT is asserted during read from DRAM bank 0-3 |
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# bit11-10: 01, M_DQ, M_DM, and M_DQS I/O buffer ODT Select: 150 ohm |
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# bit13-12: 10, M_STARTBURST_IN I/O buffer ODT Select: 75 ohm |
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# bit14: 1, M_STARTBURST_IN ODT: Enabled |
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# bit15: 1, DDR IO ODT Unit: Use ODT block |
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DATA 0xFFD01480 0x00000001 # DDR Initialization Control |
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#bit0=1, enable DDR init upon this register write |
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# End of Header extension |
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DATA 0x0 0x0 |
@ -0,0 +1,160 @@ |
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/*
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* (C) Copyright 2009 |
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* Net Insight <www.netinsight.net> |
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* Written-by: Simon Kagstrom <simon.kagstrom@netinsight.net> |
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* |
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* Based on sheevaplug.c: |
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* (C) Copyright 2009 |
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* Marvell Semiconductor <www.marvell.com> |
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* Written-by: Prafulla Wadaskar <prafulla@marvell.com> |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, |
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* MA 02110-1301 USA |
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*/ |
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#include <common.h> |
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#include <miiphy.h> |
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#include <asm/arch/kirkwood.h> |
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#include <asm/arch/mpp.h> |
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#include "openrd_base.h" |
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DECLARE_GLOBAL_DATA_PTR; |
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int board_init(void) |
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{ |
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/*
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* default gpio configuration |
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* There are maximum 64 gpios controlled through 2 sets of registers |
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* the below configuration configures mainly initial LED status |
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*/ |
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kw_config_gpio(OPENRD_OE_VAL_LOW, |
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OPENRD_OE_VAL_HIGH, |
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OPENRD_OE_LOW, OPENRD_OE_HIGH); |
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|
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/* Multi-Purpose Pins Functionality configuration */ |
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u32 kwmpp_config[] = { |
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MPP0_NF_IO2, |
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MPP1_NF_IO3, |
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MPP2_NF_IO4, |
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MPP3_NF_IO5, |
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MPP4_NF_IO6, |
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MPP5_NF_IO7, |
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MPP6_SYSRST_OUTn, |
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MPP7_GPO, |
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MPP8_TW_SDA, |
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MPP9_TW_SCK, |
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MPP10_UART0_TXD, |
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MPP11_UART0_RXD, |
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MPP12_SD_CLK, |
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MPP13_SD_CMD, /* Alt UART1_TXD */ |
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MPP14_SD_D0, /* Alt UART1_RXD */ |
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MPP15_SD_D1, |
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MPP16_SD_D2, |
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MPP17_SD_D3, |
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MPP18_NF_IO0, |
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MPP19_NF_IO1, |
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MPP20_GE1_0, |
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MPP21_GE1_1, |
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MPP22_GE1_2, |
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MPP23_GE1_3, |
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MPP24_GE1_4, |
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MPP25_GE1_5, |
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MPP26_GE1_6, |
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MPP27_GE1_7, |
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MPP28_GPIO, |
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MPP29_TSMP9, |
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MPP30_GE1_10, |
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MPP31_GE1_11, |
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MPP32_GE1_12, |
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MPP33_GE1_13, |
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MPP34_GPIO, /* UART1 / SD sel */ |
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MPP35_TDM_CH0_TX_QL, |
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MPP36_TDM_SPI_CS1, |
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MPP37_TDM_CH2_TX_QL, |
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MPP38_TDM_CH2_RX_QL, |
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MPP39_AUDIO_I2SBCLK, |
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MPP40_AUDIO_I2SDO, |
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MPP41_AUDIO_I2SLRC, |
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MPP42_AUDIO_I2SMCLK, |
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MPP43_AUDIO_I2SDI, |
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MPP44_AUDIO_EXTCLK, |
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MPP45_TDM_PCLK, |
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MPP46_TDM_FS, |
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MPP47_TDM_DRX, |
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MPP48_TDM_DTX, |
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MPP49_TDM_CH0_RX_QL, |
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0 |
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}; |
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|
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kirkwood_mpp_conf(kwmpp_config); |
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|
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/*
|
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* arch number of board |
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*/ |
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gd->bd->bi_arch_number = MACH_TYPE_OPENRD_BASE; |
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|
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/* adress of boot parameters */ |
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gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; |
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return 0; |
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} |
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|
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int dram_init(void) |
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{ |
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int i; |
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|
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for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { |
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gd->bd->bi_dram[i].start = kw_sdram_bar(i); |
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gd->bd->bi_dram[i].size = kw_sdram_bs(i); |
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} |
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return 0; |
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} |
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|
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#ifdef CONFIG_RESET_PHY_R |
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/* Configure and enable MV88E1116 PHY */ |
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void reset_phy(void) |
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{ |
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u16 reg; |
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u16 devadr; |
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char *name = "egiga0"; |
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|
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if (miiphy_set_current_dev(name)) |
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return; |
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|
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/* command to read PHY dev address */ |
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if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) { |
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printf("Err..%s could not read PHY dev address\n", |
||||
__FUNCTION__); |
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return; |
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} |
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|
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/*
|
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* Enable RGMII delay on Tx and Rx for CPU port |
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* Ref: sec 4.7.2 of chip datasheet |
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*/ |
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miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2); |
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miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®); |
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reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL); |
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miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg); |
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miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0); |
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|
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/* reset the phy */ |
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miiphy_reset(name, devadr); |
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|
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printf("88E1116 Initialized on %s\n", name); |
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} |
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#endif /* CONFIG_RESET_PHY_R */ |
@ -0,0 +1,46 @@ |
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/*
|
||||
* (C) Copyright 2009 |
||||
* Net Insight <www.netinsight.net> |
||||
* Written-by: Simon Kagstrom <simon.kagstrom@netinsight.net> |
||||
* |
||||
* Based on sheevaplug.h: |
||||
* (C) Copyright 2009 |
||||
* Marvell Semiconductor <www.marvell.com> |
||||
* Written-by: Prafulla Wadaskar <prafulla@marvell.com> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, |
||||
* MA 02110-1301 USA |
||||
*/ |
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|
||||
#ifndef __OPENRD_BASE_H |
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#define __OPENRD_BASE_H |
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|
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#define OPENRD_OE_LOW (~(1<<28)) /* RS232 / RS485 */ |
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#define OPENRD_OE_HIGH (~(1<<2)) /* SD / UART1 */ |
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#define OPENRD_OE_VAL_LOW (0) /* Sel RS232 */ |
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#define OPENRD_OE_VAL_HIGH (1 << 2) /* Sel SD */ |
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|
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/* PHY related */ |
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#define MV88E1116_LED_FCTRL_REG 10 |
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#define MV88E1116_CPRSP_CR3_REG 21 |
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#define MV88E1116_MAC_CTRL_REG 21 |
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#define MV88E1116_PGADR_REG 22 |
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#define MV88E1116_RGMII_TXTM_CTRL (1 << 4) |
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#define MV88E1116_RGMII_RXTM_CTRL (1 << 5) |
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|
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#endif /* __OPENRD_BASE_H */ |
@ -0,0 +1,220 @@ |
||||
/*
|
||||
* (C) Copyright 2009 |
||||
* Net Insight <www.netinsight.net> |
||||
* Written-by: Simon Kagstrom <simon.kagstrom@netinsight.net> |
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* |
||||
* Based on sheevaplug.h: |
||||
* (C) Copyright 2009 |
||||
* Marvell Semiconductor <www.marvell.com> |
||||
* Written-by: Prafulla Wadaskar <prafulla@marvell.com> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, |
||||
* MA 02110-1301 USA |
||||
*/ |
||||
|
||||
#ifndef _CONFIG_OPENRD_BASE_H |
||||
#define _CONFIG_OPENRD_BASE_H |
||||
|
||||
/*
|
||||
* Version number information |
||||
*/ |
||||
#define CONFIG_IDENT_STRING "\nOpenRD_base" |
||||
|
||||
/*
|
||||
* High Level Configuration Options (easy to change) |
||||
*/ |
||||
#define CONFIG_MARVELL 1 |
||||
#define CONFIG_ARM926EJS 1 /* Basic Architecture */ |
||||
#define CONFIG_SHEEVA_88SV131 1 /* CPU Core subversion */ |
||||
#define CONFIG_KIRKWOOD 1 /* SOC Family Name */ |
||||
#define CONFIG_KW88F6281 1 /* SOC Name */ |
||||
#define CONFIG_MACH_OPENRD_BASE /* Machine type */ |
||||
|
||||
#define CONFIG_MD5 /* get_random_hex on krikwood needs MD5 support */ |
||||
#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ |
||||
#define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */ |
||||
#define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */ |
||||
#define CONFIG_KIRKWOOD_PCIE_INIT /* Enable PCIE Port0 for kernel */ |
||||
|
||||
/*
|
||||
* CLKs configurations |
||||
*/ |
||||
#define CONFIG_SYS_HZ 1000 |
||||
|
||||
/*
|
||||
* NS16550 Configuration |
||||
*/ |
||||
#define CONFIG_SYS_NS16550 |
||||
#define CONFIG_SYS_NS16550_SERIAL |
||||
#define CONFIG_SYS_NS16550_REG_SIZE (-4) |
||||
#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK |
||||
#define CONFIG_SYS_NS16550_COM1 KW_UART0_BASE |
||||
|
||||
/*
|
||||
* Serial Port configuration |
||||
* The following definitions let you select what serial you want to use |
||||
* for your console driver. |
||||
*/ |
||||
|
||||
#define CONFIG_CONS_INDEX 1 /*Console on UART0 */ |
||||
#define CONFIG_BAUDRATE 115200 |
||||
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \ |
||||
115200,230400, 460800, 921600 } |
||||
/* auto boot */ |
||||
#define CONFIG_BOOTDELAY 3 /* default enable autoboot */ |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 8 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization. |
||||
*/ |
||||
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ |
||||
#define CONFIG_INITRD_TAG 1 /* enable INITRD tag */ |
||||
#define CONFIG_SETUP_MEMORY_TAGS 1 /* enable memory tag */ |
||||
|
||||
#define CONFIG_SYS_PROMPT "Marvell>> " /* Command Prompt */ |
||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */ |
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ |
||||
+sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buff */ |
||||
/*
|
||||
* Commands configuration |
||||
*/ |
||||
#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */ |
||||
#include <config_cmd_default.h> |
||||
#define CONFIG_CMD_AUTOSCRIPT |
||||
#define CONFIG_CMD_DHCP |
||||
#define CONFIG_CMD_ENV |
||||
#define CONFIG_CMD_FAT |
||||
#define CONFIG_CMD_NAND |
||||
#define CONFIG_CMD_MII |
||||
#define CONFIG_CMD_PING |
||||
#define CONFIG_CMD_USB |
||||
|
||||
/*
|
||||
* NAND configuration |
||||
*/ |
||||
#ifdef CONFIG_CMD_NAND |
||||
#define CONFIG_NAND_KIRKWOOD |
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1 |
||||
#define NAND_MAX_CHIPS 1 |
||||
#define CONFIG_SYS_NAND_BASE 0xD8000000 /* KW_DEFADR_NANDF */ |
||||
#define NAND_ALLOW_ERASE_ALL 1 |
||||
#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ |
||||
#endif |
||||
|
||||
/*
|
||||
* Environment variables configurations |
||||
*/ |
||||
#ifdef CONFIG_CMD_NAND |
||||
#define CONFIG_ENV_IS_IN_NAND 1 |
||||
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K */ |
||||
#else |
||||
#define CONFIG_ENV_IS_NOWHERE 1 /* if env in SDRAM */ |
||||
#endif |
||||
/*
|
||||
* max 4k env size is enough, but in case of nand |
||||
* it has to be rounded to sector size |
||||
*/ |
||||
#define CONFIG_ENV_SIZE 0x20000 /* 128k */ |
||||
#define CONFIG_ENV_ADDR 0x60000 |
||||
#define CONFIG_ENV_OFFSET 0x60000 /* env starts here */ |
||||
|
||||
/*
|
||||
* Default environment variables |
||||
*/ |
||||
#define CONFIG_BOOTCOMMAND "${x_bootcmd_kernel}; " \ |
||||
"setenv bootargs ${x_bootargs} ${x_bootargs_root}; " \
|
||||
"${x_bootcmd_usb}; bootm 0x6400000;" |
||||
|
||||
#define MTDIDS_DEFAULT "nand0=nand_mtd" |
||||
#define MTDPARTS_DEFAULT "mtdparts=nand_mtd:0x100000@0x000000(uboot),"\ |
||||
"0x400000@0x100000(uImage),"\
|
||||
"0x1fb00000@0x500000(rootfs)" |
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS "x_bootargs=console" \ |
||||
"=ttyS0,115200 "MTDPARTS_DEFAULT " rw ubi.mtd=2,2048\0" \
|
||||
"x_bootcmd_kernel=nand read 0x6400000 0x100000 0x300000\0" \
|
||||
"x_bootcmd_usb=usb start\0" \
|
||||
"x_bootargs_root=root=ubi0:rootfs rootfstype=ubifs\0" \
|
||||
"mtdids="MTDIDS_DEFAULT"\0" \
|
||||
"mtdparts="MTDPARTS_DEFAULT"\0" |
||||
|
||||
/*
|
||||
* Size of malloc() pool |
||||
*/ |
||||
#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* 1MiB for malloc() */ |
||||
/* size in bytes reserved for initial data */ |
||||
#define CONFIG_SYS_GBL_DATA_SIZE 128 |
||||
|
||||
/*
|
||||
* Other required minimal configurations |
||||
*/ |
||||
#define CONFIG_SYS_LONGHELP |
||||
#define CONFIG_AUTO_COMPLETE |
||||
#define CONFIG_CMDLINE_EDITING |
||||
#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */ |
||||
#define CONFIG_ARCH_MISC_INIT /* call arch_misc_init() */ |
||||
#define CONFIG_DISPLAY_CPUINFO /* Display cpu info */ |
||||
#define CONFIG_NR_DRAM_BANKS 4 |
||||
#define CONFIG_STACKSIZE 0x00100000 /* regular stack- 1M */ |
||||
#define CONFIG_SYS_LOAD_ADDR 0x00800000 /* default load adr- 8M */ |
||||
#define CONFIG_SYS_MEMTEST_START 0x00400000 /* 4M */ |
||||
#define CONFIG_SYS_MEMTEST_END 0x007fffff /*(_8M -1) */ |
||||
#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */ |
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
||||
|
||||
/*
|
||||
* Ethernet Driver configuration |
||||
*/ |
||||
#ifdef CONFIG_CMD_NET |
||||
#define CONFIG_NETCONSOLE /* include NetConsole support */ |
||||
#define CONFIG_NET_MULTI /* specify more that one ports available */ |
||||
#define CONFIG_MII /* expose smi ove miiphy interface */ |
||||
#define CONFIG_KIRKWOOD_EGIGA /* Enable kirkwood Gbe Controller Driver */ |
||||
#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */ |
||||
#define CONFIG_KIRKWOOD_EGIGA_PORTS {1,0} /* enable port 0 only */ |
||||
#define CONFIG_PHY_BASE_ADR 0x8 |
||||
#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */ |
||||
#define CONFIG_RESET_PHY_R /* use reset_phy() to init mv8831116 PHY */ |
||||
#endif /* CONFIG_CMD_NET */ |
||||
|
||||
/*
|
||||
* USB/EHCI |
||||
*/ |
||||
#ifdef CONFIG_CMD_USB |
||||
#define CONFIG_USB_EHCI /* Enable EHCI USB support */ |
||||
#define CONFIG_USB_EHCI_KIRKWOOD /* on Kirkwood platform */ |
||||
#define CONFIG_EHCI_IS_TDI |
||||
#define CONFIG_USB_STORAGE |
||||
#define CONFIG_DOS_PARTITION |
||||
#define CONFIG_ISO_PARTITION |
||||
#define CONFIG_SUPPORT_VFAT |
||||
#endif /* CONFIG_CMD_USB */ |
||||
|
||||
/*
|
||||
* File system |
||||
*/ |
||||
#define CONFIG_CMD_UBI |
||||
#define CONFIG_CMD_UBIFS |
||||
#define CONFIG_RBTREE |
||||
#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ |
||||
#define CONFIG_MTD_PARTITIONS |
||||
#define CONFIG_CMD_MTDPARTS |
||||
#define CONFIG_LZO |
||||
|
||||
#endif /* _CONFIG_OPENRD_BASE_H */ |
Loading…
Reference in new issue