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@ -116,10 +116,10 @@ static const struct { |
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* |
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* The return value is the actual bus speed that is set. |
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*/ |
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static unsigned int set_i2c_bus_speed(const struct fsl_i2c_base *base, |
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unsigned int i2c_clk, unsigned int speed) |
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static uint set_i2c_bus_speed(const struct fsl_i2c_base *base, |
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uint i2c_clk, uint speed) |
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{ |
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unsigned short divider = min(i2c_clk / speed, (unsigned int)USHRT_MAX); |
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ushort divider = min(i2c_clk / speed, (uint)USHRT_MAX); |
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/*
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* We want to choose an FDR/DFSR that generates an I2C bus speed that |
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@ -130,8 +130,8 @@ static unsigned int set_i2c_bus_speed(const struct fsl_i2c_base *base, |
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#ifdef __PPC__ |
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u8 dfsr, fdr = 0x31; /* Default if no FDR found */ |
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/* a, b and dfsr matches identifiers A,B and C respectively in AN2919 */ |
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unsigned short a, b, ga, gb; |
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unsigned long c_div, est_div; |
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ushort a, b, ga, gb; |
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ulong c_div, est_div; |
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#ifdef CONFIG_FSL_I2C_CUSTOM_DFSR |
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dfsr = CONFIG_FSL_I2C_CUSTOM_DFSR; |
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@ -151,18 +151,21 @@ static unsigned int set_i2c_bus_speed(const struct fsl_i2c_base *base, |
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for (ga = 0x4, a = 10; a <= 30; ga++, a += 2) { |
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for (gb = 0; gb < 8; gb++) { |
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b = 16 << gb; |
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c_div = b * (a + ((3*dfsr)/b)*2); |
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if ((c_div > divider) && (c_div < est_div)) { |
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unsigned short bin_gb, bin_ga; |
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c_div = b * (a + ((3 * dfsr) / b) * 2); |
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if (c_div > divider && c_div < est_div) { |
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ushort bin_gb, bin_ga; |
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est_div = c_div; |
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bin_gb = gb << 2; |
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bin_ga = (ga & 0x3) | ((ga & 0x4) << 3); |
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fdr = bin_gb | bin_ga; |
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speed = i2c_clk / est_div; |
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debug("FDR:0x%.2x, div:%ld, ga:0x%x, gb:0x%x, " |
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"a:%d, b:%d, speed:%d\n", |
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fdr, est_div, ga, gb, a, b, speed); |
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debug("FDR: 0x%.2x, ", fdr); |
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debug("div: %ld, ", est_div); |
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debug("ga: 0x%x, gb: 0x%x, ", ga, gb); |
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debug("a: %d, b: %d, speed: %d\n", a, b, speed); |
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/* Condition 2 not accounted for */ |
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debug("Tr <= %d ns\n", |
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(b - 3 * dfsr) * 1000000 / |
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@ -174,13 +177,13 @@ static unsigned int set_i2c_bus_speed(const struct fsl_i2c_base *base, |
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if (a == 24) |
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a += 4; |
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} |
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debug("divider:%d, est_div:%ld, DFSR:%d\n", divider, est_div, dfsr); |
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debug("FDR:0x%.2x, speed:%d\n", fdr, speed); |
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debug("divider: %d, est_div: %ld, DFSR: %d\n", divider, est_div, dfsr); |
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debug("FDR: 0x%.2x, speed: %d\n", fdr, speed); |
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#endif |
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writeb(dfsr, &base->dfsrr); /* set default filter */ |
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writeb(fdr, &base->fdr); /* set bus speed */ |
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#else |
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unsigned int i; |
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uint i; |
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for (i = 0; i < ARRAY_SIZE(fsl_i2c_speed_map); i++) |
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if (fsl_i2c_speed_map[i].divider >= divider) { |
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@ -197,7 +200,7 @@ static unsigned int set_i2c_bus_speed(const struct fsl_i2c_base *base, |
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} |
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#ifndef CONFIG_DM_I2C |
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static unsigned int get_i2c_clock(int bus) |
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static uint get_i2c_clock(int bus) |
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{ |
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if (bus) |
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return gd->arch.i2c2_clk; /* I2C2 clock */ |
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@ -211,10 +214,11 @@ static int fsl_i2c_fixup(const struct fsl_i2c_base *base) |
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const unsigned long long timeout = usec2ticks(CONFIG_I2C_MBB_TIMEOUT); |
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unsigned long long timeval = 0; |
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int ret = -1; |
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unsigned int flags = 0; |
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uint flags = 0; |
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#ifdef CONFIG_SYS_FSL_ERRATUM_I2C_A004447 |
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unsigned int svr = get_svr(); |
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uint svr = get_svr(); |
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if ((SVR_SOC_VER(svr) == SVR_8548 && IS_SVR_REV(svr, 3, 1)) || |
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(SVR_REV(svr) <= CONFIG_SYS_FSL_A004447_SVR_REV)) |
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flags = I2C_CR_BIT6; |
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@ -263,7 +267,7 @@ static void __i2c_init(const struct fsl_i2c_base *base, int speed, int |
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/* Call board specific i2c bus reset routine before accessing the
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* environment, which might be in a chip on that bus. For details |
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* about this problem see doc/I2C_Edge_Conditions. |
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*/ |
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*/ |
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i2c_init_board(); |
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#endif |
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writeb(0, &base->cr); /* stop I2C controller */ |
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@ -286,8 +290,7 @@ static void __i2c_init(const struct fsl_i2c_base *base, int speed, int |
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} |
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} |
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static int |
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i2c_wait4bus(const struct fsl_i2c_base *base) |
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static int i2c_wait4bus(const struct fsl_i2c_base *base) |
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{ |
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unsigned long long timeval = get_ticks(); |
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const unsigned long long timeout = usec2ticks(CONFIG_I2C_MBB_TIMEOUT); |
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@ -300,8 +303,7 @@ i2c_wait4bus(const struct fsl_i2c_base *base) |
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return 0; |
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} |
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static inline int |
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i2c_wait(const struct fsl_i2c_base *base, int write) |
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static int i2c_wait(const struct fsl_i2c_base *base, int write) |
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{ |
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u32 csr; |
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unsigned long long timeval = get_ticks(); |
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@ -317,29 +319,29 @@ i2c_wait(const struct fsl_i2c_base *base, int write) |
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writeb(0x0, &base->sr); |
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if (csr & I2C_SR_MAL) { |
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debug("i2c_wait: MAL\n"); |
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debug("%s: MAL\n", __func__); |
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return -1; |
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} |
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if (!(csr & I2C_SR_MCF)) { |
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debug("i2c_wait: unfinished\n"); |
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debug("%s: unfinished\n", __func__); |
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return -1; |
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} |
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if (write == I2C_WRITE_BIT && (csr & I2C_SR_RXAK)) { |
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debug("i2c_wait: No RXACK\n"); |
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debug("%s: No RXACK\n", __func__); |
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return -1; |
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} |
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return 0; |
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} while ((get_ticks() - timeval) < timeout); |
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debug("i2c_wait: timed out\n"); |
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debug("%s: timed out\n", __func__); |
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return -1; |
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} |
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static inline int |
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i2c_write_addr(const struct fsl_i2c_base *base, u8 dev, u8 dir, int rsta) |
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static int i2c_write_addr(const struct fsl_i2c_base *base, u8 dev, |
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u8 dir, int rsta) |
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{ |
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writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX |
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| (rsta ? I2C_CR_RSTA : 0), |
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@ -353,8 +355,8 @@ i2c_write_addr(const struct fsl_i2c_base *base, u8 dev, u8 dir, int rsta) |
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return 1; |
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} |
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static inline int |
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__i2c_write_data(const struct fsl_i2c_base *base, u8 *data, int length) |
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static int __i2c_write_data(const struct fsl_i2c_base *base, u8 *data, |
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int length) |
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{ |
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int i; |
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@ -368,8 +370,8 @@ __i2c_write_data(const struct fsl_i2c_base *base, u8 *data, int length) |
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return i; |
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} |
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static inline int |
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__i2c_read_data(const struct fsl_i2c_base *base, u8 *data, int length) |
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static int __i2c_read_data(const struct fsl_i2c_base *base, u8 *data, |
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int length) |
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{ |
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int i; |
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@ -399,9 +401,8 @@ __i2c_read_data(const struct fsl_i2c_base *base, u8 *data, int length) |
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return i; |
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} |
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static int |
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__i2c_read(const struct fsl_i2c_base *base, u8 chip_addr, u8 *offset, int olen, |
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u8 *data, int dlen) |
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static int __i2c_read(const struct fsl_i2c_base *base, u8 chip_addr, u8 *offset, |
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int olen, u8 *data, int dlen) |
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{ |
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int ret = -1; /* signal error */ |
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@ -447,9 +448,8 @@ __i2c_read(const struct fsl_i2c_base *base, u8 chip_addr, u8 *offset, int olen, |
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return -1; |
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} |
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static int |
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__i2c_write(const struct fsl_i2c_base *base, u8 chip_addr, u8 *offset, int olen, |
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u8 *data, int dlen) |
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static int __i2c_write(const struct fsl_i2c_base *base, u8 chip_addr, |
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u8 *offset, int olen, u8 *data, int dlen) |
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{ |
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int ret = -1; /* signal error */ |
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@ -471,10 +471,9 @@ __i2c_write(const struct fsl_i2c_base *base, u8 chip_addr, u8 *offset, int olen, |
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return -1; |
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} |
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static int |
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__i2c_probe_chip(const struct fsl_i2c_base *base, uchar chip) |
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static int __i2c_probe_chip(const struct fsl_i2c_base *base, uchar chip) |
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{ |
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/* For unknow reason the controller will ACK when
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/* For unknown reason the controller will ACK when
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* probing for a slave with the same address, so skip |
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* it. |
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*/ |
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@ -484,8 +483,8 @@ __i2c_probe_chip(const struct fsl_i2c_base *base, uchar chip) |
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return __i2c_read(base, chip, 0, 0, NULL, 0); |
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} |
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static unsigned int __i2c_set_bus_speed(const struct fsl_i2c_base *base, |
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unsigned int speed, int i2c_clk) |
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static uint __i2c_set_bus_speed(const struct fsl_i2c_base *base, |
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uint speed, int i2c_clk) |
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{ |
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writeb(0, &base->cr); /* stop controller */ |
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set_i2c_bus_speed(base, i2c_clk, speed); |
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@ -501,32 +500,30 @@ static void fsl_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd) |
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get_i2c_clock(adap->hwadapnr), adap->hwadapnr); |
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} |
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static int |
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fsl_i2c_probe_chip(struct i2c_adapter *adap, uchar chip) |
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static int fsl_i2c_probe_chip(struct i2c_adapter *adap, uchar chip) |
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{ |
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return __i2c_probe_chip(i2c_base[adap->hwadapnr], chip); |
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} |
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static int |
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fsl_i2c_read(struct i2c_adapter *adap, u8 chip_addr, uint offset, int olen, |
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u8 *data, int dlen) |
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static int fsl_i2c_read(struct i2c_adapter *adap, u8 chip_addr, uint offset, |
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int olen, u8 *data, int dlen) |
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{ |
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u8 *o = (u8 *)&offset; |
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return __i2c_read(i2c_base[adap->hwadapnr], chip_addr, &o[4 - olen], |
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olen, data, dlen); |
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} |
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static int |
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fsl_i2c_write(struct i2c_adapter *adap, u8 chip_addr, uint offset, int olen, |
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u8 *data, int dlen) |
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static int fsl_i2c_write(struct i2c_adapter *adap, u8 chip_addr, uint offset, |
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int olen, u8 *data, int dlen) |
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{ |
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u8 *o = (u8 *)&offset; |
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return __i2c_write(i2c_base[adap->hwadapnr], chip_addr, &o[4 - olen], |
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olen, data, dlen); |
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} |
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static unsigned int fsl_i2c_set_bus_speed(struct i2c_adapter *adap, |
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unsigned int speed) |
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static uint fsl_i2c_set_bus_speed(struct i2c_adapter *adap, uint speed) |
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{ |
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return __i2c_set_bus_speed(i2c_base[adap->hwadapnr], speed, |
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get_i2c_clock(adap->hwadapnr)); |
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@ -562,12 +559,14 @@ static int fsl_i2c_probe_chip(struct udevice *bus, u32 chip_addr, |
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u32 chip_flags) |
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{ |
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struct fsl_i2c_dev *dev = dev_get_priv(bus); |
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return __i2c_probe_chip(dev->base, chip_addr); |
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} |
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static int fsl_i2c_set_bus_speed(struct udevice *bus, unsigned int speed) |
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static int fsl_i2c_set_bus_speed(struct udevice *bus, uint speed) |
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{ |
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struct fsl_i2c_dev *dev = dev_get_priv(bus); |
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return __i2c_set_bus_speed(dev->base, speed, dev->i2c_clk); |
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} |
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@ -575,22 +574,18 @@ static int fsl_i2c_ofdata_to_platdata(struct udevice *bus) |
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{ |
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struct fsl_i2c_dev *dev = dev_get_priv(bus); |
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fdt_addr_t addr; |
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fdt_size_t size; |
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int node = dev_of_offset(bus); |
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addr = fdtdec_get_addr_size_auto_noparent(gd->fdt_blob, node, "reg", 0, |
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&size, false); |
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addr = dev_read_u32_default(bus, "reg", -1); |
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dev->base = map_sysmem(CONFIG_SYS_IMMR + addr, size); |
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dev->base = map_sysmem(CONFIG_SYS_IMMR + addr, sizeof(struct fsl_i2c_base)); |
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if (!dev->base) |
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return -ENOMEM; |
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dev->index = fdtdec_get_int(gd->fdt_blob, node, "cell-index", -1); |
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dev->slaveadd = fdtdec_get_int(gd->fdt_blob, node, |
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"u-boot,i2c-slave-addr", 0x7f); |
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dev->speed = fdtdec_get_int(gd->fdt_blob, node, "clock-frequency", |
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400000); |
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dev->index = dev_read_u32_default(bus, "cell-index", -1); |
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dev->slaveadd = dev_read_u32_default(bus, "u-boot,i2c-slave-addr", |
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0x7f); |
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dev->speed = dev_read_u32_default(bus, "clock-frequency", 400000); |
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dev->i2c_clk = dev->index ? gd->arch.i2c2_clk : gd->arch.i2c1_clk; |
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@ -600,6 +595,7 @@ static int fsl_i2c_ofdata_to_platdata(struct udevice *bus) |
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static int fsl_i2c_probe(struct udevice *bus) |
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{ |
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struct fsl_i2c_dev *dev = dev_get_priv(bus); |
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__i2c_init(dev->base, dev->speed, dev->slaveadd, dev->i2c_clk, |
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dev->index); |
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return 0; |
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@ -613,7 +609,8 @@ static int fsl_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs) |
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memset(&dummy, 0, sizeof(struct i2c_msg)); |
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/* We expect either two messages (one with an offset and one with the
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* actucal data) or one message (just data) */ |
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* actual data) or one message (just data) |
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*/ |
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if (nmsgs > 2 || nmsgs == 0) { |
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debug("%s: Only one or two messages are supported.", __func__); |
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return -1; |
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