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@ -117,6 +117,49 @@ static void ccgr_init(void) |
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writel(0x000003FF, &ccm->CCGR6); |
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} |
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#ifdef CONFIG_MX6_DDRCAL |
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static void spl_dram_print_cal(struct mx6_ddr_sysinfo const *sysinfo) |
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{ |
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struct mx6_mmdc_calibration calibration = {0}; |
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mmdc_read_calibration(sysinfo, &calibration); |
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debug(".p0_mpdgctrl0\t= 0x%08X\n", calibration.p0_mpdgctrl0); |
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debug(".p0_mpdgctrl1\t= 0x%08X\n", calibration.p0_mpdgctrl1); |
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debug(".p0_mprddlctl\t= 0x%08X\n", calibration.p0_mprddlctl); |
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debug(".p0_mpwrdlctl\t= 0x%08X\n", calibration.p0_mpwrdlctl); |
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debug(".p0_mpwldectrl0\t= 0x%08X\n", calibration.p0_mpwldectrl0); |
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debug(".p0_mpwldectrl1\t= 0x%08X\n", calibration.p0_mpwldectrl1); |
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debug(".p1_mpdgctrl0\t= 0x%08X\n", calibration.p1_mpdgctrl0); |
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debug(".p1_mpdgctrl1\t= 0x%08X\n", calibration.p1_mpdgctrl1); |
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debug(".p1_mprddlctl\t= 0x%08X\n", calibration.p1_mprddlctl); |
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debug(".p1_mpwrdlctl\t= 0x%08X\n", calibration.p1_mpwrdlctl); |
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debug(".p1_mpwldectrl0\t= 0x%08X\n", calibration.p1_mpwldectrl0); |
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debug(".p1_mpwldectrl1\t= 0x%08X\n", calibration.p1_mpwldectrl1); |
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} |
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static void spl_dram_perform_cal(struct mx6_ddr_sysinfo const *sysinfo) |
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{ |
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int ret; |
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/* Perform DDR DRAM calibration */ |
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udelay(100); |
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ret = mmdc_do_write_level_calibration(sysinfo); |
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if (ret) { |
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printf("DDR: Write level calibration error [%d]\n", ret); |
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return; |
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} |
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ret = mmdc_do_dqs_calibration(sysinfo); |
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if (ret) { |
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printf("DDR: DQS calibration error [%d]\n", ret); |
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return; |
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} |
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spl_dram_print_cal(sysinfo); |
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} |
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#endif /* CONFIG_MX6_DDRCAL */ |
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static void spl_dram_init(void) |
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{ |
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struct mx6_ddr_sysinfo sysinfo = { |
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@ -143,6 +186,10 @@ static void spl_dram_init(void) |
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mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs); |
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mx6_dram_cfg(&sysinfo, &mx6_4x256mx16_mmdc_calib, &mt41k128m16jt_125); |
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#ifdef CONFIG_MX6_DDRCAL |
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spl_dram_perform_cal(&sysinfo); |
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#endif |
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} |
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#ifdef CONFIG_SPL_SPI_SUPPORT |
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