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ARM: UniPhier: support 1CS support card for all the UniPhier SoCs

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Two support card variants are used with UniPhier reference boards:
 - 1 chip select support card (original CPLD)
 - 3 chip selects support card (ARIMA-compatible CPLD)

Currently, the former is only supported on PH1-Pro4, but it can be
expanded to PH1-LD4, PH1-sLD8 with a little code change.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
master
Masahiro Yamada 9 years ago
parent 53c45d4e1e
commit ea6de4ac80
9 changed files with 189 additions and 121 deletions
Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL
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  1. 4
      arch/arm/mach-uniphier/ph1-ld4/Makefile
  2. 56
      arch/arm/mach-uniphier/ph1-ld4/sbc_init.c
  3. 50
      arch/arm/mach-uniphier/ph1-ld4/sbc_init_3cs.c
  4. 4
      arch/arm/mach-uniphier/ph1-pro4/Makefile
  5. 32
      arch/arm/mach-uniphier/ph1-pro4/sbc_init.c
  6. 43
      arch/arm/mach-uniphier/ph1-pro4/sbc_init_3cs.c
  7. 4
      arch/arm/mach-uniphier/ph1-sld8/Makefile
  8. 59
      arch/arm/mach-uniphier/ph1-sld8/sbc_init.c
  9. 58
      arch/arm/mach-uniphier/ph1-sld8/sbc_init_3cs.c

4
arch/arm/mach-uniphier/ph1-ld4/Makefile
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@ -4,8 +4,10 @@
ifdef CONFIG_SPL_BUILD
obj-$(CONFIG_DEBUG_LL) += lowlevel_debug.o
obj-y += bcu_init.o sbc_init.o sg_init.o pll_init.o early_clkrst_init.o \
obj-y += bcu_init.o sg_init.o pll_init.o early_clkrst_init.o \
pll_spectrum.o umc_init.o ddrphy_init.o
obj-$(CONFIG_PFC_MICRO_SUPPORT_CARD) += sbc_init.o
obj-$(CONFIG_DCC_MICRO_SUPPORT_CARD) += sbc_init_3cs.o
else
obj-$(CONFIG_BOARD_EARLY_INIT_F) += pinctrl.o clkrst_init.o
obj-$(if $(CONFIG_OF_CONTROL),,y) += platdevice.o

56
arch/arm/mach-uniphier/ph1-ld4/sbc_init.c
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@ -19,32 +19,32 @@ void sbc_init(void)
tmp &= 0xfffffcff;
writel(tmp, PC0CTRL);
/* XECS1: sub/boot memory (boot swap = off/on) */
writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL10);
writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL11);
writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL12);
writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL14);
/* XECS0: boot/sub memory (boot swap = off/on) */
writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL00);
writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL01);
writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL02);
writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL04);
/* XECS3: peripherals */
writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL30);
writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL31);
writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL32);
writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL34);
/* base address regsiters */
writel(0x0000bc01, SBBASE0);
writel(0x0400bc01, SBBASE1);
writel(0x0800bf01, SBBASE3);
/* enable access to sub memory when boot swap is on */
if (boot_is_swapped())
sg_set_pinsel(155, 1); /* PORT24 -> XECS0 */
sg_set_pinsel(156, 1); /* PORT25 -> XECS3 */
/*
* Only CS1 is connected to support card.
* BKSZ[1:0] should be set to "01".
*/
writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL10);
writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL11);
writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL12);
writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL14);
if (boot_is_swapped()) {
/*
* Boot Swap On: boot from external NOR/SRAM
* 0x02000000-0x03ffffff is a mirror of 0x00000000-0x01ffffff.
*
* 0x00000000-0x01efffff, 0x02000000-0x03efffff: memory bank
* 0x01f00000-0x01ffffff, 0x03f00000-0x03ffffff: peripherals
*/
writel(0x0000bc01, SBBASE0);
} else {
/*
* Boot Swap Off: boot from mask ROM
* 0x00000000-0x01ffffff: mask ROM
* 0x02000000-0x03efffff: memory bank (31MB)
* 0x03f00000-0x03ffffff: peripherals (1MB)
*/
writel(0x0000be01, SBBASE0); /* dummy */
writel(0x0200be01, SBBASE1);
}
}

50
arch/arm/mach-uniphier/ph1-ld4/sbc_init_3cs.c
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@ -0,0 +1,50 @@
/*
* Copyright (C) 2011-2015 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <mach/sbc-regs.h>
#include <mach/sg-regs.h>
void sbc_init(void)
{
u32 tmp;
/* system bus output enable */
tmp = readl(PC0CTRL);
tmp &= 0xfffffcff;
writel(tmp, PC0CTRL);
/* XECS1: sub/boot memory (boot swap = off/on) */
writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL10);
writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL11);
writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL12);
writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL14);
/* XECS0: boot/sub memory (boot swap = off/on) */
writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL00);
writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL01);
writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL02);
writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL04);
/* XECS3: peripherals */
writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL30);
writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL31);
writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL32);
writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL34);
/* base address regsiters */
writel(0x0000bc01, SBBASE0);
writel(0x0400bc01, SBBASE1);
writel(0x0800bf01, SBBASE3);
/* enable access to sub memory when boot swap is on */
if (boot_is_swapped())
sg_set_pinsel(155, 1); /* PORT24 -> XECS0 */
sg_set_pinsel(156, 1); /* PORT25 -> XECS3 */
}

4
arch/arm/mach-uniphier/ph1-pro4/Makefile
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@ -4,8 +4,10 @@
ifdef CONFIG_SPL_BUILD
obj-$(CONFIG_DEBUG_LL) += lowlevel_debug.o
obj-y += sbc_init.o sg_init.o pll_init.o early_clkrst_init.o \
obj-y += sg_init.o pll_init.o early_clkrst_init.o \
pll_spectrum.o umc_init.o ddrphy_init.o
obj-$(CONFIG_PFC_MICRO_SUPPORT_CARD) += sbc_init.o
obj-$(CONFIG_DCC_MICRO_SUPPORT_CARD) += sbc_init_3cs.o
else
obj-$(CONFIG_BOARD_EARLY_INIT_F) += pinctrl.o clkrst_init.o
obj-$(if $(CONFIG_OF_CONTROL),,y) += platdevice.o

32
arch/arm/mach-uniphier/ph1-pro4/sbc_init.c
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@ -12,7 +12,6 @@
void sbc_init(void)
{
#if defined(CONFIG_PFC_MICRO_SUPPORT_CARD)
/*
* Only CS1 is connected to support card.
* BKSZ[1:0] should be set to "01".
@ -41,35 +40,4 @@ void sbc_init(void)
writel(0x0000be01, SBBASE0); /* dummy */
writel(0x0200be01, SBBASE1);
}
#elif defined(CONFIG_DCC_MICRO_SUPPORT_CARD)
/* XECS0: boot/sub memory (boot swap = off/on) */
writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL00);
writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL01);
writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL02);
writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL04);
/* XECS1: sub/boot memory (boot swap = off/on) */
writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL10);
writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL11);
writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL12);
writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL14);
/* XECS3: peripherals */
writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL30);
writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL31);
writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL32);
writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL34);
writel(0x0000bc01, SBBASE0); /* boot memory */
writel(0x0400bc01, SBBASE1); /* sub memory */
writel(0x0800bf01, SBBASE3); /* peripherals */
/* enable access to sub memory when boot swap is on */
if (boot_is_swapped())
sg_set_pinsel(318, 5); /* PORT22 -> XECS0 */
sg_set_pinsel(313, 5); /* PORT15 -> XECS3 */
writel(0x00000001, SG_LOADPINCTRL);
#endif /* CONFIG_XXX_MICRO_SUPPORT_CARD */
}

43
arch/arm/mach-uniphier/ph1-pro4/sbc_init_3cs.c
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@ -0,0 +1,43 @@
/*
* Copyright (C) 2011-2015 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <mach/sbc-regs.h>
#include <mach/sg-regs.h>
void sbc_init(void)
{
/* XECS0: boot/sub memory (boot swap = off/on) */
writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL00);
writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL01);
writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL02);
writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL04);
/* XECS1: sub/boot memory (boot swap = off/on) */
writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL10);
writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL11);
writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL12);
writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL14);
/* XECS3: peripherals */
writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL30);
writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL31);
writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL32);
writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL34);
writel(0x0000bc01, SBBASE0); /* boot memory */
writel(0x0400bc01, SBBASE1); /* sub memory */
writel(0x0800bf01, SBBASE3); /* peripherals */
/* enable access to sub memory when boot swap is on */
if (boot_is_swapped())
sg_set_pinsel(318, 5); /* PORT22 -> XECS0 */
sg_set_pinsel(313, 5); /* PORT15 -> XECS3 */
writel(0x00000001, SG_LOADPINCTRL);
}

4
arch/arm/mach-uniphier/ph1-sld8/Makefile
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@ -4,8 +4,10 @@
ifdef CONFIG_SPL_BUILD
obj-$(CONFIG_DEBUG_LL) += lowlevel_debug.o
obj-y += bcu_init.o sbc_init.o sg_init.o pll_init.o early_clkrst_init.o \
obj-y += bcu_init.o sg_init.o pll_init.o early_clkrst_init.o \
pll_spectrum.o umc_init.o ddrphy_init.o
obj-$(CONFIG_PFC_MICRO_SUPPORT_CARD) += sbc_init.o
obj-$(CONFIG_DCC_MICRO_SUPPORT_CARD) += sbc_init_3cs.o
else
obj-$(CONFIG_BOARD_EARLY_INIT_F) += pinctrl.o clkrst_init.o
obj-$(if $(CONFIG_OF_CONTROL),,y) += platdevice.o

59
arch/arm/mach-uniphier/ph1-sld8/sbc_init.c
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@ -1,58 +1 @@
/*
* Copyright (C) 2011-2015 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <mach/sbc-regs.h>
#include <mach/sg-regs.h>
void sbc_init(void)
{
u32 tmp;
/* system bus output enable */
tmp = readl(PC0CTRL);
tmp &= 0xfffffcff;
writel(tmp, PC0CTRL);
/*
* SBCTRL0* does not need settings because PH1-sLD8 has no support for
* XECS0. The boot swap must be enabled to boot from the support card.
*/
if (boot_is_swapped()) {
/* XECS1 : boot memory if boot swap is on */
writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL10);
writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL11);
writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL12);
writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL14);
}
/* XECS4 : sub memory */
writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL40);
writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL41);
writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL42);
writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL44);
/* XECS5 : peripherals */
writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL50);
writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL51);
writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL52);
writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL54);
/* base address regsiters */
writel(0x0000bc01, SBBASE0); /* boot memory */
writel(0x0900bfff, SBBASE1); /* dummy */
writel(0x0400bc01, SBBASE4); /* sub memory */
writel(0x0800bf01, SBBASE5); /* peripherals */
sg_set_pinsel(134, 16); /* XIRQ6 -> XECS4 */
sg_set_pinsel(135, 16); /* XIRQ7 -> XECS5 */
/* dummy read to assure write process */
readl(SG_PINCTRL(0));
}
#include "../ph1-ld4/sbc_init.c"

58
arch/arm/mach-uniphier/ph1-sld8/sbc_init_3cs.c
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@ -0,0 +1,58 @@
/*
* Copyright (C) 2011-2015 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <mach/sbc-regs.h>
#include <mach/sg-regs.h>
void sbc_init(void)
{
u32 tmp;
/* system bus output enable */
tmp = readl(PC0CTRL);
tmp &= 0xfffffcff;
writel(tmp, PC0CTRL);
/*
* SBCTRL0* does not need settings because PH1-sLD8 has no support for
* XECS0. The boot swap must be enabled to boot from the support card.
*/
if (boot_is_swapped()) {
/* XECS1 : boot memory if boot swap is on */
writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL10);
writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL11);
writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL12);
writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL14);
}
/* XECS4 : sub memory */
writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL40);
writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL41);
writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL42);
writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL44);
/* XECS5 : peripherals */
writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL50);
writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL51);
writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL52);
writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL54);
/* base address regsiters */
writel(0x0000bc01, SBBASE0); /* boot memory */
writel(0x0900bfff, SBBASE1); /* dummy */
writel(0x0400bc01, SBBASE4); /* sub memory */
writel(0x0800bf01, SBBASE5); /* peripherals */
sg_set_pinsel(134, 16); /* XIRQ6 -> XECS4 */
sg_set_pinsel(135, 16); /* XIRQ7 -> XECS5 */
/* dummy read to assure write process */
readl(SG_PINCTRL(0));
}
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