ppc4xx: Update 440EPx lwmon5 board support

- Clear ECC status regs after ECC POST test
- Set dcbz for ECC generation with caches enabled as default
- Code cleanup

Signed-off-by: Stefan Roese <sr@denx.de>
master
Stefan Roese 18 years ago
parent 27a528fb41
commit ea9f6bce38
  1. 37
      board/lwmon5/sdram.c
  2. 1
      include/configs/lwmon5.h
  3. 13
      include/ppc440.h
  4. 12
      post/board/lwmon5/ecc.c
  5. 2
      post/cpu/ppc4xx/fpu.c

@ -473,7 +473,7 @@ static void program_ecc(u32 start_address,
blank_string(strlen(str));
} else {
/* ECC bit set method for cached memory */
#if 1 /* test-only: will remove this define later, when ECC problems are solved! */
#if 0 /* test-only: will remove this define later, when ECC problems are solved! */
/*
* Some boards (like lwmon5) need to preserve the memory
* content upon ECC generation (for the log-buffer).
@ -486,6 +486,11 @@ static void program_ecc(u32 start_address,
current_address = start_address;
while (current_address < end_address) {
/*
* TODO: Th following sequence doesn't work correctly.
* Just invalidating and flushing the cache doesn't
* seem to trigger the re-write of the memory.
*/
ppcDcbi(current_address);
ppcDcbf(current_address);
current_address += CFG_CACHELINE_SIZE;
@ -514,19 +519,6 @@ static void program_ecc(u32 start_address,
}
#endif
static __inline__ u32 get_mcsr(void)
{
u32 val;
asm volatile("mfspr %0, 0x23c" : "=r" (val) :);
return val;
}
static __inline__ void set_mcsr(u32 val)
{
asm volatile("mtspr 0x23c, %0" : "=r" (val) :);
}
/*************************************************************************
*
* initdram -- 440EPx's DDR controller is a DENALI Core
@ -534,8 +526,6 @@ static __inline__ void set_mcsr(u32 val)
************************************************************************/
long int initdram (int board_type)
{
u32 val;
#if 0 /* test-only: will remove this define later, when ECC problems are solved! */
/* CL=3 */
mtsdram(DDR0_02, 0x00000000);
@ -640,14 +630,6 @@ long int initdram (int board_type)
* Perform data eye search if requested.
*/
denali_core_search_data_eye(CFG_DDR_CACHED_ADDR, CFG_MBYTES_SDRAM << 20);
/*
* Clear possible errors resulting from data-eye-search.
* If not done, then we could get an interrupt later on when
* exceptions are enabled.
*/
val = get_mcsr();
set_mcsr(val);
#endif
#ifdef CONFIG_DDR_ECC
@ -657,5 +639,12 @@ long int initdram (int board_type)
program_ecc(CFG_DDR_CACHED_ADDR, CFG_MBYTES_SDRAM << 20, 0);
#endif
/*
* Clear possible errors resulting from data-eye-search.
* If not done, then we could get an interrupt later on when
* exceptions are enabled.
*/
set_mcsr(get_mcsr());
return (CFG_MBYTES_SDRAM << 20);
}

@ -140,7 +140,6 @@
/* POST support */
#define CONFIG_POST (CFG_POST_ECC)
#endif
/*-----------------------------------------------------------------------

@ -3354,6 +3354,19 @@ typedef struct {
unsigned long pciClkSync; /* PCI clock is synchronous */
} PPC440_SYS_INFO;
static inline u32 get_mcsr(void)
{
u32 val;
asm volatile("mfspr %0, 0x23c" : "=r" (val) :);
return val;
}
static inline void set_mcsr(u32 val)
{
asm volatile("mtspr 0x23c, %0" : "=r" (val) :);
}
#endif /* _ASMLANGUAGE */
#define RESET_VECTOR 0xfffffffc

@ -236,7 +236,6 @@ int ecc_post_test (int flags)
mfsdram(DDR0_00, value);
mtsdram(DDR0_00, value | DDR0_00_INT_ACK_ALL);
/* enable full support of ECC */
mfsdram(DDR0_22, value);
mtsdram(DDR0_22, (value &~ DDR0_22_CTRL_RAW_MASK)
@ -247,6 +246,17 @@ int ecc_post_test (int flags)
if (ret)
break;
}
/* clear error status */
mfsdram(DDR0_00, value);
mtsdram(DDR0_00, value | DDR0_00_INT_ACK_ALL);
/*
* Clear possible errors resulting from ECC testing.
* If not done, then we could get an interrupt later on when
* exceptions are enabled.
*/
set_mcsr(get_mcsr());
#endif
return ret;

@ -29,8 +29,8 @@
#if defined(CONFIG_440EP) || \
defined(CONFIG_440EPX)
#include <ppc4xx.h>
#include <asm/processor.h>
#include <ppc4xx.h>
int fpu_status(void)

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