From 70205e5a6ddc8528b11db9eb4d3fa0209d9fce2a Mon Sep 17 00:00:00 2001 From: Haiying Wang Date: Tue, 30 May 2006 08:51:19 -0500 Subject: [PATCH 1/2] Fix two SDRAM setup bugs. Fix ECC setup bug. Enable 1T/2T based on number of DIMMs present. Signed-off-by: Haiying Wang --- cpu/mpc86xx/spd_sdram.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/cpu/mpc86xx/spd_sdram.c b/cpu/mpc86xx/spd_sdram.c index 130c8fc..f30bbbd 100644 --- a/cpu/mpc86xx/spd_sdram.c +++ b/cpu/mpc86xx/spd_sdram.c @@ -1088,24 +1088,24 @@ unsigned int enable_ddr(unsigned int ddr_num) * If the user wanted ECC (enabled via sdram_cfg[2]) */ if (config == 0x02) { + ddr->err_disable = 0x00000000; + asm("sync;isync;"); + ddr->err_sbe = 0x00ff0000; + ddr->err_int_en = 0x0000000d; sdram_cfg_1 |= 0x20000000; /* ECC_EN */ } #endif /* - * REV1 uses 1T timing. - * REV2 may use 1T or 2T as configured by the user. + * Set 1T or 2T timing based on 1 or 2 modules */ { - uint pvr = get_pvr(); - - if (pvr != PVR_85xx_REV1) { -#if defined(CONFIG_DDR_2T_TIMING) + if (!(no_dimm1 || no_dimm2)) { /* + * 2T timing,because both DIMMS are present. * Enable 2T timing by setting sdram_cfg[16]. */ sdram_cfg_1 |= 0x8000; /* 2T_EN */ -#endif } } From 38cee12dcfcc257371c901c7e13e58ecab0a35d8 Mon Sep 17 00:00:00 2001 From: Haiying Wang Date: Tue, 30 May 2006 09:10:32 -0500 Subject: [PATCH 2/2] Improve "reset" command's interaction with watchdog. "reset altbank" will reset another bank WITHOUT watch dog timer enabled "reset altbank wd" will reset another bank WITH watch dog enabled "diswd" will disable watch dog after u-boot boots up successfully Signed-off-by: Haiying Wang --- cpu/mpc86xx/cpu.c | 37 ++++++++++++++++++++++++++++++++----- 1 file changed, 32 insertions(+), 5 deletions(-) diff --git a/cpu/mpc86xx/cpu.c b/cpu/mpc86xx/cpu.c index 36da777..5c6c2ee 100644 --- a/cpu/mpc86xx/cpu.c +++ b/cpu/mpc86xx/cpu.c @@ -169,7 +169,7 @@ soft_restart(unsigned long addr) int set_px_sysclk(ulong sysclk) { - u8 sysclk_s, sysclk_r, sysclk_v, vclkh, vclkl, sysclk_aux,tmp; + u8 sysclk_s, sysclk_r, sysclk_v, vclkh, vclkl, sysclk_aux; /* Per table 27, page 58 of MPC8641HPCN spec*/ switch(sysclk) @@ -354,6 +354,24 @@ void set_px_go_with_watchdog(void) out8(PIXIS_BASE+PIXIS_VCTL,tmp); } +int disable_watchdog(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + u8 tmp; + tmp = in8(PIXIS_BASE+PIXIS_VCTL); + tmp = tmp & 0x1E; + out8(PIXIS_BASE+PIXIS_VCTL,tmp); + tmp = in8(PIXIS_BASE + PIXIS_VCTL); + tmp &= ~ 0x08; /* setting VCTL[WDEN] to 0 to disable watch dog */ + out8(PIXIS_BASE + PIXIS_VCTL, tmp); + return 0; +} + +U_BOOT_CMD( + diswd, 1, 0, disable_watchdog, + "diswd - Disable watchdog timer \n", + NULL +); + /* This function takes the non-integral cpu:mpx pll ratio * and converts it to an integer that can be used to assign * FPGA register values. @@ -509,18 +527,27 @@ do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) goto my_usage; while(1); /* Not reached */ - } else { - /* Reset from next bank without changing frequencies */ + } else if(argv[2][1] == 'd'){ + /* Reset from next bank without changing frequencies but with watchdog timer enabled */ read_from_px_regs(0); read_from_px_regs_altbank(0); - if(argc > 2) - goto my_usage; printf("Setting registers VCFGEN1, VBOOT, and VCTL\n"); set_altbank(); read_from_px_regs_altbank(1); printf("Enabling watchdog timer on the FPGA and resetting board to boot from the other bank....\n"); set_px_go_with_watchdog(); while(1); /* Not reached */ + } else { + /* Reset from next bank without changing frequency and without watchdog timer enabled */ + read_from_px_regs(0); + read_from_px_regs_altbank(0); + if(argc > 2) + goto my_usage; + printf("Setting registers VCFGNE1, VBOOT, and VCTL\n"); + set_altbank(); + read_from_px_regs_altbank(1); + printf("Resetting board to boot from the other bank....\n"); + set_px_go(); } default: