MIPSfpga is an FPGA based dev platform. In a nutshell, its a microAptiv cpu core with lots of Xilinx IP blocks The FPGA dev board used is the Nexys4DDR board by Digilent. For more information, check the Readme file in board/imgtec/xilfpga Signed-off-by: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com> Reviewed-by: Paul Burton <paul.burton@imgtec.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>master
Zubair Lutfullah Kakakhel
8 years ago
committed by
Daniel Schwierzeck
parent
d4e85377e7
commit
ebf2b9e3df
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if TARGET_XILFPGA |
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config SYS_BOARD |
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default "xilfpga" |
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config SYS_VENDOR |
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default "imgtec" |
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config SYS_CONFIG_NAME |
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default "imgtec_xilfpga" |
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config SYS_TEXT_BASE |
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default 0x80C00000 |
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endif |
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XILFPGA BOARD |
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M: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com> |
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S: Maintained |
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F: board/imgtec/xilfpga |
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F: include/configs/xilfpga.h |
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F: configs/imgtec_xilfpga_defconfig |
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#
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# Copyright (C) 2016, Imagination Technologies Ltd.
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# Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com>
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y := xilfpga.o
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/* |
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* Copyright (C) 2016, Imagination Technologies Ltd. |
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* |
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* Zubair Lutfullah Kakakhel, Zubair.Kakakhel@imgtec.com |
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*/ |
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MIPSfpga |
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======================================= |
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MIPSfpga is an FPGA based development platform by Imagination Technologies |
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As we are dealing with a MIPS core instantiated on an FPGA, specifications |
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are fluid and can be varied in RTL. |
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The example project provided by IMGTEC runs on the Nexys4DDR board by |
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Digilent powered by the ARTIX-7 FPGA by Xilinx. Relevant details about |
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the example project and the Nexys4DDR board: |
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- microAptiv UP core m14Kc |
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- 50MHz clock speed |
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- 128Mbyte DDR RAM at 0x0000_0000 |
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- 8Kbyte RAM at 0x1000_0000 |
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- axi_intc at 0x1020_0000 |
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- axi_uart16550 at 0x1040_0000 |
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- axi_gpio at 0x1060_0000 |
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- axi_i2c at 0x10A0_0000 |
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- custom_gpio at 0x10C0_0000 |
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- axi_ethernetlite at 0x10E0_0000 |
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- 8Kbyte BootRAM at 0x1FC0_0000 |
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- 16Mbyte QPI at 0x1D00_0000 |
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Boot protocol: |
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-------------- |
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The BootRAM is a writeable "RAM" in FPGA at 0x1FC0_0000. |
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This is for easy reprogrammibility via JTAG. |
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DDR initialization is already handled by a HW IP block. |
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When the example project bitstream is loaded, the cpu_reset button |
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needs to be pressed. |
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The bootram initializes the cache and axi_uart |
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Then checks if there is anything non 0xffff_ffff at location 0x1D40_0000 |
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If there is, then that is considered as u-boot. u-boot is copied from |
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0x1D40_0000 to memory and the bootram jumps into u-boot code. |
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At this point, the board is ready to load the Linux kernel + buildroot initramfs |
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This can be done in multiple ways: |
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1- JTAG load the binary and jump into it. |
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2- Load kernel stored in the QSPI flash at 0x1D80_0000 |
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3- Load uImage via tftp. Ethernet works in u-boot. |
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e.g. env set server ip 192.168.154.45; dhcp uImage; bootm |
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/*
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* Imagination Technologies MIPSfpga platform code |
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* |
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* Copyright (C) 2016, Imagination Technologies Ltd. |
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* |
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* Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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* |
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*/ |
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#include <common.h> |
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/* initialize the DDR Controller and PHY */ |
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phys_size_t initdram(int board_type) |
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{ |
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/* MIG IP block is smart and doesn't need SW
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* to do any init */ |
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return CONFIG_SYS_SDRAM_SIZE; /* in bytes */ |
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} |
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CONFIG_MIPS=y |
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CONFIG_SYS_MALLOC_F_LEN=0x600 |
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CONFIG_TARGET_XILFPGA=y |
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# CONFIG_MIPS_BOOT_ENV_LEGACY is not set |
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CONFIG_MIPS_BOOT_FDT=y |
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CONFIG_DEFAULT_DEVICE_TREE="nexys4ddr" |
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CONFIG_BOOTDELAY=5 |
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CONFIG_HUSH_PARSER=y |
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CONFIG_SYS_PROMPT="MIPSfpga # " |
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# CONFIG_CMD_IMLS is not set |
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# CONFIG_CMD_SAVEENV is not set |
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CONFIG_CMD_MEMINFO=y |
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# CONFIG_CMD_FLASH is not set |
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# CONFIG_CMD_FPGA is not set |
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CONFIG_CMD_DHCP=y |
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CONFIG_CMD_MII=y |
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CONFIG_CMD_PING=y |
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CONFIG_CMD_TIME=y |
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CONFIG_OF_EMBED=y |
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CONFIG_NET_RANDOM_ETHADDR=y |
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CONFIG_NETCONSOLE=y |
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CONFIG_CLK=y |
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CONFIG_XILINX_EMACLITE=y |
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CONFIG_SYS_NS16550=y |
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CONFIG_CMD_DHRYSTONE=y |
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/*
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* Copyright (C) 2016, Imagination Technologies Ltd. |
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* |
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* Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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* |
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* Imagination Technologies Ltd. MIPSfpga |
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*/ |
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#ifndef __XILFPGA_CONFIG_H |
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#define __XILFPGA_CONFIG_H |
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/* BootROM + MIG is pretty smart. DDR and Cache initialized */ |
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#define CONFIG_SKIP_LOWLEVEL_INIT |
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/*--------------------------------------------
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* CPU configuration |
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*/ |
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/* CPU Timer rate */ |
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#define CONFIG_SYS_MIPS_TIMER_FREQ 50000000 |
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/* Cache Configuration */ |
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#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT |
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/*----------------------------------------------------------------------
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* Memory Layout |
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*/ |
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/* SDRAM Configuration (for final code, data, stack, heap) */ |
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#define CONFIG_SYS_SDRAM_BASE 0x80000000 |
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#define CONFIG_SYS_SDRAM_SIZE 0x08000000 /* 128 Mbytes */ |
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#define CONFIG_SYS_INIT_SP_ADDR \ |
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(CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE - 0x1000) |
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#define CONFIG_SYS_MALLOC_LEN (256 << 10) |
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
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#define CONFIG_SYS_LOAD_ADDR 0x80500000 /* default load address */ |
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/*----------------------------------------------------------------------
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* Commands |
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*/ |
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#define CONFIG_SYS_LONGHELP /* undef to save memory */ |
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/*-------------------------------------------------
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* FLASH configuration |
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*/ |
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#define CONFIG_SYS_NO_FLASH |
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/*------------------------------------------------------------
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* Console Configuration |
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*/ |
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#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args*/ |
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#define CONFIG_BAUDRATE 115200 |
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/* -------------------------------------------------
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* Environment |
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*/ |
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#define CONFIG_ENV_IS_NOWHERE 1 |
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#define CONFIG_ENV_SIZE 0x4000 |
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/* ---------------------------------------------------------------------
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* Board boot configuration |
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*/ |
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#define CONFIG_TIMESTAMP /* Print image info with timestamp */ |
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#endif /* __XILFPGA_CONFIG_H */ |
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