1: - board/altera/common/flash.c:flash_erase(): o allow interrupts befor get_timer() call o check-up each erased sector and avoid unexpected timeouts - board/altera/dk1c20/dk1s10.c:board_early_init_f(): o enclose sevenseg_set() in cpp condition - remove the ASMI configuration for DK1S10_standard_32 (never present) - fix some typed in mistakes in the NIOS documentation 2: - split DK1C20 configuration into several header files: o two new files for each NIOS CPU description o U-Boot related part is remaining in DK1C20.h 3: - split DK1S10 configuration into several header files: o two new files for each NIOS CPU description o U-Boot related part is remaining in DK1S10.h 4: - Add support for the Microtronix Linux Development Kit NIOS CPU configuration at the Altera Nios Development Kit, Stratix Edition (DK-1S10) 5: - Add documentation for the Altera Nios Development Kit, Stratix Edition (DK-1S10) 6: - Add support for the Nios Serial Peripharel Interface (SPI) (master only) 7: - Add support for the common U-Boot SPI framework at RTC driver DS1306master
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/*
|
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* (C) Copyright 2004, Li-Pro.Net <www.li-pro.net> |
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* Stephan Linz <linz@li-pro.net> |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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|
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#include <common.h> |
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#include <linux/ctype.h> |
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#if defined(CONFIG_NIOS_SPI) |
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#include <nios-io.h> |
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#include <spi.h> |
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#if !defined(CFG_NIOS_SPIBASE) |
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#error "*** CFG_NIOS_SPIBASE not defined ***" |
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#endif |
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#if !defined(CFG_NIOS_SPIBITS) |
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#error "*** CFG_NIOS_SPIBITS not defined ***" |
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#endif |
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#if (CFG_NIOS_SPIBITS != 8) && (CFG_NIOS_SPIBITS != 16) |
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#error "*** CFG_NIOS_SPIBITS should be either 8 or 16 ***" |
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#endif |
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static nios_spi_t *spi = (nios_spi_t *)CFG_NIOS_SPIBASE; |
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|
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/* Warning:
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* You cannot enable DEBUG for early system initalization, i. e. when |
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* this driver is used to read environment parameters like "baudrate" |
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* from EEPROM which are used to initialize the serial port which is |
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* needed to print the debug messages... |
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*/ |
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#undef DEBUG |
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#ifdef DEBUG |
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#define DPRINT(a) printf a; |
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/* -----------------------------------------------
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* Helper functions to peek into tx and rx buffers |
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* ----------------------------------------------- */ |
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static const char * const hex_digit = "0123456789ABCDEF"; |
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static char quickhex (int i) |
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{ |
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return hex_digit[i]; |
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} |
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static void memdump (void *pv, int num) |
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{ |
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int i; |
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unsigned char *pc = (unsigned char *) pv; |
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for (i = 0; i < num; i++) |
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printf ("%c%c ", quickhex (pc[i] >> 4), quickhex (pc[i] & 0x0f)); |
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printf ("\t"); |
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for (i = 0; i < num; i++) |
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printf ("%c", isprint (pc[i]) ? pc[i] : '.'); |
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printf ("\n"); |
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} |
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#else /* !DEBUG */ |
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#define DPRINT(a) |
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#define memdump(p,n) |
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#endif /* DEBUG */ |
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/*
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* SPI transfer: |
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* |
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* See include/spi.h and http://www.altera.com/literature/ds/ds_nios_spi.pdf
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* for more informations. |
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*/ |
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int spi_xfer(spi_chipsel_type chipsel, int bitlen, uchar *dout, uchar *din) |
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{ |
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int j; |
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DPRINT(("spi_xfer: chipsel %08X dout %08X din %08X bitlen %d\n", |
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(int)chipsel, *(uint *)dout, *(uint *)din, bitlen)); |
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memdump((void*)dout, (bitlen + 7) / 8); |
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if(chipsel != NULL) { |
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chipsel(1); /* select the target chip */ |
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} |
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if (bitlen > CFG_NIOS_SPIBITS) { /* leave chip select active */ |
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spi->control |= NIOS_SPI_SSO; |
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} |
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for ( j = 0; /* count each byte in */ |
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j < ((bitlen + 7) / 8); /* dout[] and din[] */ |
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#if (CFG_NIOS_SPIBITS == 8) |
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j++) { |
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while ((spi->status & NIOS_SPI_TRDY) == 0) |
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; |
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spi->txdata = (unsigned)(dout[j]); |
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while ((spi->status & NIOS_SPI_RRDY) == 0) |
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; |
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din[j] = (unsigned char)(spi->rxdata & 0xff); |
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#elif (CFG_NIOS_SPIBITS == 16) |
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j++, j++) { |
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while ((spi->status & NIOS_SPI_TRDY) == 0) |
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; |
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if ((j+1) < ((bitlen + 7) / 8)) |
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spi->txdata = (unsigned)((dout[j] << 8) | dout[j+1]); |
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else |
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spi->txdata = (unsigned)(dout[j] << 8); |
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while ((spi->status & NIOS_SPI_RRDY) == 0) |
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; |
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din[j] = (unsigned char)((spi->rxdata >> 8) & 0xff); |
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if ((j+1) < ((bitlen + 7) / 8)) |
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din[j+1] = (unsigned char)(spi->rxdata & 0xff); |
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#else |
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#error "*** unsupported value of CFG_NIOS_SPIBITS ***" |
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#endif |
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} |
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if (bitlen > CFG_NIOS_SPIBITS) { |
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spi->control &= ~NIOS_SPI_SSO; |
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} |
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if(chipsel != NULL) { |
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chipsel(0); /* deselect the target chip */ |
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} |
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memdump((void*)din, (bitlen + 7) / 8); |
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return 0; |
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} |
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#endif /* CONFIG_NIOS_SPI */ |
@ -0,0 +1,131 @@ |
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Nios Development Kit |
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Startix Editions |
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Last Update: January 28, 2004 |
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==================================================================== |
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This file contains information regarding U-Boot and the Altera |
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Nios Development Kit, Startix Edition (DK-1S10). For general Nios |
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information see doc/README.nios. |
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Most stuff of this file was borrowed and based on README.dk1c20, |
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the DK-1C20 related information file. |
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For those interested in contributing ... see HELP WANTED section |
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in doc/README.nios. |
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Contents: |
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1. Files |
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2. Memory Organization |
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3. CPU Variations |
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4. Examples |
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5. Programming U-Boot into FLASH with GERMS |
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|
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==================================================================== |
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1. Files |
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========= |
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board/altera/dk1s10/* |
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include/configs/DK1S10.h |
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2. Memory Organization |
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======================= |
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-The heap is placed below the monitor (U-Boot code). |
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-Global data is placed below the heap. |
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-The stack is placed below global data (&grows down). |
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|
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3. CPU Variations |
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================= |
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There are more than one NIOS CPU variation for the DK-1S10. U-Boot |
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supports the following CPU configurations: |
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- Altera Standard 32 (make DK1S10_standard_32_config) |
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- Microtronix LDK 2.0 (make DK1S10_mtx_ldk_20_config) |
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4. Examples |
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============ |
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The hello_world example was never tested on DK-1S10. Neverthelse |
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it should work as far as possible, because the DK-1S10 port is |
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more than ninetieth percents equal to the DK-1C20 port and at |
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this platform the hello_world example was already tested |
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successfully (see README.dk1c20). |
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5. Programming U-Boot into FLASH with GERMS |
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============================================ |
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The current version of the DK-1S10 port with the default |
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configuration settings occupies about 78 KBytes of flash. |
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A minimal configuration occupies less than 60 KByte |
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(network support disabled). |
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To program U-Boot into the DK-1S10 flash using GERMS do the |
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following: |
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1. From the command line, download U-Boot using the nios-run: |
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$ nios-run -r u-boot.srec |
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This takes about 45 seconds (GERMS is not very speedy here). |
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After u-boot is downloaded it will be executed. You should |
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see the following: |
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U-Boot 1.0.2 (Jan 28 2004 - 19:02:30) |
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CPU: Nios-32 Rev. 3.3 (0x3038) |
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Reg file size: 256 LO_LIMIT/HI_LIMIT: 2/14 |
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Board: Altera Nios 1S10 Development Kit |
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In: serial |
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Out: serial |
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Err: serial |
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DK1S10 > |
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2. Quit nios-run and start your terminal application (e.g. start |
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Hyperterminal or minicom). |
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3. Download the u-boot code to RAM. When using Hyperterminal, do the |
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following: |
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a. From the u-boot command prompt start a binary download to |
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SRAM / SDRAM: |
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at the Altera Standard 32 to SRAM: |
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==> loadb 800000 |
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at the Microtronix LDK 2.0 to SDRAM: |
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==> loadb 1010000 |
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b. Download u-boot.bin using kermit. |
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4. From the U-Boot command prompt, erase flash: |
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at the Altera Standard 32 from 0x40000 to 0x5ffff: |
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==> erase 1:4-5 |
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at the Microtronix LDK 2.0 from 0x8000000 to 0x81ffff: |
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==> erase 1:0-1 |
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5. Copy the binary image from SRAM / SDRAM to flash: |
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at the Altera Standard 32 to SRAM: |
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==> cp.b 800000 40000 $(filesize) |
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at the Microtronix LDK 2.0 to SDRAM: |
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==> cp.b 1010000 8000000 $(filesize) |
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U-Boot will now automatically start when the board is powered on or |
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reset using the Standard-32 configuration. To start U-Boot with the |
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Safe-32 configuration, enter the following GERMS command: |
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+ g 40000 |
@ -0,0 +1,286 @@ |
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TODO: specify IDE i/f |
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=============================================================================== |
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C P U , M E M O R Y , I N / O U T C O M P O N E N T S |
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=============================================================================== |
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see also [1]-[5] |
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CPU: "LDK2" |
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32 bit NIOS for 75 MHz |
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512 Byte for register file (30 levels) |
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with out instruction cache |
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with out data cache |
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2 KByte On Chip ROM with GERMS boot monitor |
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with out On Chip RAM |
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MSTEP multiplier |
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no Debug Core |
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no On Chip Instrumentation (OCI) |
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U-Boot CFG: CFG_NIOS_CPU_CLK = 75000000 |
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CFG_NIOS_CPU_ICACHE = (not present) |
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CFG_NIOS_CPU_DCACHE = (not present) |
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CFG_NIOS_CPU_REG_NUMS = 512 |
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CFG_NIOS_CPU_MUL = 0 |
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CFG_NIOS_CPU_MSTEP = 1 |
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CFG_NIOS_CPU_DBG_CORE = 0 |
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IRQ: Nr. | used by |
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------+-------------------------------------------------------- |
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16 | TIMER0 | CFG_NIOS_CPU_TIMER0_IRQ = 16 |
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17 | UART0 | CFG_NIOS_CPU_UART0_IRQ = 17 |
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18 | UART1 | CFG_NIOS_CPU_UART1_IRQ = 18 |
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20 | LAN91C111 | CFG_NIOS_CPU_LAN0_IRQ = 20 |
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25 | IDE0 | CFG_NIOS_CPU_IDE0_IRQ = 25 |
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MEMORY: 8 MByte Flash |
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16 MByte SDRAM |
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Timer: TIMER0: high priority programmable timer (IRQ16) |
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U-Boot CFG: CFG_NIOS_CPU_TICK_TIMER = 0 |
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CFG_NIOS_CPU_USER_TIMER = (not present) |
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PIO: Nr. | description |
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------+-------------------------------------------------------- |
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PIO0 | CFPOWER: 1 output to controll CF power supply |
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PIO1 | BUTTON: 4 inputs for user push buttons (no IRQ) |
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------+-------------------------------------------------------- |
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not | LCD: 11 in/outputs for ASCII LCD |
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pres.| LED: 8 outputs for user LEDs |
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| SEVENSEG: 16 outputs for user seven segment display |
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| RECONF: 1 in/output for . . . . . . . . . . . . |
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| CFPRESENT: 1 input for CF present event (IRQ35) |
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| CFATASEL: 1 output to controll CF ATA card select |
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U-Boot CFG: CFG_NIOS_CPU_BUTTON_PIO = 1 |
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CFG_NIOS_CPU_LCD_PIO = (not present) |
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CFG_NIOS_CPU_LED_PIO = (not present) |
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CFG_NIOS_CPU_SEVENSEG_PIO = (not present) |
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CFG_NIOS_CPU_RECONF_PIO = (not present) |
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CFG_NIOS_CPU_CFPRESENT_PIO = (not present) |
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CFG_NIOS_CPU_CFPOWER_PIO = 0 |
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CFG_NIOS_CPU_CFATASEL_PIO = (not present) |
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UART: UART0: fixed baudrate of 115200, fixed protocol 8N2, |
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without handshake RTS/CTS (IRQ17) |
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UART1: fixed baudrate of 115200, fixed protocol 8N1, |
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without handshake RTS/CTS (IRQ18) |
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LAN: SMsC LAN91C111 with: |
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- offset 0x300 (LAN91C111_REGISTERS_OFFSET) |
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- data bus width 32 bit (LAN91C111_DATA_BUS_WIDTH) |
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IDE: (TODO) |
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=============================================================================== |
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M E M O R Y M A P |
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=============================================================================== |
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- - - - - - - - - - - external memory - - - - - - - - - - - - - - - - - - - |
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0x02000000 ---32-----------16|15------------0- CFG_NIOS_CPU_STACK |
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0x02000000 --+32-----------16|15------------0+ |
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| . | \ \ |
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| . | | | |
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| . | | > stack area |
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| . | | | |
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| . | | V |
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| . | | |
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| . | | |
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SDRAM | . | > CFG_NIOS_CPU_SDRAM_SIZE |
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| . | | = 0x01000000 |
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| . | | |
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0x01000100 |- - - - - - - - - - - - - - - -+-|- |
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| . | | \ |
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| . | | | |
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| . | | > CFG_NIOS_CPU_VEC_SIZE |
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| . | | | = 0x00000100 |
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| | / / |
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0x01000000 |- - - - - - - - - - - - - - - -+- - CFG_NIOS_CPU_VEC_BASE |
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0x01000000 ---32-----------16|15------------0- CFG_NIOS_CPU_SDRAM_BASE |
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| sector 127 | \ |
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+ 0x7f0000 |- - - - - - - - - - - - - - - -| | |
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| : | | |
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Flash |- - - - : - - - -| > CFG_NIOS_CPU_FLASH_SIZE |
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| sector 1 : | | = 0x00800000 |
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+ 0x010000 |- - - - - - - - - - - - - - - -| | |
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| sector 0 (size = 0x10000) | / |
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0x00800000 ---8-------------4|3-------------0- CFG_NIOS_CPU_FLASH_BASE |
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| | |
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: gap : |
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: : |
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- - - - - - - - - - - external i/o - - - - - - - - - - - - - - - - - - - |
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: : |
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: gap : |
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| | |
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0x00020000 ---32-----------16|15------------0- |
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| gap | \ |
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0x00010310 --+-------------------------------| | |
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| | | |
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| register bank (size = 0x10) | | |
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| +--------.---.---.--- | | |
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| | bank 0 \ 1 \ 2 \ 3 \ | | |
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| |---------------------------+ | | |
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LAN91C111 | | BANK | RESERVED | | | |
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| |- - - - - - -|- - - - - - -| | > na_enet_size |
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| | RPCR | MIR | | | = 0x00010000 |
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| |- - - - - - -|- - - - - - -| | | |
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| | COUNTER | RCR | | | |
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| |- - - - - - -|- - - - - - -| | | |
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| | EPH STATUS | TCR | | | |
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| +---------------------------+ | | |
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0x00010300 --+--LAN91C111_REGISTERS_OFFSET---| | |
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| gap | / |
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0x00010000 ---32-----------16|15------------0- CFG_NIOS_CPU_LAN0_BASE |
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| | |
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: gap : |
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: : |
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- - - - - - - - - - - on chip i/o - - - - - - - - - - - - - - - - - - - |
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|
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: : |
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: gap : |
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| | |
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0x00000980 ---32-----------16|15------------0- |
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| | | \ |
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: (real size : : | |
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IDE i/f : and content : : > 0x00000080 |
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[5] : unknown) : : | |
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| | | / |
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0x00000900 ---32-----------16|15------------0- CFG_NIOS_CPU_IDE0 |
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| | \ |
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: gap : > (space for PIO4..7) |
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| | / |
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0x000008c0 ---32-----------16|15------------0- |
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| (unused) | \ |
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+ 0x1c |- - - - - - - - - - - - - - - -| | |
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| (unused) | | |
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+ 0x18 |- - - - - - - - - - - - - - - -| | |
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| (unused) | | |
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+ 0x14 |- - - - - - - - - - - - - - - -| | |
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UART1 | (unused) | > 0x00000020 |
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[2] + 0x10 |- - - - - - - - - - - - - - - -| | |
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| control (10 bit) (rw) | | |
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+ 0x0c |- - - - - - - - - - - - - - - -| | |
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| status (10 bit) (rw) | | |
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+ 0x08 |- - - - - - - - - - - - - - - -| | |
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| txdata (8 bit) (wo) | | |
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+ 0x04 |- - - - - - - - - - - - - - - -| | |
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| rxdata (8 bit) (ro) | / |
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0x000008a0 ---32-----------16|15------------0- CFG_NIOS_CPU_UART1 |
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| | \ |
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: gap : > (space for PIO2..3) |
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| | / |
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0x00000880 ---32-----------16|15------------0- |
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| edgecapture (4 bit) (rw) | \ |
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+ 0x0c |- - - - - - - - - - - - - - - -| | |
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PIO1 | interruptmask (4 bit) (rw) | | |
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[4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010 |
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| (unused) | | |
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+ 0x04 |- - - - - - - - - - - - - - - -| | |
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| data (4 bit) (ro) | / |
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0x00000870 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO1 |
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| (unused) | \ |
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+ 0x0c |- - - - - - - - - - - - - - - -| | |
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PIO0 | (unused) | | |
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[4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010 |
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| (unused) | | |
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+ 0x04 |- - - - - - - - - - - - - - - -| | |
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| data (1 bit) (wo) | / |
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0x00000860 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO0 |
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| (unused) | \ |
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+ 0x1c |- - - - - - - - - - - - - - - -| | |
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| (unused) | | |
||||
+ 0x18 |- - - - - - - - - - - - - - - -| | |
||||
| snaph (16 bit) (rw) | | |
||||
+ 0x14 |- - - - - - - - - - - - - - - -| | |
||||
TIMER0 | snapl (16 bit) (rw) | | |
||||
[3] + 0x10 |- - - - - - - - - - - - - - - -| > 0x00000020 |
||||
| periodh (16 bit) (rw) | | |
||||
+ 0x0c |- - - - - - - - - - - - - - - -| | |
||||
| periodl (16 bit) (rw) | | |
||||
+ 0x08 |- - - - - - - - - - - - - - - -| | |
||||
| control (4 bit) (rw) | | |
||||
+ 0x04 |- - - - - - - - - - - - - - - -| | |
||||
| status (2 bit) (rw) | / |
||||
0x00000840 ---32-----------16|15------------0- CFG_NIOS_CPU_TIMER0 |
||||
| | \ |
||||
: gap : > (space for UART2) |
||||
| | / |
||||
0x00000820 ---32-----------16|15------------0- |
||||
| (unused) | \ |
||||
+ 0x1c |- - - - - - - - - - - - - - - -| | |
||||
| (unused) | | |
||||
+ 0x18 |- - - - - - - - - - - - - - - -| | |
||||
| (unused) | | |
||||
+ 0x14 |- - - - - - - - - - - - - - - -| | |
||||
UART0 | (unused) | > 0x00000020 |
||||
[2] + 0x10 |- - - - - - - - - - - - - - - -| | |
||||
| control (10 bit) (rw) | | |
||||
+ 0x0c |- - - - - - - - - - - - - - - -| | |
||||
| status (10 bit) (rw) | | |
||||
+ 0x08 |- - - - - - - - - - - - - - - -| | |
||||
| txdata (8 bit) (wo) | | |
||||
+ 0x04 |- - - - - - - - - - - - - - - -| | |
||||
| rxdata (8 bit) (ro) | / |
||||
0x00000800 ---32-----------16|15------------0- CFG_NIOS_CPU_UART0 |
||||
|
||||
- - - - - - - - - - - on chip memory 1 - - - - - - - - - - - |
||||
|
||||
0x00000800 ---32-----------16|15------------0- |
||||
| : | \ |
||||
| : | | |
||||
GERMS | : | > CFG_NIOS_CPU_ROM_SIZE |
||||
| : | | = 0x00000800 |
||||
| : | / |
||||
0x00000000 |- - - - - - - - - - - - - - - -+- - CFG_NIOS_CPU_RST_VECT |
||||
0x00000000 ---32-----------16|15------------0- CFG_NIOS_CPU_ROM_BASE |
||||
|
||||
=============================================================================== |
||||
F L A S H M E M O R Y A L L O C A T I O N |
||||
=============================================================================== |
||||
|
||||
0x01000000 ---8-------------4|3-------------0- |
||||
| : | \ |
||||
SAFE | : | > 1 MByte |
||||
FPGA conf. | : | / (NOT usable by software) |
||||
0x00f00000 --+- - - - - - - -:- - - - - - - -+- |
||||
| : | \ |
||||
USER | : | > 1 MByte |
||||
FPGA conf. | : | / (NOT usable by software) |
||||
0x00e00000 --+- - - - - - - -:- - - - - - - -+- |
||||
| : | \ |
||||
| : | | |
||||
WEB pages | : | > 2 MByte |
||||
| : | | (provisory usable) |
||||
| : | / |
||||
0x00c00000 --+- - - - - - - -:- - - - - - - -+- |
||||
| : | \ |
||||
| : | | |
||||
| : | | |
||||
| : | > 4 MByte free for use |
||||
| : | | |
||||
0x00840000 --+- - - - - - - -:- - - - - - - -+-|- u-boot environment |
||||
| : | / |
||||
0x00800000 |- - - - - - - -:- - - - - - - -+- - u-boot _start() |
||||
0x00800000 ---8-------------4|3-------------0- |
||||
|
||||
|
||||
=============================================================================== |
||||
R E F E R E N C E S |
||||
=============================================================================== |
||||
[1] http://www.altera.com/literature/manual/mnl_nios_board_stratix_1s10.pdf |
||||
[2] http://www.altera.com/literature/ds/ds_nios_uart.pdf |
||||
[3] http://www.altera.com/literature/ds/ds_nios_timer.pdf |
||||
[4] http://www.altera.com/literature/ds/ds_nios_pio.pdf |
||||
[5] http://www.opencores.org/projects/ata/ |
||||
http://www.t13.org/index.html |
||||
|
||||
|
||||
=============================================================================== |
||||
Stephan Linz <linz@li-pro.net> |
@ -0,0 +1,34 @@ |
||||
/*
|
||||
* (C) Copyright 2003, Li-Pro.Net <www.li-pro.net> |
||||
* Stephan Linz <linz@li-pro.net> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_DK1C20_SAFE_32_H |
||||
#define __CONFIG_DK1C20_SAFE_32_H |
||||
|
||||
/*
|
||||
* NIOS CPU configuration. (PART OF configs/DK1C20.h) |
||||
* |
||||
* !!! TODO !!! TODO !!! |
||||
*/ |
||||
#error *** CFG_ERROR: DK1C20_safe_32 have to be defined (use DK1C20_standard_32 as template) |
||||
|
||||
#endif /* __CONFIG_DK1C20_SAFE_32_H */ |
@ -0,0 +1,279 @@ |
||||
/*
|
||||
* (C) Copyright 2003, Li-Pro.Net <www.li-pro.net> |
||||
* Stephan Linz <linz@li-pro.net> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_DK1C20_STANDARD_32_H |
||||
#define __CONFIG_DK1C20_STANDARD_32_H |
||||
|
||||
/*
|
||||
* NIOS CPU configuration. (PART OF configs/DK1C20.h) |
||||
* |
||||
* Here we must define CPU dependencies. Any unsupported option have to |
||||
* be defined with zero, example CPU without data cache / OCI: |
||||
* |
||||
* #define CFG_NIOS_CPU_ICACHE 4096 |
||||
* #define CFG_NIOS_CPU_DCACHE 0 |
||||
* #define CFG_NIOS_CPU_OCI_BASE 0 |
||||
* #define CFG_NIOS_CPU_OCI_SIZE 0 |
||||
*/ |
||||
|
||||
/* CPU core */ |
||||
#define CFG_NIOS_CPU_CLK 50000000 /* NIOS CPU clock */ |
||||
#define CFG_NIOS_CPU_ICACHE (4 * 1024) /* instruction cache */ |
||||
#define CFG_NIOS_CPU_DCACHE (4 * 1024) /* data cache */ |
||||
#define CFG_NIOS_CPU_REG_NUMS 256 /* number of register */ |
||||
#define CFG_NIOS_CPU_MUL 0 /* 16x16 MUL: no(0) */ |
||||
/* yes(1) */ |
||||
#define CFG_NIOS_CPU_MSTEP 1 /* 16x16 MSTEP: no(0) */ |
||||
/* yes(1) */ |
||||
#define CFG_NIOS_CPU_STACK 0x008fff00 /* stack top addr */ |
||||
#define CFG_NIOS_CPU_VEC_BASE 0x008fff00 /* IRQ vectors addr */ |
||||
#define CFG_NIOS_CPU_VEC_SIZE 256 /* size */ |
||||
#define CFG_NIOS_CPU_VEC_NUMS 64 /* numbers */ |
||||
#define CFG_NIOS_CPU_RST_VECT 0x00920000 /* RESET vector addr */ |
||||
#define CFG_NIOS_CPU_DBG_CORE 0 /* CPU debug: no(0) */ |
||||
/* yes(1) */ |
||||
|
||||
/* on-chip extensions */ |
||||
#define CFG_NIOS_CPU_RAM_BASE 0 /* on chip RAM addr */ |
||||
#define CFG_NIOS_CPU_RAM_SIZE 0 /* size */ |
||||
|
||||
#define CFG_NIOS_CPU_ROM_BASE 0x00920000 /* on chip ROM addr */ |
||||
#define CFG_NIOS_CPU_ROM_SIZE (2 * 1024) /* 2 KB size */ |
||||
|
||||
#define CFG_NIOS_CPU_OCI_BASE 0x00920800 /* OCI core addr */ |
||||
#define CFG_NIOS_CPU_OCI_SIZE 256 /* size */ |
||||
|
||||
/* timer */ |
||||
#define CFG_NIOS_CPU_TIMER_NUMS 2 /* number of timer */ |
||||
|
||||
#define CFG_NIOS_CPU_TIMER0 0x00920940 /* TIMER0 addr */ |
||||
#define CFG_NIOS_CPU_TIMER0_IRQ 16 /* IRQ */ |
||||
#define CFG_NIOS_CPU_TIMER0_PER 1000 /* periode usec */ |
||||
#define CFG_NIOS_CPU_TIMER0_AR 0 /* always run: no(0) */ |
||||
/* yes(1) */ |
||||
#define CFG_NIOS_CPU_TIMER0_FP 0 /* fixed per: no(0) */ |
||||
/* yes(1) */ |
||||
#define CFG_NIOS_CPU_TIMER0_SS 1 /* snaphot: no(0) */ |
||||
/* yes(1) */ |
||||
|
||||
#define CFG_NIOS_CPU_TIMER1 0x009209e0 /* TIMER1 addr */ |
||||
#define CFG_NIOS_CPU_TIMER1_IRQ 50 /* IRQ */ |
||||
#define CFG_NIOS_CPU_TIMER1_PER 10000 /* periode usec */ |
||||
#define CFG_NIOS_CPU_TIMER1_AR 1 /* always run: no(0) */ |
||||
/* yes(1) */ |
||||
#define CFG_NIOS_CPU_TIMER1_FP 1 /* fixed per: no(0) */ |
||||
/* yes(1) */ |
||||
#define CFG_NIOS_CPU_TIMER1_SS 0 /* snaphot: no(0) */ |
||||
/* yes(1) */ |
||||
|
||||
/* serial i/o */ |
||||
#define CFG_NIOS_CPU_UART_NUMS 1 /* number of uarts */ |
||||
|
||||
#define CFG_NIOS_CPU_UART0 0x00920900 /* UART0 addr */ |
||||
#define CFG_NIOS_CPU_UART0_IRQ 25 /* IRQ */ |
||||
#define CFG_NIOS_CPU_UART0_BR 115200 /* baudrate var(0) */ |
||||
#define CFG_NIOS_CPU_UART0_DB 8 /* data bit */ |
||||
#define CFG_NIOS_CPU_UART0_SB 1 /* stop bit */ |
||||
#define CFG_NIOS_CPU_UART0_PA 0 /* parity none(0) */ |
||||
/* odd(1) */ |
||||
/* even(2) */ |
||||
#define CFG_NIOS_CPU_UART0_HS 0 /* handshake: no(0) */ |
||||
/* crts(1) */ |
||||
#define CFG_NIOS_CPU_UART0_EOP 0 /* eop reg: no(0) */ |
||||
/* yes(1) */ |
||||
|
||||
/* parallel i/o */ |
||||
#define CFG_NIOS_CPU_PIO_NUMS 8 /* number of parports */ |
||||
|
||||
#define CFG_NIOS_CPU_PIO0 0x00920960 /* PIO0 addr */ |
||||
#define CFG_NIOS_CPU_PIO0_IRQ 40 /* IRQ */ |
||||
#define CFG_NIOS_CPU_PIO0_BITS 4 /* number of bits */ |
||||
#define CFG_NIOS_CPU_PIO0_TYPE 2 /* io type: tris(0) */ |
||||
/* out(1) */ |
||||
/* in(2) */ |
||||
#define CFG_NIOS_CPU_PIO0_CAP 1 /* capture: no(0) */ |
||||
/* yes(1) */ |
||||
#define CFG_NIOS_CPU_PIO0_EDGE 3 /* edge type: none(0) */ |
||||
/* fall(1) */ |
||||
/* rise(2) */ |
||||
/* any(3) */ |
||||
#define CFG_NIOS_CPU_PIO0_ITYPE 2 /* IRQ type: none(0) */ |
||||
/* level(1)*/ |
||||
/* edge(2) */ |
||||
|
||||
#define CFG_NIOS_CPU_PIO1 0x00920970 /* PIO1 addr */ |
||||
#undef CFG_NIOS_CPU_PIO1_IRQ /* w/o IRQ */ |
||||
#define CFG_NIOS_CPU_PIO1_BITS 11 /* number of bits */ |
||||
#define CFG_NIOS_CPU_PIO1_TYPE 0 /* io type: tris(0) */ |
||||
/* out(1) */ |
||||
/* in(2) */ |
||||
#define CFG_NIOS_CPU_PIO1_CAP 0 /* capture: no(0) */ |
||||
/* yes(1) */ |
||||
#define CFG_NIOS_CPU_PIO1_EDGE 0 /* edge type: none(0) */ |
||||
/* fall(1) */ |
||||
/* rise(2) */ |
||||
/* any(3) */ |
||||
#define CFG_NIOS_CPU_PIO1_ITYPE 0 /* IRQ type: none(0) */ |
||||
/* level(1)*/ |
||||
/* edge(2) */ |
||||
|
||||
#define CFG_NIOS_CPU_PIO2 0x00920980 /* PIO2 addr */ |
||||
#undef CFG_NIOS_CPU_PIO2_IRQ /* w/o IRQ */ |
||||
#define CFG_NIOS_CPU_PIO2_BITS 8 /* number of bits */ |
||||
#define CFG_NIOS_CPU_PIO2_TYPE 1 /* io type: tris(0) */ |
||||
/* out(1) */ |
||||
/* in(2) */ |
||||
#define CFG_NIOS_CPU_PIO2_CAP 0 /* capture: no(0) */ |
||||
/* yes(1) */ |
||||
#define CFG_NIOS_CPU_PIO2_EDGE 0 /* edge type: none(0) */ |
||||
/* fall(1) */ |
||||
/* rise(2) */ |
||||
/* any(3) */ |
||||
#define CFG_NIOS_CPU_PIO2_ITYPE 0 /* IRQ type: none(0) */ |
||||
/* level(1)*/ |
||||
/* edge(2) */ |
||||
|
||||
#define CFG_NIOS_CPU_PIO3 0x00920990 /* PIO3 addr */ |
||||
#undef CFG_NIOS_CPU_PIO3_IRQ /* w/o IRQ */ |
||||
#define CFG_NIOS_CPU_PIO3_BITS 16 /* number of bits */ |
||||
#define CFG_NIOS_CPU_PIO3_TYPE 1 /* io type: tris(0) */ |
||||
/* out(1) */ |
||||
/* in(2) */ |
||||
#define CFG_NIOS_CPU_PIO3_CAP 0 /* capture: no(0) */ |
||||
/* yes(1) */ |
||||
#define CFG_NIOS_CPU_PIO3_EDGE 0 /* edge type: none(0) */ |
||||
/* fall(1) */ |
||||
/* rise(2) */ |
||||
/* any(3) */ |
||||
#define CFG_NIOS_CPU_PIO3_ITYPE 0 /* IRQ type: none(0) */ |
||||
/* level(1)*/ |
||||
/* edge(2) */ |
||||
|
||||
#define CFG_NIOS_CPU_PIO4 0x009209a0 /* PIO4 addr */ |
||||
#undef CFG_NIOS_CPU_PIO4_IRQ /* w/o IRQ */ |
||||
#define CFG_NIOS_CPU_PIO4_BITS 1 /* number of bits */ |
||||
#define CFG_NIOS_CPU_PIO4_TYPE 0 /* io type: tris(0) */ |
||||
/* out(1) */ |
||||
/* in(2) */ |
||||
#define CFG_NIOS_CPU_PIO4_CAP 0 /* capture: no(0) */ |
||||
/* yes(1) */ |
||||
#define CFG_NIOS_CPU_PIO4_EDGE 0 /* edge type: none(0) */ |
||||
/* fall(1) */ |
||||
/* rise(2) */ |
||||
/* any(3) */ |
||||
#define CFG_NIOS_CPU_PIO4_ITYPE 0 /* IRQ type: none(0) */ |
||||
/* level(1)*/ |
||||
/* edge(2) */ |
||||
|
||||
#define CFG_NIOS_CPU_PIO5 0x009209b0 /* PIO5 addr */ |
||||
#define CFG_NIOS_CPU_PIO5_IRQ 35 /* IRQ */ |
||||
#define CFG_NIOS_CPU_PIO5_BITS 1 /* number of bits */ |
||||
#define CFG_NIOS_CPU_PIO5_TYPE 2 /* io type: tris(0) */ |
||||
/* out(1) */ |
||||
/* in(2) */ |
||||
#define CFG_NIOS_CPU_PIO5_CAP 1 /* capture: no(0) */ |
||||
/* yes(1) */ |
||||
#define CFG_NIOS_CPU_PIO5_EDGE 3 /* edge type: none(0) */ |
||||
/* fall(1) */ |
||||
/* rise(2) */ |
||||
/* any(3) */ |
||||
#define CFG_NIOS_CPU_PIO5_ITYPE 2 /* IRQ type: none(0) */ |
||||
/* level(1)*/ |
||||
/* edge(2) */ |
||||
|
||||
#define CFG_NIOS_CPU_PIO6 0x009209c0 /* PIO6 addr */ |
||||
#undef CFG_NIOS_CPU_PIO6_IRQ /* w/o IRQ */ |
||||
#define CFG_NIOS_CPU_PIO6_BITS 1 /* number of bits */ |
||||
#define CFG_NIOS_CPU_PIO6_TYPE 1 /* io type: tris(0) */ |
||||
/* out(1) */ |
||||
/* in(2) */ |
||||
#define CFG_NIOS_CPU_PIO6_CAP 0 /* capture: no(0) */ |
||||
/* yes(1) */ |
||||
#define CFG_NIOS_CPU_PIO6_EDGE 0 /* edge type: none(0) */ |
||||
/* fall(1) */ |
||||
/* rise(2) */ |
||||
/* any(3) */ |
||||
#define CFG_NIOS_CPU_PIO6_ITYPE 0 /* IRQ type: none(0) */ |
||||
/* level(1)*/ |
||||
/* edge(2) */ |
||||
|
||||
#define CFG_NIOS_CPU_PIO7 0x009209d0 /* PIO7 addr */ |
||||
#undef CFG_NIOS_CPU_PIO7_IRQ /* w/o IRQ */ |
||||
#define CFG_NIOS_CPU_PIO7_BITS 1 /* number of bits */ |
||||
#define CFG_NIOS_CPU_PIO7_TYPE 1 /* io type: tris(0) */ |
||||
/* out(1) */ |
||||
/* in(2) */ |
||||
#define CFG_NIOS_CPU_PIO7_CAP 0 /* capture: no(0) */ |
||||
/* yes(1) */ |
||||
#define CFG_NIOS_CPU_PIO7_EDGE 0 /* edge type: none(0) */ |
||||
/* fall(1) */ |
||||
/* rise(2) */ |
||||
/* any(3) */ |
||||
#define CFG_NIOS_CPU_PIO7_ITYPE 0 /* IRQ type: none(0) */ |
||||
/* level(1)*/ |
||||
/* edge(2) */ |
||||
|
||||
/* IDE i/f */ |
||||
#define CFG_NIOS_CPU_IDE_NUMS 1 /* number of IDE contr. */ |
||||
#define CFG_NIOS_CPU_IDE0 0x00920a00 /* IDE0 addr */ |
||||
|
||||
/* active serial memory i/f */ |
||||
#define CFG_NIOS_CPU_ASMI_NUMS 1 /* number of ASMI */ |
||||
#define CFG_NIOS_CPU_ASMI0 0x00920b00 /* ASMI0 addr */ |
||||
#define CFG_NIOS_CPU_ASMI0_IRQ 45 /* IRQ */ |
||||
|
||||
/* memory accessibility */ |
||||
#define CFG_NIOS_CPU_SRAM_BASE 0x00800000 /* board SRAM addr */ |
||||
#define CFG_NIOS_CPU_SRAM_SIZE (1024 * 1024) /* 1 MB size */ |
||||
|
||||
#define CFG_NIOS_CPU_SDRAM_BASE 0x01000000 /* board SDRAM addr */ |
||||
#define CFG_NIOS_CPU_SDRAM_SIZE (16*1024*1024) /* 16 MB size */ |
||||
|
||||
#define CFG_NIOS_CPU_FLASH_BASE 0x00000000 /* board Flash addr */ |
||||
#define CFG_NIOS_CPU_FLASH_SIZE (8*1024*1024) /* 8 MB size */ |
||||
|
||||
/* LAN */ |
||||
#define CFG_NIOS_CPU_LAN_NUMS 1 /* number of LAN i/f */ |
||||
|
||||
#define CFG_NIOS_CPU_LAN0_BASE 0x00910000 /* LAN0 addr */ |
||||
#define CFG_NIOS_CPU_LAN0_OFFS 0x0300 /* offset */ |
||||
#define CFG_NIOS_CPU_LAN0_IRQ 30 /* IRQ */ |
||||
#define CFG_NIOS_CPU_LAN0_BUSW 32 /* buswidth*/ |
||||
#define CFG_NIOS_CPU_LAN0_TYPE 0 /* smc91111(0) */ |
||||
/* cs8900(1) */ |
||||
/* ex: alteramac(2) */ |
||||
|
||||
/* symbolic redefinition (undef, if not present) */ |
||||
#define CFG_NIOS_CPU_USER_TIMER 0 /* TIMER0: users choice */ |
||||
#define CFG_NIOS_CPU_TICK_TIMER 1 /* TIMER1: tick (needed)*/ |
||||
|
||||
#define CFG_NIOS_CPU_BUTTON_PIO 0 /* PIO0: buttons */ |
||||
#define CFG_NIOS_CPU_LCD_PIO 1 /* PIO1: ASCII LCD */ |
||||
#define CFG_NIOS_CPU_LED_PIO 2 /* PIO2: LED bar */ |
||||
#define CFG_NIOS_CPU_SEVENSEG_PIO 3 /* PIO3: 7-seg. display */ |
||||
#define CFG_NIOS_CPU_RECONF_PIO 4 /* PIO4: reconf pin */ |
||||
#define CFG_NIOS_CPU_CFPRESENT_PIO 5 /* PIO5: CF present IRQ */ |
||||
#define CFG_NIOS_CPU_CFPOWER_PIO 6 /* PIO6: CF power/sw. */ |
||||
#define CFG_NIOS_CPU_CFATASEL_PIO 7 /* PIO7: CF ATA select */ |
||||
|
||||
#endif /* __CONFIG_DK1C20_STANDARD_32_H */ |
@ -0,0 +1,187 @@ |
||||
/*
|
||||
* (C) Copyright 2003, Li-Pro.Net <www.li-pro.net> |
||||
* Stephan Linz <linz@li-pro.net> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_DK1S10_MTX_LDK_20_H |
||||
#define __CONFIG_DK1S10_MTX_LDK_20_H |
||||
|
||||
/*
|
||||
* NIOS CPU configuration. (PART OF configs/DK1S10.h) |
||||
* |
||||
* Here we must define CPU dependencies. Any unsupported option have to |
||||
* be defined with zero, example CPU without data cache / OCI: |
||||
* |
||||
* #define CFG_NIOS_CPU_ICACHE 4096 |
||||
* #define CFG_NIOS_CPU_DCACHE 0 |
||||
* #define CFG_NIOS_CPU_OCI_BASE 0 |
||||
* #define CFG_NIOS_CPU_OCI_SIZE 0 |
||||
*/ |
||||
|
||||
/* CPU core */ |
||||
#define CFG_NIOS_CPU_CLK 75000000 /* NIOS CPU clock */ |
||||
#define CFG_NIOS_CPU_ICACHE (0) /* instruction cache */ |
||||
#define CFG_NIOS_CPU_DCACHE (0) /* data cache */ |
||||
#define CFG_NIOS_CPU_REG_NUMS 512 /* number of register */ |
||||
#define CFG_NIOS_CPU_MUL 0 /* 16x16 MUL: no(0) */ |
||||
/* yes(1) */ |
||||
#define CFG_NIOS_CPU_MSTEP 1 /* 16x16 MSTEP: no(0) */ |
||||
/* yes(1) */ |
||||
#define CFG_NIOS_CPU_STACK 0x02000000 /* stack top addr */ |
||||
#define CFG_NIOS_CPU_VEC_BASE 0x01000000 /* IRQ vectors addr */ |
||||
#define CFG_NIOS_CPU_VEC_SIZE 256 /* size */ |
||||
#define CFG_NIOS_CPU_VEC_NUMS 64 /* numbers */ |
||||
#define CFG_NIOS_CPU_RST_VECT 0x00000000 /* RESET vector addr */ |
||||
#define CFG_NIOS_CPU_DBG_CORE 0 /* CPU debug: no(0) */ |
||||
/* yes(1) */ |
||||
|
||||
/* The offset address in flash to check for the Nios signature "Ni".
|
||||
* (see GM_FlashExec in germs_monitor.s) */ |
||||
#define CFG_NIOS_CPU_EXES_OFFS 0x0C |
||||
|
||||
/* on-chip extensions */ |
||||
#undef CFG_NIOS_CPU_RAM_BASE /* on chip RAM addr */ |
||||
#undef CFG_NIOS_CPU_RAM_SIZE /* 64 KB size */ |
||||
|
||||
#define CFG_NIOS_CPU_ROM_BASE 0x00000000 /* on chip ROM addr */ |
||||
#define CFG_NIOS_CPU_ROM_SIZE (2 * 1024) /* 2 KB size */ |
||||
|
||||
#undef CFG_NIOS_CPU_OCI_BASE /* OCI core addr */ |
||||
#undef CFG_NIOS_CPU_OCI_SIZE /* size */ |
||||
|
||||
/* timer */ |
||||
#define CFG_NIOS_CPU_TIMER_NUMS 1 /* number of timer */ |
||||
|
||||
#define CFG_NIOS_CPU_TIMER0 0x00000840 /* TIMER0 addr */ |
||||
#define CFG_NIOS_CPU_TIMER0_IRQ 16 /* IRQ */ |
||||
#define CFG_NIOS_CPU_TIMER0_PER 1000 /* periode usec */ |
||||
#define CFG_NIOS_CPU_TIMER0_AR 0 /* always run: no(0) */ |
||||
/* yes(1) */ |
||||
#define CFG_NIOS_CPU_TIMER0_FP 0 /* fixed per: no(0) */ |
||||
/* yes(1) */ |
||||
#define CFG_NIOS_CPU_TIMER0_SS 1 /* snaphot: no(0) */ |
||||
/* yes(1) */ |
||||
|
||||
/* serial i/o */ |
||||
#define CFG_NIOS_CPU_UART_NUMS 2 /* number of uarts */ |
||||
|
||||
#define CFG_NIOS_CPU_UART0 0x00000800 /* UART0 addr */ |
||||
#define CFG_NIOS_CPU_UART0_IRQ 17 /* IRQ */ |
||||
#define CFG_NIOS_CPU_UART0_BR 115200 /* baudrate var(0) */ |
||||
#define CFG_NIOS_CPU_UART0_DB 8 /* data bit */ |
||||
#define CFG_NIOS_CPU_UART0_SB 2 /* stop bit */ |
||||
#define CFG_NIOS_CPU_UART0_PA 0 /* parity none(0) */ |
||||
/* odd(1) */ |
||||
/* even(2) */ |
||||
#define CFG_NIOS_CPU_UART0_HS 0 /* handshake: no(0) */ |
||||
/* crts(1) */ |
||||
#define CFG_NIOS_CPU_UART0_EOP 0 /* eop reg: no(0) */ |
||||
/* yes(1) */ |
||||
|
||||
#define CFG_NIOS_CPU_UART1 0x000008a0 /* UART1 addr */ |
||||
#define CFG_NIOS_CPU_UART1_IRQ 18 /* IRQ */ |
||||
#define CFG_NIOS_CPU_UART1_BR 115200 /* baudrate var(0) */ |
||||
#define CFG_NIOS_CPU_UART1_DB 8 /* data bit */ |
||||
#define CFG_NIOS_CPU_UART1_SB 1 /* stop bit */ |
||||
#define CFG_NIOS_CPU_UART1_PA 0 /* parity none(0) */ |
||||
/* odd(1) */ |
||||
/* even(2) */ |
||||
#define CFG_NIOS_CPU_UART1_HS 0 /* handshake: no(0) */ |
||||
/* crts(1) */ |
||||
#define CFG_NIOS_CPU_UART1_EOP 0 /* eop reg: no(0) */ |
||||
/* yes(1) */ |
||||
|
||||
/* parallel i/o */ |
||||
#define CFG_NIOS_CPU_PIO_NUMS 2 /* number of parports */ |
||||
|
||||
#define CFG_NIOS_CPU_PIO0 0x00000860 /* PIO0 addr */ |
||||
#undef CFG_NIOS_CPU_PIO0_IRQ /* w/o IRQ */ |
||||
#define CFG_NIOS_CPU_PIO0_BITS 1 /* number of bits */ |
||||
#define CFG_NIOS_CPU_PIO0_TYPE 1 /* io type: tris(0) */ |
||||
/* out(1) */ |
||||
/* in(2) */ |
||||
#define CFG_NIOS_CPU_PIO0_CAP 0 /* capture: no(0) */ |
||||
/* yes(1) */ |
||||
#define CFG_NIOS_CPU_PIO0_EDGE 0 /* edge type: none(0) */ |
||||
/* fall(1) */ |
||||
/* rise(2) */ |
||||
/* any(3) */ |
||||
#define CFG_NIOS_CPU_PIO0_ITYPE 0 /* IRQ type: none(0) */ |
||||
/* level(1)*/ |
||||
/* edge(2) */ |
||||
|
||||
#define CFG_NIOS_CPU_PIO1 0x00000870 /* PIO1 addr */ |
||||
#undef CFG_NIOS_CPU_PIO1_IRQ /* w/o IRQ */ |
||||
#define CFG_NIOS_CPU_PIO1_BITS 4 /* number of bits */ |
||||
#define CFG_NIOS_CPU_PIO1_TYPE 2 /* io type: tris(0) */ |
||||
/* out(1) */ |
||||
/* in(2) */ |
||||
#define CFG_NIOS_CPU_PIO1_CAP 0 /* capture: no(0) */ |
||||
/* yes(1) */ |
||||
#define CFG_NIOS_CPU_PIO1_EDGE 0 /* edge type: none(0) */ |
||||
/* fall(1) */ |
||||
/* rise(2) */ |
||||
/* any(3) */ |
||||
#define CFG_NIOS_CPU_PIO1_ITYPE 0 /* IRQ type: none(0) */ |
||||
/* level(1)*/ |
||||
/* edge(2) */ |
||||
|
||||
/* IDE i/f */ |
||||
#define CFG_NIOS_CPU_IDE_NUMS 1 /* number of IDE contr. */ |
||||
#define CFG_NIOS_CPU_IDE0 0x00000900 /* IDE0 addr */ |
||||
#define CFG_NIOS_CPU_IDE0_IRQ 25 /* IRQ */ |
||||
|
||||
/* memory accessibility */ |
||||
#undef CFG_NIOS_CPU_SRAM_BASE /* board SRAM addr */ |
||||
#undef CFG_NIOS_CPU_SRAM_SIZE /* 1 MB size */ |
||||
|
||||
#define CFG_NIOS_CPU_SDRAM_BASE 0x01000000 /* board SDRAM addr */ |
||||
#define CFG_NIOS_CPU_SDRAM_SIZE (16*1024*1024) /* 16 MB size */ |
||||
|
||||
#define CFG_NIOS_CPU_FLASH_BASE 0x00800000 /* board Flash addr */ |
||||
#define CFG_NIOS_CPU_FLASH_SIZE (8*1024*1024) /* 8 MB size */ |
||||
|
||||
/* LAN */ |
||||
#define CFG_NIOS_CPU_LAN_NUMS 1 /* number of LAN i/f */ |
||||
|
||||
#define CFG_NIOS_CPU_LAN0_BASE 0x00010000 /* LAN0 addr */ |
||||
#define CFG_NIOS_CPU_LAN0_OFFS 0x0300 /* offset */ |
||||
#define CFG_NIOS_CPU_LAN0_IRQ 20 /* IRQ */ |
||||
#define CFG_NIOS_CPU_LAN0_BUSW 32 /* buswidth*/ |
||||
#define CFG_NIOS_CPU_LAN0_TYPE 0 /* smc91111(0) */ |
||||
/* cs8900(1) */ |
||||
/* ex: openmac(2) */ |
||||
/* ex: alteramac(3) */ |
||||
|
||||
/* symbolic redefinition (undef, if not present) */ |
||||
#define CFG_NIOS_CPU_TICK_TIMER 0 /* TIMER0: tick (needed)*/ |
||||
#undef CFG_NIOS_CPU_USER_TIMER /* TIMERx: users choice */ |
||||
|
||||
#define CFG_NIOS_CPU_CFPOWER_PIO 0 /* PIO0: CF power/sw. */ |
||||
#define CFG_NIOS_CPU_BUTTON_PIO 1 /* PIO1: buttons */ |
||||
#undef CFG_NIOS_CPU_LCD_PIO /* PIOx: ASCII LCD */ |
||||
#undef CFG_NIOS_CPU_LED_PIO /* PIOx: LED bar */ |
||||
#undef CFG_NIOS_CPU_SEVENSEG_PIO /* PIOx: 7-seg. display */ |
||||
#undef CFG_NIOS_CPU_RECONF_PIO /* PIOx: reconf pin */ |
||||
#undef CFG_NIOS_CPU_CFPRESENT_PIO /* PIOx: CF present IRQ */ |
||||
#undef CFG_NIOS_CPU_CFATASEL_PIO /* PIOx: CF ATA select */ |
||||
|
||||
#endif /* __CONFIG_DK1S10_MTX_LDK_20_H */ |
@ -0,0 +1,34 @@ |
||||
/*
|
||||
* (C) Copyright 2003, Li-Pro.Net <www.li-pro.net> |
||||
* Stephan Linz <linz@li-pro.net> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_DK1S10_SAFE_32_H |
||||
#define __CONFIG_DK1S10_SAFE_32_H |
||||
|
||||
/*
|
||||
* NIOS CPU configuration. (PART OF configs/DK1S10.h) |
||||
* |
||||
* !!! TODO !!! TODO !!! |
||||
*/ |
||||
#error *** CFG_ERROR: DK1S10_safe_32 have to be defined (use DK1S10_standard_32 as template) |
||||
|
||||
#endif /* __CONFIG_DK1S10_SAFE_32_H */ |
@ -0,0 +1,274 @@ |
||||
/*
|
||||
* (C) Copyright 2003, Li-Pro.Net <www.li-pro.net> |
||||
* Stephan Linz <linz@li-pro.net> |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_DK1S10_STANDARD_32_H |
||||
#define __CONFIG_DK1S10_STANDARD_32_H |
||||
|
||||
/*
|
||||
* NIOS CPU configuration. (PART OF configs/DK1S10.h) |
||||
* |
||||
* Here we must define CPU dependencies. Any unsupported option have to |
||||
* be defined with zero, example CPU without data cache / OCI: |
||||
* |
||||
* #define CFG_NIOS_CPU_ICACHE 4096 |
||||
* #define CFG_NIOS_CPU_DCACHE 0 |
||||
* #define CFG_NIOS_CPU_OCI_BASE 0 |
||||
* #define CFG_NIOS_CPU_OCI_SIZE 0 |
||||
*/ |
||||
|
||||
/* CPU core */ |
||||
#define CFG_NIOS_CPU_CLK 50000000 /* NIOS CPU clock */ |
||||
#define CFG_NIOS_CPU_ICACHE (4 * 1024) /* instruction cache */ |
||||
#define CFG_NIOS_CPU_DCACHE (4 * 1024) /* data cache */ |
||||
#define CFG_NIOS_CPU_REG_NUMS 256 /* number of register */ |
||||
#define CFG_NIOS_CPU_MUL 0 /* 16x16 MUL: no(0) */ |
||||
/* yes(1) */ |
||||
#define CFG_NIOS_CPU_MSTEP 1 /* 16x16 MSTEP: no(0) */ |
||||
/* yes(1) */ |
||||
#define CFG_NIOS_CPU_STACK 0x008fff00 /* stack top addr */ |
||||
#define CFG_NIOS_CPU_VEC_BASE 0x008fff00 /* IRQ vectors addr */ |
||||
#define CFG_NIOS_CPU_VEC_SIZE 256 /* size */ |
||||
#define CFG_NIOS_CPU_VEC_NUMS 64 /* numbers */ |
||||
#define CFG_NIOS_CPU_RST_VECT 0x00920000 /* RESET vector addr */ |
||||
#define CFG_NIOS_CPU_DBG_CORE 0 /* CPU debug: no(0) */ |
||||
/* yes(1) */ |
||||
|
||||
/* on-chip extensions */ |
||||
#define CFG_NIOS_CPU_RAM_BASE 0x00900000 /* on chip RAM addr */ |
||||
#define CFG_NIOS_CPU_RAM_SIZE (64 * 1024) /* 64 KB size */ |
||||
|
||||
#define CFG_NIOS_CPU_ROM_BASE 0x00920000 /* on chip ROM addr */ |
||||
#define CFG_NIOS_CPU_ROM_SIZE (2 * 1024) /* 2 KB size */ |
||||
|
||||
#define CFG_NIOS_CPU_OCI_BASE 0x00920800 /* OCI core addr */ |
||||
#define CFG_NIOS_CPU_OCI_SIZE 256 /* size */ |
||||
|
||||
/* timer */ |
||||
#define CFG_NIOS_CPU_TIMER_NUMS 2 /* number of timer */ |
||||
|
||||
#define CFG_NIOS_CPU_TIMER0 0x00920940 /* TIMER0 addr */ |
||||
#define CFG_NIOS_CPU_TIMER0_IRQ 16 /* IRQ */ |
||||
#define CFG_NIOS_CPU_TIMER0_PER 1000 /* periode usec */ |
||||
#define CFG_NIOS_CPU_TIMER0_AR 0 /* always run: no(0) */ |
||||
/* yes(1) */ |
||||
#define CFG_NIOS_CPU_TIMER0_FP 0 /* fixed per: no(0) */ |
||||
/* yes(1) */ |
||||
#define CFG_NIOS_CPU_TIMER0_SS 1 /* snaphot: no(0) */ |
||||
/* yes(1) */ |
||||
|
||||
#define CFG_NIOS_CPU_TIMER1 0x009209e0 /* TIMER1 addr */ |
||||
#define CFG_NIOS_CPU_TIMER1_IRQ 50 /* IRQ */ |
||||
#define CFG_NIOS_CPU_TIMER1_PER 10000 /* periode usec */ |
||||
#define CFG_NIOS_CPU_TIMER1_AR 1 /* always run: no(0) */ |
||||
/* yes(1) */ |
||||
#define CFG_NIOS_CPU_TIMER1_FP 1 /* fixed per: no(0) */ |
||||
/* yes(1) */ |
||||
#define CFG_NIOS_CPU_TIMER1_SS 0 /* snaphot: no(0) */ |
||||
/* yes(1) */ |
||||
|
||||
/* serial i/o */ |
||||
#define CFG_NIOS_CPU_UART_NUMS 1 /* number of uarts */ |
||||
|
||||
#define CFG_NIOS_CPU_UART0 0x00920900 /* UART0 addr */ |
||||
#define CFG_NIOS_CPU_UART0_IRQ 25 /* IRQ */ |
||||
#define CFG_NIOS_CPU_UART0_BR 115200 /* baudrate var(0) */ |
||||
#define CFG_NIOS_CPU_UART0_DB 8 /* data bit */ |
||||
#define CFG_NIOS_CPU_UART0_SB 1 /* stop bit */ |
||||
#define CFG_NIOS_CPU_UART0_PA 0 /* parity none(0) */ |
||||
/* odd(1) */ |
||||
/* even(2) */ |
||||
#define CFG_NIOS_CPU_UART0_HS 0 /* handshake: no(0) */ |
||||
/* crts(1) */ |
||||
#define CFG_NIOS_CPU_UART0_EOP 0 /* eop reg: no(0) */ |
||||
/* yes(1) */ |
||||
|
||||
/* parallel i/o */ |
||||
#define CFG_NIOS_CPU_PIO_NUMS 8 /* number of parports */ |
||||
|
||||
#define CFG_NIOS_CPU_PIO0 0x00920960 /* PIO0 addr */ |
||||
#define CFG_NIOS_CPU_PIO0_IRQ 40 /* IRQ */ |
||||
#define CFG_NIOS_CPU_PIO0_BITS 4 /* number of bits */ |
||||
#define CFG_NIOS_CPU_PIO0_TYPE 2 /* io type: tris(0) */ |
||||
/* out(1) */ |
||||
/* in(2) */ |
||||
#define CFG_NIOS_CPU_PIO0_CAP 1 /* capture: no(0) */ |
||||
/* yes(1) */ |
||||
#define CFG_NIOS_CPU_PIO0_EDGE 3 /* edge type: none(0) */ |
||||
/* fall(1) */ |
||||
/* rise(2) */ |
||||
/* any(3) */ |
||||
#define CFG_NIOS_CPU_PIO0_ITYPE 2 /* IRQ type: none(0) */ |
||||
/* level(1)*/ |
||||
/* edge(2) */ |
||||
|
||||
#define CFG_NIOS_CPU_PIO1 0x00920970 /* PIO1 addr */ |
||||
#undef CFG_NIOS_CPU_PIO1_IRQ /* w/o IRQ */ |
||||
#define CFG_NIOS_CPU_PIO1_BITS 11 /* number of bits */ |
||||
#define CFG_NIOS_CPU_PIO1_TYPE 0 /* io type: tris(0) */ |
||||
/* out(1) */ |
||||
/* in(2) */ |
||||
#define CFG_NIOS_CPU_PIO1_CAP 0 /* capture: no(0) */ |
||||
/* yes(1) */ |
||||
#define CFG_NIOS_CPU_PIO1_EDGE 0 /* edge type: none(0) */ |
||||
/* fall(1) */ |
||||
/* rise(2) */ |
||||
/* any(3) */ |
||||
#define CFG_NIOS_CPU_PIO1_ITYPE 0 /* IRQ type: none(0) */ |
||||
/* level(1)*/ |
||||
/* edge(2) */ |
||||
|
||||
#define CFG_NIOS_CPU_PIO2 0x00920980 /* PIO2 addr */ |
||||
#undef CFG_NIOS_CPU_PIO2_IRQ /* w/o IRQ */ |
||||
#define CFG_NIOS_CPU_PIO2_BITS 8 /* number of bits */ |
||||
#define CFG_NIOS_CPU_PIO2_TYPE 1 /* io type: tris(0) */ |
||||
/* out(1) */ |
||||
/* in(2) */ |
||||
#define CFG_NIOS_CPU_PIO2_CAP 0 /* capture: no(0) */ |
||||
/* yes(1) */ |
||||
#define CFG_NIOS_CPU_PIO2_EDGE 0 /* edge type: none(0) */ |
||||
/* fall(1) */ |
||||
/* rise(2) */ |
||||
/* any(3) */ |
||||
#define CFG_NIOS_CPU_PIO2_ITYPE 0 /* IRQ type: none(0) */ |
||||
/* level(1)*/ |
||||
/* edge(2) */ |
||||
|
||||
#define CFG_NIOS_CPU_PIO3 0x00920990 /* PIO3 addr */ |
||||
#undef CFG_NIOS_CPU_PIO3_IRQ /* w/o IRQ */ |
||||
#define CFG_NIOS_CPU_PIO3_BITS 16 /* number of bits */ |
||||
#define CFG_NIOS_CPU_PIO3_TYPE 1 /* io type: tris(0) */ |
||||
/* out(1) */ |
||||
/* in(2) */ |
||||
#define CFG_NIOS_CPU_PIO3_CAP 0 /* capture: no(0) */ |
||||
/* yes(1) */ |
||||
#define CFG_NIOS_CPU_PIO3_EDGE 0 /* edge type: none(0) */ |
||||
/* fall(1) */ |
||||
/* rise(2) */ |
||||
/* any(3) */ |
||||
#define CFG_NIOS_CPU_PIO3_ITYPE 0 /* IRQ type: none(0) */ |
||||
/* level(1)*/ |
||||
/* edge(2) */ |
||||
|
||||
#define CFG_NIOS_CPU_PIO4 0x009209a0 /* PIO4 addr */ |
||||
#undef CFG_NIOS_CPU_PIO4_IRQ /* w/o IRQ */ |
||||
#define CFG_NIOS_CPU_PIO4_BITS 1 /* number of bits */ |
||||
#define CFG_NIOS_CPU_PIO4_TYPE 0 /* io type: tris(0) */ |
||||
/* out(1) */ |
||||
/* in(2) */ |
||||
#define CFG_NIOS_CPU_PIO4_CAP 0 /* capture: no(0) */ |
||||
/* yes(1) */ |
||||
#define CFG_NIOS_CPU_PIO4_EDGE 0 /* edge type: none(0) */ |
||||
/* fall(1) */ |
||||
/* rise(2) */ |
||||
/* any(3) */ |
||||
#define CFG_NIOS_CPU_PIO4_ITYPE 0 /* IRQ type: none(0) */ |
||||
/* level(1)*/ |
||||
/* edge(2) */ |
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|
||||
#define CFG_NIOS_CPU_PIO5 0x009209b0 /* PIO5 addr */ |
||||
#define CFG_NIOS_CPU_PIO5_IRQ 35 /* IRQ */ |
||||
#define CFG_NIOS_CPU_PIO5_BITS 1 /* number of bits */ |
||||
#define CFG_NIOS_CPU_PIO5_TYPE 2 /* io type: tris(0) */ |
||||
/* out(1) */ |
||||
/* in(2) */ |
||||
#define CFG_NIOS_CPU_PIO5_CAP 1 /* capture: no(0) */ |
||||
/* yes(1) */ |
||||
#define CFG_NIOS_CPU_PIO5_EDGE 3 /* edge type: none(0) */ |
||||
/* fall(1) */ |
||||
/* rise(2) */ |
||||
/* any(3) */ |
||||
#define CFG_NIOS_CPU_PIO5_ITYPE 2 /* IRQ type: none(0) */ |
||||
/* level(1)*/ |
||||
/* edge(2) */ |
||||
|
||||
#define CFG_NIOS_CPU_PIO6 0x009209c0 /* PIO6 addr */ |
||||
#undef CFG_NIOS_CPU_PIO6_IRQ /* w/o IRQ */ |
||||
#define CFG_NIOS_CPU_PIO6_BITS 1 /* number of bits */ |
||||
#define CFG_NIOS_CPU_PIO6_TYPE 1 /* io type: tris(0) */ |
||||
/* out(1) */ |
||||
/* in(2) */ |
||||
#define CFG_NIOS_CPU_PIO6_CAP 0 /* capture: no(0) */ |
||||
/* yes(1) */ |
||||
#define CFG_NIOS_CPU_PIO6_EDGE 0 /* edge type: none(0) */ |
||||
/* fall(1) */ |
||||
/* rise(2) */ |
||||
/* any(3) */ |
||||
#define CFG_NIOS_CPU_PIO6_ITYPE 0 /* IRQ type: none(0) */ |
||||
/* level(1)*/ |
||||
/* edge(2) */ |
||||
|
||||
#define CFG_NIOS_CPU_PIO7 0x009209d0 /* PIO7 addr */ |
||||
#undef CFG_NIOS_CPU_PIO7_IRQ /* w/o IRQ */ |
||||
#define CFG_NIOS_CPU_PIO7_BITS 1 /* number of bits */ |
||||
#define CFG_NIOS_CPU_PIO7_TYPE 1 /* io type: tris(0) */ |
||||
/* out(1) */ |
||||
/* in(2) */ |
||||
#define CFG_NIOS_CPU_PIO7_CAP 0 /* capture: no(0) */ |
||||
/* yes(1) */ |
||||
#define CFG_NIOS_CPU_PIO7_EDGE 0 /* edge type: none(0) */ |
||||
/* fall(1) */ |
||||
/* rise(2) */ |
||||
/* any(3) */ |
||||
#define CFG_NIOS_CPU_PIO7_ITYPE 0 /* IRQ type: none(0) */ |
||||
/* level(1)*/ |
||||
/* edge(2) */ |
||||
|
||||
/* IDE i/f */ |
||||
#define CFG_NIOS_CPU_IDE_NUMS 1 /* number of IDE contr. */ |
||||
#define CFG_NIOS_CPU_IDE0 0x00920a00 /* IDE0 addr */ |
||||
|
||||
/* memory accessibility */ |
||||
#define CFG_NIOS_CPU_SRAM_BASE 0x00800000 /* board SRAM addr */ |
||||
#define CFG_NIOS_CPU_SRAM_SIZE (1024 * 1024) /* 1 MB size */ |
||||
|
||||
#define CFG_NIOS_CPU_SDRAM_BASE 0x01000000 /* board SDRAM addr */ |
||||
#define CFG_NIOS_CPU_SDRAM_SIZE (16*1024*1024) /* 16 MB size */ |
||||
|
||||
#define CFG_NIOS_CPU_FLASH_BASE 0x00000000 /* board Flash addr */ |
||||
#define CFG_NIOS_CPU_FLASH_SIZE (8*1024*1024) /* 8 MB size */ |
||||
|
||||
/* LAN */ |
||||
#define CFG_NIOS_CPU_LAN_NUMS 1 /* number of LAN i/f */ |
||||
|
||||
#define CFG_NIOS_CPU_LAN0_BASE 0x00910000 /* LAN0 addr */ |
||||
#define CFG_NIOS_CPU_LAN0_OFFS 0x0300 /* offset */ |
||||
#define CFG_NIOS_CPU_LAN0_IRQ 30 /* IRQ */ |
||||
#define CFG_NIOS_CPU_LAN0_BUSW 32 /* buswidth*/ |
||||
#define CFG_NIOS_CPU_LAN0_TYPE 0 /* smc91111(0) */ |
||||
/* cs8900(1) */ |
||||
/* ex: alteramac(2) */ |
||||
|
||||
/* symbolic redefinition (undef, if not present) */ |
||||
#define CFG_NIOS_CPU_USER_TIMER 0 /* TIMER0: users choice */ |
||||
#define CFG_NIOS_CPU_TICK_TIMER 1 /* TIMER1: tick (needed)*/ |
||||
|
||||
#define CFG_NIOS_CPU_BUTTON_PIO 0 /* PIO0: buttons */ |
||||
#define CFG_NIOS_CPU_LCD_PIO 1 /* PIO1: ASCII LCD */ |
||||
#define CFG_NIOS_CPU_LED_PIO 2 /* PIO2: LED bar */ |
||||
#define CFG_NIOS_CPU_SEVENSEG_PIO 3 /* PIO3: 7-seg. display */ |
||||
#define CFG_NIOS_CPU_RECONF_PIO 4 /* PIO4: reconf pin */ |
||||
#define CFG_NIOS_CPU_CFPRESENT_PIO 5 /* PIO5: CF present IRQ */ |
||||
#define CFG_NIOS_CPU_CFPOWER_PIO 6 /* PIO6: CF power/sw. */ |
||||
#define CFG_NIOS_CPU_CFATASEL_PIO 7 /* PIO7: CF ATA select */ |
||||
|
||||
#endif /* __CONFIG_DK1S10_STANDARD_32_H */ |
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Reference in new issue