This patch changes the kilauea and kilauea_nand (for NAND booting) board port to not use a board specific DDR2 init routine anymore. Now the common code from cpu/ppc4xx is used. Thanks to Grant Erickson for all his basic work on this 405EX early bootup. Signed-off-by: Stefan Roese <sr@denx.de>master
Stefan Roese
16 years ago
parent
17ceb069b8
commit
ec724f883e
@ -1,167 +0,0 @@ |
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/* |
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* Copyright (c) 2008 Nuovation System Designs, LLC |
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* Grant Erickson <gerickson@nuovations.com>
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* |
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* (C) Copyright 2007-2008 |
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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* |
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* Originally based on code provided from UDTech and AMCC |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of
|
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <config.h> |
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#include <ppc4xx.h> |
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#include <ppc_asm.tmpl> |
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#include <ppc_defs.h> |
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#define mtsdram_as(reg, value) \ |
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addi r4,0,reg ; \
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mtdcr memcfga,r4 ; \
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addis r4,0,value@h ; \
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ori r4,r4,value@l ; \
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mtdcr memcfgd,r4 ;
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#if defined(CONFIG_DDR_ECC) |
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.extern ecc_init
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#endif /* defined(CONFIG_DDR_ECC) */ |
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.globl ext_bus_cntlr_init
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ext_bus_cntlr_init: |
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#if !defined(CFG_INIT_DCACHE_CS) |
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#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) |
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/* |
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* DDR2 SDRAM Controller Setup |
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*/ |
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/* Set Memory Bank Configuration Registers */ |
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mtsdram_as(SDRAM_MB0CF, CFG_SDRAM0_MB0CF);
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mtsdram_as(SDRAM_MB1CF, CFG_SDRAM0_MB1CF);
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mtsdram_as(SDRAM_MB2CF, CFG_SDRAM0_MB2CF);
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mtsdram_as(SDRAM_MB3CF, CFG_SDRAM0_MB3CF);
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/* Set Memory Clock Timing Register */ |
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mtsdram_as(SDRAM_CLKTR, CFG_SDRAM0_CLKTR);
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/* Set Refresh Time Register */ |
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mtsdram_as(SDRAM_RTR, CFG_SDRAM0_RTR);
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/* Set SDRAM Timing Registers */ |
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mtsdram_as(SDRAM_SDTR1, CFG_SDRAM0_SDTR1);
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mtsdram_as(SDRAM_SDTR2, CFG_SDRAM0_SDTR2);
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mtsdram_as(SDRAM_SDTR3, CFG_SDRAM0_SDTR3);
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/* Set Mode and Extended Mode Registers */ |
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mtsdram_as(SDRAM_MMODE, CFG_SDRAM0_MMODE);
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mtsdram_as(SDRAM_MEMODE, CFG_SDRAM0_MEMODE);
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/* Set Memory Controller Options 1 Register */ |
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mtsdram_as(SDRAM_MCOPT1, CFG_SDRAM0_MCOPT1);
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/* Set Manual Initialization Control Registers */ |
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mtsdram_as(SDRAM_INITPLR0, CFG_SDRAM0_INITPLR0);
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mtsdram_as(SDRAM_INITPLR1, CFG_SDRAM0_INITPLR1);
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mtsdram_as(SDRAM_INITPLR2, CFG_SDRAM0_INITPLR2);
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mtsdram_as(SDRAM_INITPLR3, CFG_SDRAM0_INITPLR3);
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mtsdram_as(SDRAM_INITPLR4, CFG_SDRAM0_INITPLR4);
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mtsdram_as(SDRAM_INITPLR5, CFG_SDRAM0_INITPLR5);
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mtsdram_as(SDRAM_INITPLR6, CFG_SDRAM0_INITPLR6);
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mtsdram_as(SDRAM_INITPLR7, CFG_SDRAM0_INITPLR7);
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mtsdram_as(SDRAM_INITPLR8, CFG_SDRAM0_INITPLR8);
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mtsdram_as(SDRAM_INITPLR9, CFG_SDRAM0_INITPLR9);
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mtsdram_as(SDRAM_INITPLR10, CFG_SDRAM0_INITPLR10);
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mtsdram_as(SDRAM_INITPLR11, CFG_SDRAM0_INITPLR11);
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mtsdram_as(SDRAM_INITPLR12, CFG_SDRAM0_INITPLR12);
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mtsdram_as(SDRAM_INITPLR13, CFG_SDRAM0_INITPLR13);
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mtsdram_as(SDRAM_INITPLR14, CFG_SDRAM0_INITPLR14);
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mtsdram_as(SDRAM_INITPLR15, CFG_SDRAM0_INITPLR15);
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/* Set On-Die Termination Registers */ |
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mtsdram_as(SDRAM_CODT, CFG_SDRAM0_CODT);
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mtsdram_as(SDRAM_MODT0, CFG_SDRAM0_MODT0);
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mtsdram_as(SDRAM_MODT1, CFG_SDRAM0_MODT1);
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/* Set Write Timing Register */ |
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mtsdram_as(SDRAM_WRDTR, CFG_SDRAM0_WRDTR);
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/* |
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* Start Initialization by SDRAM0_MCOPT2[SREN] = 0 and |
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* SDRAM0_MCOPT2[IPTR] = 1 |
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*/ |
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mtsdram_as(SDRAM_MCOPT2, SDRAM_MCOPT2_SREN_EXIT | \ |
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SDRAM_MCOPT2_IPTR_EXECUTE);
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/* |
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* Poll SDRAM0_MCSTAT[MIC] for assertion to indicate the |
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* completion of initialization. |
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* |
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* do { |
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* mfsdram(SDRAM_MCSTAT, val);
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* } while ((val & SDRAM_MCSTAT_MIC_MASK) != SDRAM_MCSTAT_MIC_COMP);
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*/ |
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li r4,SDRAM_MCSTAT |
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lis r2,SDRAM_MCSTAT_MIC_COMP@h
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ori r2,r2,SDRAM_MCSTAT_MIC_COMP@l
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0: mtdcr memcfga,r4 |
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mfdcr r3,memcfgd |
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clrrwi r3,r3,31 |
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cmpw cr7,r3,r2 |
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bne+ cr7,0b |
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/* Set Delay Control Registers */ |
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mtsdram_as(SDRAM_DLCR, CFG_SDRAM0_DLCR);
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mtsdram_as(SDRAM_RDCC, CFG_SDRAM0_RDCC);
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mtsdram_as(SDRAM_RQDC, CFG_SDRAM0_RQDC);
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mtsdram_as(SDRAM_RFDC, CFG_SDRAM0_RFDC);
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/* |
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* Enable Controller by SDRAM0_MCOPT2[DCEN] = 1: |
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* |
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* mcopt2 = mfsdram(SDRAM_MCOPT2);
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*/ |
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li r4,SDRAM_MCOPT2 |
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mtdcr memcfga,r4 |
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mfdcr r3,memcfgd |
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/* |
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* mtsdram(SDRAM_MCOPT2, mcopt2 | SDRAM_MCOPT2_DCEN_ENABLE);
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*/ |
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mtdcr memcfga,r4 |
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oris r3,r3,SDRAM_MCOPT2_DCEN_ENABLE@h
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ori r3,r3,SDRAM_MCOPT2_DCEN_ENABLE@l
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mtdcr memcfgd,r3 |
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#if defined(CONFIG_DDR_ECC) |
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/* |
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* ecc_init(CFG_SDRAM_BASE, CFG_MBYTES_SDRAM << 20);
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*/ |
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mflr r13 |
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lis r3,CFG_SDRAM_BASE@h
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ori r3,r3,CFG_SDRAM_BASE@l
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lis r4,(CFG_MBYTES_SDRAM << 20)@h
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ori r4,r4,(CFG_MBYTES_SDRAM << 20)@l
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bl ecc_init |
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mtlr r13 |
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#endif /* defined(CONFIG_DDR_ECC) */ |
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#endif /* !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) */ |
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#endif /* !defined(CFG_INIT_DCACHE_CS) */ |
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blr |
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@ -1,84 +0,0 @@ |
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/*
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* Copyright (c) 2008 Nuovation System Designs, LLC |
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* Grant Erickson <gerickson@nuovations.com> |
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* |
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* (C) Copyright 2007 |
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* Stefan Roese, DENX Software Engineering, sr@denx.de. |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <common.h> |
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#include <asm/processor.h> |
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#include <i2c.h> |
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void sdram_init(void) |
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{ |
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return; |
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} |
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#if defined(CONFIG_NAND_U_BOOT) |
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long int initdram(int board_type) |
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{ |
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return (CFG_MBYTES_SDRAM << 20); |
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} |
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#endif /* defined(CONFIG_NAND_U_BOOT) */ |
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#if defined(CFG_DRAM_TEST) |
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int testdram (void) |
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{ |
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printf ("testdram\n"); |
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#if defined (CONFIG_NAND_U_BOOT) |
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return 0; |
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#endif |
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uint *pstart = (uint *) 0x00000000; |
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uint *pend = (uint *) 0x00001000; |
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uint *p; |
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for (p = pstart; p < pend; p++) { |
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*p = 0xaaaaaaaa; |
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} |
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for (p = pstart; p < pend; p++) { |
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if (*p != 0xaaaaaaaa) { |
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#if !defined (CONFIG_NAND_SPL) |
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printf ("SDRAM test fails at: %08x\n", (uint) p); |
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#endif |
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return 1; |
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} |
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} |
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for (p = pstart; p < pend; p++) { |
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*p = 0x55555555; |
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} |
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for (p = pstart; p < pend; p++) { |
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if (*p != 0x55555555) { |
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#if !defined (CONFIG_NAND_SPL) |
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printf ("SDRAM test fails at: %08x\n", (uint) p); |
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#endif |
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return 1; |
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} |
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} |
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#if !defined (CONFIG_NAND_SPL) |
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printf ("SDRAM test passed!!!\n"); |
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#endif |
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return 0; |
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} |
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#endif |
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