ppc4xx support was removed some time ago. Lets remove the now unused NAND driver and all its references for this platform as well. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Heinrich Schuchardt <xypron.glpk@gmx.de> Cc: Scott Wood <oss@buserror.net>master
Stefan Roese
7 years ago
committed by
Tom Rini
parent
f8598d9815
commit
ec9c80d643
@ -1,200 +0,0 @@ |
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/*
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* Overview: |
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* Platform independent driver for NDFC (NanD Flash Controller) |
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* integrated into IBM/AMCC PPC4xx cores |
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* |
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* (C) Copyright 2006-2009 |
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* Stefan Roese, DENX Software Engineering, sr@denx.de. |
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* |
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* Based on original work by |
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* Thomas Gleixner |
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* Copyright 2006 IBM |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <nand.h> |
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#include <linux/mtd/ndfc.h> |
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#include <linux/mtd/nand_ecc.h> |
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#include <asm/processor.h> |
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#include <asm/io.h> |
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#include <asm/ppc4xx.h> |
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#ifndef CONFIG_SYS_NAND_BCR |
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#define CONFIG_SYS_NAND_BCR 0x80002222 |
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#endif |
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#ifndef CONFIG_SYS_NDFC_EBC0_CFG |
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#define CONFIG_SYS_NDFC_EBC0_CFG 0xb8400000 |
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#endif |
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/*
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* We need to store the info, which chip-select (CS) is used for the |
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* chip number. For example on Sequoia NAND chip #0 uses |
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* CS #3. |
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*/ |
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static int ndfc_cs[NDFC_MAX_BANKS]; |
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static void ndfc_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) |
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{ |
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struct nand_chip *this = mtd_to_nand(mtd); |
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ulong base = (ulong) this->IO_ADDR_W & 0xffffff00; |
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if (cmd == NAND_CMD_NONE) |
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return; |
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if (ctrl & NAND_CLE) |
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out_8((u8 *)(base + NDFC_CMD), cmd & 0xFF); |
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else |
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out_8((u8 *)(base + NDFC_ALE), cmd & 0xFF); |
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} |
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static int ndfc_dev_ready(struct mtd_info *mtdinfo) |
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{ |
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struct nand_chip *this = mtd_to_nand(mtdinfo); |
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ulong base = (ulong) this->IO_ADDR_W & 0xffffff00; |
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return (in_be32((u32 *)(base + NDFC_STAT)) & NDFC_STAT_IS_READY); |
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} |
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static void ndfc_enable_hwecc(struct mtd_info *mtdinfo, int mode) |
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{ |
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struct nand_chip *this = mtd_to_nand(mtdinfo); |
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ulong base = (ulong) this->IO_ADDR_W & 0xffffff00; |
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u32 ccr; |
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ccr = in_be32((u32 *)(base + NDFC_CCR)); |
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ccr |= NDFC_CCR_RESET_ECC; |
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out_be32((u32 *)(base + NDFC_CCR), ccr); |
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} |
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static int ndfc_calculate_ecc(struct mtd_info *mtdinfo, |
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const u_char *dat, u_char *ecc_code) |
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{ |
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struct nand_chip *this = mtd_to_nand(mtdinfo); |
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ulong base = (ulong) this->IO_ADDR_W & 0xffffff00; |
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u32 ecc; |
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u8 *p = (u8 *)&ecc; |
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ecc = in_be32((u32 *)(base + NDFC_ECC)); |
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/* The NDFC uses Smart Media (SMC) bytes order
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*/ |
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ecc_code[0] = p[1]; |
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ecc_code[1] = p[2]; |
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ecc_code[2] = p[3]; |
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return 0; |
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} |
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/*
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* Speedups for buffer read/write/verify |
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* |
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* NDFC allows 32bit read/write of data. So we can speed up the buffer |
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* functions. No further checking, as nand_base will always read/write |
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* page aligned. |
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*/ |
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static void ndfc_read_buf(struct mtd_info *mtdinfo, uint8_t *buf, int len) |
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{ |
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struct nand_chip *this = mtd_to_nand(mtdinfo); |
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ulong base = (ulong) this->IO_ADDR_W & 0xffffff00; |
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uint32_t *p = (uint32_t *) buf; |
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for (;len > 0; len -= 4) |
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*p++ = in_be32((u32 *)(base + NDFC_DATA)); |
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} |
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/*
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* Don't use these speedup functions in NAND boot image, since the image |
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* has to fit into 4kByte. |
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*/ |
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static void ndfc_write_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len) |
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{ |
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struct nand_chip *this = mtd_to_nand(mtdinfo); |
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ulong base = (ulong) this->IO_ADDR_W & 0xffffff00; |
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uint32_t *p = (uint32_t *) buf; |
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for (; len > 0; len -= 4) |
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out_be32((u32 *)(base + NDFC_DATA), *p++); |
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} |
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/*
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* Read a byte from the NDFC. |
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*/ |
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static uint8_t ndfc_read_byte(struct mtd_info *mtd) |
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{ |
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struct nand_chip *chip = mtd_to_nand(mtd); |
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#ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT |
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return (uint8_t) readw(chip->IO_ADDR_R); |
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#else |
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return readb(chip->IO_ADDR_R); |
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#endif |
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} |
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void board_nand_select_device(struct nand_chip *nand, int chip) |
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{ |
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/*
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* Don't use "chip" to address the NAND device, |
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* generate the cs from the address where it is encoded. |
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*/ |
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ulong base = (ulong)nand->IO_ADDR_W & 0xffffff00; |
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int cs = ndfc_cs[chip]; |
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/* Set NandFlash Core Configuration Register */ |
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/* 1 col x 2 rows */ |
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out_be32((u32 *)(base + NDFC_CCR), 0x00000000 | (cs << 24)); |
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out_be32((u32 *)(base + NDFC_BCFG0 + (cs << 2)), CONFIG_SYS_NAND_BCR); |
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} |
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static void ndfc_select_chip(struct mtd_info *mtd, int chip) |
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{ |
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/*
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* Nothing to do here! |
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*/ |
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} |
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int board_nand_init(struct nand_chip *nand) |
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{ |
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int cs = (ulong)nand->IO_ADDR_W & 0x00000003; |
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ulong base = (ulong)nand->IO_ADDR_W & 0xffffff00; |
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static int chip = 0; |
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/*
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* Save chip-select for this chip # |
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*/ |
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ndfc_cs[chip] = cs; |
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/*
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* Select required NAND chip in NDFC |
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*/ |
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board_nand_select_device(nand, chip); |
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nand->IO_ADDR_R = (void __iomem *)(base + NDFC_DATA); |
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nand->IO_ADDR_W = (void __iomem *)(base + NDFC_DATA); |
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nand->cmd_ctrl = ndfc_hwcontrol; |
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nand->chip_delay = 50; |
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nand->read_buf = ndfc_read_buf; |
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nand->dev_ready = ndfc_dev_ready; |
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nand->ecc.correct = nand_correct_data; |
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nand->ecc.hwctl = ndfc_enable_hwecc; |
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nand->ecc.calculate = ndfc_calculate_ecc; |
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nand->ecc.mode = NAND_ECC_HW; |
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nand->ecc.size = 256; |
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nand->ecc.bytes = 3; |
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nand->ecc.strength = 1; |
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nand->select_chip = ndfc_select_chip; |
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#ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT |
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nand->options |= NAND_BUSWIDTH_16; |
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#endif |
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nand->write_buf = ndfc_write_buf; |
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nand->read_byte = ndfc_read_byte; |
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chip++; |
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return 0; |
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} |
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