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@ -256,14 +256,13 @@ pci_init_board(void) |
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} else { |
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printf (" PCIE3: disabled\n"); |
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} |
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} |
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} |
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#else |
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gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */ |
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#endif |
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#ifdef CONFIG_PCIE1 |
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{ |
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{ |
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volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; |
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struct pci_controller *hose = &pcie1_hose; |
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int pcie_ep = (host_agent == 5); |
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@ -315,14 +314,13 @@ pci_init_board(void) |
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} else { |
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printf (" PCIE1: disabled\n"); |
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} |
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} |
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} |
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#else |
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gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */ |
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#endif |
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#ifdef CONFIG_PCIE2 |
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{ |
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{ |
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volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR; |
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struct pci_controller *hose = &pcie2_hose; |
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int pcie_ep = (host_agent == 3); |
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@ -372,13 +370,11 @@ pci_init_board(void) |
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} else { |
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printf (" PCIE2: disabled\n"); |
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} |
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} |
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} |
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#else |
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gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */ |
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#endif |
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#ifdef CONFIG_PCI1 |
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{ |
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volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR; |
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@ -391,7 +387,6 @@ pci_init_board(void) |
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uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */ |
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uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */ |
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if (!(devdisr & MPC85xx_DEVDISR_PCI1)) { |
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printf ("\n PCI: %d bit, %s MHz, %s, %s, %s (base address %x)\n", |
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(pci_32) ? 32 : 64, |
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@ -441,7 +436,6 @@ pci_init_board(void) |
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#endif |
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} |
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int board_early_init_r(void) |
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{ |
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const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; |
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