powerpc/85xx: Rename Security Engine Job Queue to Job Ring to match docs

Official docs call it the Job Ring not Job Queue for the p4080 security
block.  Match the docs to reduce confusion.

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
master
Kumar Gala 15 years ago
parent 680c613a5c
commit ed062e0f6c
  1. 8
      arch/powerpc/cpu/mpc85xx/p4080_ids.c
  2. 8
      arch/powerpc/include/asm/fsl_liodn.h
  3. 6
      arch/powerpc/include/asm/immap_85xx.h

@ -81,10 +81,10 @@ struct liodn_id_table fman2_liodn_tbl[] = {
#endif
struct liodn_id_table sec_liodn_tbl[] = {
SET_SEC_JQ_LIODN_ENTRY(0, 146, 154),
SET_SEC_JQ_LIODN_ENTRY(1, 147, 155),
SET_SEC_JQ_LIODN_ENTRY(2, 178, 186),
SET_SEC_JQ_LIODN_ENTRY(3, 179, 187),
SET_SEC_JR_LIODN_ENTRY(0, 146, 154),
SET_SEC_JR_LIODN_ENTRY(1, 147, 155),
SET_SEC_JR_LIODN_ENTRY(2, 178, 186),
SET_SEC_JR_LIODN_ENTRY(3, 179, 187),
SET_SEC_RTIC_LIODN_ENTRY(a, 144),
SET_SEC_RTIC_LIODN_ENTRY(b, 145),
SET_SEC_RTIC_LIODN_ENTRY(c, 176),

@ -115,11 +115,11 @@ extern void fdt_fixup_liodn(void *blob);
FM_PPID_RX_PORT_OFFSET(fmNum, enetNum + 16), \
CONFIG_SYS_FSL_FM##fmNum##_RX##enetNum##_10G_OFFSET) \
#define SET_SEC_JQ_LIODN_ENTRY(jqNum, liodnA, liodnB) \
SET_LIODN_ENTRY_2("fsl,sec4.0-job-queue", liodnA, liodnB,\
offsetof(ccsr_sec_t, jqliodnr[jqNum].ls) + \
#define SET_SEC_JR_LIODN_ENTRY(jrNum, liodnA, liodnB) \
SET_LIODN_ENTRY_2("fsl,sec4.0-job-ring", liodnA, liodnB,\
offsetof(ccsr_sec_t, jrliodnr[jrNum].ls) + \
CONFIG_SYS_FSL_SEC_OFFSET, \
CONFIG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jqNum)
CONFIG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jrNum)
/* This is a bit evil since we treat rtic param as both a string & hex value */
#define SET_SEC_RTIC_LIODN_ENTRY(rtic, liodnA) \

@ -2063,7 +2063,7 @@ typedef struct ccsr_sec {
struct {
u32 ms; /* Job Ring LIODN Register, MS */
u32 ls; /* Job Ring LIODN Register, LS */
} jqliodnr[4];
} jrliodnr[4];
u8 res2[0x30];
struct {
u32 ms; /* RTIC LIODN Register, MS */
@ -2108,8 +2108,8 @@ typedef struct ccsr_sec {
#define SEC_CTPR_MS_AXI_LIODN 0x08000000
#define SEC_CTPR_MS_QI 0x02000000
#define SEC_RVID_MA 0x0f000000
#define SEC_CHANUM_MS_JQNUM_MASK 0xf0000000
#define SEC_CHANUM_MS_JQNUM_SHIFT 28
#define SEC_CHANUM_MS_JRNUM_MASK 0xf0000000
#define SEC_CHANUM_MS_JRNUM_SHIFT 28
#define SEC_CHANUM_MS_DECONUM_MASK 0x0f000000
#define SEC_CHANUM_MS_DECONUM_SHIFT 24
#endif

Loading…
Cancel
Save