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mips: ath79: add support for AR933x SOCs

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This patch enable work for ar933x SOC.

Signed-off-by: Wills Wang <wills.wang@live.com>
master
Wills Wang 9 years ago committed by Daniel Schwierzeck
parent 1d3d0f1f1c
commit ee7bb5be35
6 changed files with 720 additions and 0 deletions
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  1. 9
      arch/mips/mach-ath79/Kconfig
  2. 2
      arch/mips/mach-ath79/Makefile
  3. 7
      arch/mips/mach-ath79/ar933x/Makefile
  4. 89
      arch/mips/mach-ath79/ar933x/clk.c
  5. 333
      arch/mips/mach-ath79/ar933x/ddr.c
  6. 280
      arch/mips/mach-ath79/ar933x/lowlevel_init.S

9
arch/mips/mach-ath79/Kconfig
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@ -4,4 +4,13 @@ menu "QCA/Atheros 7xxx/9xxx platforms"
config SYS_SOC
default "ath79"
config SOC_AR933X
bool
select SUPPORTS_BIG_ENDIAN
select SUPPORTS_CPU_MIPS32_R1
select SUPPORTS_CPU_MIPS32_R2
select MIPS_TUNE_24KC
help
This supports QCA/Atheros ar933x family SOCs.
endmenu

2
arch/mips/mach-ath79/Makefile
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@ -5,3 +5,5 @@
obj-y += reset.o
obj-y += cpu.o
obj-y += dram.o
obj-$(CONFIG_SOC_AR933X) += ar933x/

7
arch/mips/mach-ath79/ar933x/Makefile
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@ -0,0 +1,7 @@
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += clk.o
obj-y += ddr.o
obj-y += lowlevel_init.o

89
arch/mips/mach-ath79/ar933x/clk.c
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/*
* Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/addrspace.h>
#include <asm/types.h>
#include <mach/ar71xx_regs.h>
#include <mach/reset.h>
DECLARE_GLOBAL_DATA_PTR;
static u32 ar933x_get_xtal(void)
{
u32 val;
val = get_bootstrap();
if (val & AR933X_BOOTSTRAP_REF_CLK_40)
return 40000000;
else
return 25000000;
}
int get_serial_clock(void)
{
return ar933x_get_xtal();
}
int get_clocks(void)
{
void __iomem *regs;
u32 val, xtal, pll, div;
regs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE,
MAP_NOCACHE);
xtal = ar933x_get_xtal();
val = readl(regs + AR933X_PLL_CPU_CONFIG_REG);
/* VCOOUT = XTAL * DIV_INT */
div = (val >> AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT)
& AR933X_PLL_CPU_CONFIG_REFDIV_MASK;
pll = xtal / div;
/* PLLOUT = VCOOUT * (1/2^OUTDIV) */
div = (val >> AR933X_PLL_CPU_CONFIG_NINT_SHIFT)
& AR933X_PLL_CPU_CONFIG_NINT_MASK;
pll *= div;
div = (val >> AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT)
& AR933X_PLL_CPU_CONFIG_OUTDIV_MASK;
if (!div)
div = 1;
pll >>= div;
val = readl(regs + AR933X_PLL_CLK_CTRL_REG);
/* CPU_CLK = PLLOUT / CPU_POST_DIV */
div = ((val >> AR933X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT)
& AR933X_PLL_CLK_CTRL_CPU_POST_DIV_MASK) + 1;
gd->cpu_clk = pll / div;
/* DDR_CLK = PLLOUT / DDR_POST_DIV */
div = ((val >> AR933X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT)
& AR933X_PLL_CLK_CTRL_DDR_POST_DIV_MASK) + 1;
gd->mem_clk = pll / div;
/* AHB_CLK = PLLOUT / AHB_POST_DIV */
div = ((val >> AR933X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT)
& AR933X_PLL_CLK_CTRL_AHB_POST_DIV_MASK) + 1;
gd->bus_clk = pll / div;
return 0;
}
ulong get_bus_freq(ulong dummy)
{
if (!gd->bus_clk)
get_clocks();
return gd->bus_clk;
}
ulong get_ddr_freq(ulong dummy)
{
if (!gd->mem_clk)
get_clocks();
return gd->mem_clk;
}

333
arch/mips/mach-ath79/ar933x/ddr.c
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@ -0,0 +1,333 @@
/*
* Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
* Based on Atheros LSDK/QSDK
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/addrspace.h>
#include <asm/types.h>
#include <mach/ar71xx_regs.h>
#include <mach/reset.h>
DECLARE_GLOBAL_DATA_PTR;
#define DDR_CTRL_UPD_EMR3S BIT(5)
#define DDR_CTRL_UPD_EMR2S BIT(4)
#define DDR_CTRL_PRECHARGE BIT(3)
#define DDR_CTRL_AUTO_REFRESH BIT(2)
#define DDR_CTRL_UPD_EMRS BIT(1)
#define DDR_CTRL_UPD_MRS BIT(0)
#define DDR_REFRESH_EN (1 << 14)
#define DDR_REFRESH_M 0x3ff
#define DDR_REFRESH(x) ((x) & 0x3ff)
#define DDR_REFRESH_VAL_25M (DDR_REFRESH_EN | DDR_REFRESH(390))
#define DDR_REFRESH_VAL_40M (DDR_REFRESH_EN | DDR_REFRESH(624))
#define DDR_TRAS_S 0
#define DDR_TRAS_M 0x1f
#define DDR_TRAS(x) ((x) << DDR_TRAS_S)
#define DDR_TRCD_M 0xf
#define DDR_TRCD_S 5
#define DDR_TRCD(x) ((x) << DDR_TRCD_S)
#define DDR_TRP_M 0xf
#define DDR_TRP_S 9
#define DDR_TRP(x) ((x) << DDR_TRP_S)
#define DDR_TRRD_M 0xf
#define DDR_TRRD_S 13
#define DDR_TRRD(x) ((x) << DDR_TRRD_S)
#define DDR_TRFC_M 0x7f
#define DDR_TRFC_S 17
#define DDR_TRFC(x) ((x) << DDR_TRFC_S)
#define DDR_TMRD_M 0xf
#define DDR_TMRD_S 23
#define DDR_TMRD(x) ((x) << DDR_TMRD_S)
#define DDR_CAS_L_M 0x17
#define DDR_CAS_L_S 27
#define DDR_CAS_L(x) (((x) & DDR_CAS_L_M) << DDR_CAS_L_S)
#define DDR_OPEN (1 << 30)
#define DDR_CONF_REG_VAL (DDR_TRAS(16) | DDR_TRCD(6) | \
DDR_TRP(6) | DDR_TRRD(4) | \
DDR_TRFC(30) | DDR_TMRD(15) | \
DDR_CAS_L(7) | DDR_OPEN)
#define DDR_BURST_LEN_S 0
#define DDR_BURST_LEN_M 0xf
#define DDR_BURST_LEN(x) ((x) << DDR_BURST_LEN_S)
#define DDR_BURST_TYPE (1 << 4)
#define DDR_CNTL_OE_EN (1 << 5)
#define DDR_PHASE_SEL (1 << 6)
#define DDR_CKE (1 << 7)
#define DDR_TWR_S 8
#define DDR_TWR_M 0xf
#define DDR_TWR(x) ((x) << DDR_TWR_S)
#define DDR_TRTW_S 12
#define DDR_TRTW_M 0x1f
#define DDR_TRTW(x) ((x) << DDR_TRTW_S)
#define DDR_TRTP_S 17
#define DDR_TRTP_M 0xf
#define DDR_TRTP(x) ((x) << DDR_TRTP_S)
#define DDR_TWTR_S 21
#define DDR_TWTR_M 0x1f
#define DDR_TWTR(x) ((x) << DDR_TWTR_S)
#define DDR_G_OPEN_L_S 26
#define DDR_G_OPEN_L_M 0xf
#define DDR_G_OPEN_L(x) ((x) << DDR_G_OPEN_L_S)
#define DDR_HALF_WIDTH_LOW (1 << 31)
#define DDR_CONF2_REG_VAL (DDR_BURST_LEN(8) | DDR_CNTL_OE_EN | \
DDR_CKE | DDR_TWR(6) | DDR_TRTW(14) | \
DDR_TRTP(8) | DDR_TWTR(14) | \
DDR_G_OPEN_L(7) | DDR_HALF_WIDTH_LOW)
#define DDR2_CONF_TWL_S 10
#define DDR2_CONF_TWL_M 0xf
#define DDR2_CONF_TWL(x) (((x) & DDR2_CONF_TWL_M) << DDR2_CONF_TWL_S)
#define DDR2_CONF_ODT BIT(9)
#define DDR2_CONF_TFAW_S 2
#define DDR2_CONF_TFAW_M 0x3f
#define DDR2_CONF_TFAW(x) (((x) & DDR2_CONF_TFAW_M) << DDR2_CONF_TFAW_S)
#define DDR2_CONF_EN BIT(0)
#define DDR2_CONF_VAL (DDR2_CONF_TWL(2) | DDR2_CONF_ODT | \
DDR2_CONF_TFAW(22) | DDR2_CONF_EN)
#define DDR1_EXT_MODE_VAL 0x02
#define DDR2_EXT_MODE_VAL 0x402
#define DDR2_EXT_MODE_OCD_VAL 0x382
#define DDR1_MODE_DLL_VAL 0x133
#define DDR2_MODE_DLL_VAL 0x100
#define DDR1_MODE_VAL 0x33
#define DDR2_MODE_VAL 0xa33
#define DDR_TAP_VAL0 0x08
#define DDR_TAP_VAL1 0x09
void ddr_init(void)
{
void __iomem *regs;
u32 val;
regs = map_physmem(AR71XX_DDR_CTRL_BASE, AR71XX_DDR_CTRL_SIZE,
MAP_NOCACHE);
writel(DDR_CONF_REG_VAL, regs + AR71XX_DDR_REG_CONFIG);
writel(DDR_CONF2_REG_VAL, regs + AR71XX_DDR_REG_CONFIG2);
val = get_bootstrap();
if (val & AR933X_BOOTSTRAP_DDR2) {
/* AHB maximum timeout */
writel(0xfffff, regs + AR933X_DDR_REG_TIMEOUT_MAX);
/* Enable DDR2 */
writel(DDR2_CONF_VAL, regs + AR933X_DDR_REG_DDR2_CONFIG);
/* Precharge All */
writel(DDR_CTRL_PRECHARGE, regs + AR71XX_DDR_REG_CONTROL);
/* Disable High Temperature Self-Refresh, Full Array */
writel(0x00, regs + AR933X_DDR_REG_EMR2);
/* Extended Mode Register 2 Set (EMR2S) */
writel(DDR_CTRL_UPD_EMR2S, regs + AR71XX_DDR_REG_CONTROL);
writel(0x00, regs + AR933X_DDR_REG_EMR3);
/* Extended Mode Register 3 Set (EMR3S) */
writel(DDR_CTRL_UPD_EMR3S, regs + AR71XX_DDR_REG_CONTROL);
/* Enable DLL, Full strength, ODT Disabled */
writel(0x00, regs + AR71XX_DDR_REG_EMR);
/* Extended Mode Register Set (EMRS) */
writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL);
/* Reset DLL */
writel(DDR2_MODE_DLL_VAL, regs + AR71XX_DDR_REG_MODE);
/* Mode Register Set (MRS) */
writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL);
/* Precharge All */
writel(DDR_CTRL_PRECHARGE, regs + AR71XX_DDR_REG_CONTROL);
/* Auto Refresh */
writel(DDR_CTRL_AUTO_REFRESH, regs + AR71XX_DDR_REG_CONTROL);
writel(DDR_CTRL_AUTO_REFRESH, regs + AR71XX_DDR_REG_CONTROL);
/* Write recovery (WR) 6 clock, CAS Latency 3, Burst Length 8 */
writel(DDR2_MODE_VAL, regs + AR71XX_DDR_REG_MODE);
/* Mode Register Set (MRS) */
writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL);
/* Enable OCD defaults, Enable DLL, Reduced Drive Strength */
writel(DDR2_EXT_MODE_OCD_VAL, regs + AR71XX_DDR_REG_EMR);
/* Extended Mode Register Set (EMRS) */
writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL);
/* OCD exit, Enable DLL, Enable /DQS, Reduced Drive Strength */
writel(DDR2_EXT_MODE_VAL, regs + AR71XX_DDR_REG_EMR);
/* Extended Mode Register Set (EMRS) */
writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL);
/* Refresh time control */
if (val & AR933X_BOOTSTRAP_REF_CLK_40)
writel(DDR_REFRESH_VAL_40M, regs +
AR71XX_DDR_REG_REFRESH);
else
writel(DDR_REFRESH_VAL_25M, regs +
AR71XX_DDR_REG_REFRESH);
/* DQS 0 Tap Control */
writel(DDR_TAP_VAL0, regs + AR71XX_DDR_REG_TAP_CTRL0);
/* DQS 1 Tap Control */
writel(DDR_TAP_VAL1, regs + AR71XX_DDR_REG_TAP_CTRL1);
/* For 16-bit DDR */
writel(0xff, regs + AR71XX_DDR_REG_RD_CYCLE);
} else {
/* AHB maximum timeout */
writel(0xfffff, regs + AR933X_DDR_REG_TIMEOUT_MAX);
/* Precharge All */
writel(DDR_CTRL_PRECHARGE, regs + AR71XX_DDR_REG_CONTROL);
/* Reset DLL, Burst Length 8, CAS Latency 3 */
writel(DDR1_MODE_DLL_VAL, regs + AR71XX_DDR_REG_MODE);
/* Forces an MRS update cycle in DDR */
writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL);
/* Enable DLL, Full strength */
writel(DDR1_EXT_MODE_VAL, regs + AR71XX_DDR_REG_EMR);
/* Extended Mode Register Set (EMRS) */
writel(DDR_CTRL_UPD_EMRS, regs + AR71XX_DDR_REG_CONTROL);
/* Precharge All */
writel(DDR_CTRL_PRECHARGE, regs + AR71XX_DDR_REG_CONTROL);
/* Normal DLL, Burst Length 8, CAS Latency 3 */
writel(DDR1_MODE_VAL, regs + AR71XX_DDR_REG_MODE);
/* Mode Register Set (MRS) */
writel(DDR_CTRL_UPD_MRS, regs + AR71XX_DDR_REG_CONTROL);
/* Refresh time control */
if (val & AR933X_BOOTSTRAP_REF_CLK_40)
writel(DDR_REFRESH_VAL_40M, regs +
AR71XX_DDR_REG_REFRESH);
else
writel(DDR_REFRESH_VAL_25M, regs +
AR71XX_DDR_REG_REFRESH);
/* DQS 0 Tap Control */
writel(DDR_TAP_VAL0, regs + AR71XX_DDR_REG_TAP_CTRL0);
/* DQS 1 Tap Control */
writel(DDR_TAP_VAL1, regs + AR71XX_DDR_REG_TAP_CTRL1);
/* For 16-bit DDR */
writel(0xff, regs + AR71XX_DDR_REG_RD_CYCLE);
}
}
void ddr_tap_tuning(void)
{
void __iomem *regs;
u32 *addr_k0, *addr_k1, *addr;
u32 val, tap, upper, lower;
int i, j, dir, err, done;
regs = map_physmem(AR71XX_DDR_CTRL_BASE, AR71XX_DDR_CTRL_SIZE,
MAP_NOCACHE);
/* Init memory pattern */
addr = (void *)CKSEG0ADDR(0x2000);
for (i = 0; i < 256; i++) {
val = 0;
for (j = 0; j < 8; j++) {
if (i & (1 << j)) {
if (j % 2)
val |= 0xffff0000;
else
val |= 0x0000ffff;
}
if (j % 2) {
*addr++ = val;
val = 0;
}
}
}
err = 0;
done = 0;
dir = 1;
tap = readl(regs + AR71XX_DDR_REG_TAP_CTRL0);
val = tap;
while (!done) {
err = 0;
/* Update new DDR tap value */
writel(val, regs + AR71XX_DDR_REG_TAP_CTRL0);
writel(val, regs + AR71XX_DDR_REG_TAP_CTRL1);
/* Compare DDR with cache */
for (i = 0; i < 2; i++) {
addr_k1 = (void *)CKSEG1ADDR(0x2000);
addr_k0 = (void *)CKSEG0ADDR(0x2000);
addr = (void *)CKSEG0ADDR(0x3000);
while (addr_k0 < addr) {
if (*addr_k1++ != *addr_k0++) {
err = 1;
break;
}
}
if (err)
break;
}
if (err) {
/* Save upper/lower threshold if error */
if (dir) {
dir = 0;
val--;
upper = val;
val = tap;
} else {
val++;
lower = val;
done = 1;
}
} else {
/* Try the next value until limitation */
if (dir) {
if (val < 0x20) {
val++;
} else {
dir = 0;
upper = val;
val = tap;
}
} else {
if (!val) {
lower = val;
done = 1;
} else {
val--;
}
}
}
}
/* compute an intermediate value and write back */
val = (upper + lower) / 2;
writel(val, regs + AR71XX_DDR_REG_TAP_CTRL0);
val++;
writel(val, regs + AR71XX_DDR_REG_TAP_CTRL1);
}

280
arch/mips/mach-ath79/ar933x/lowlevel_init.S
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/*
* Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
* Based on Atheros LSDK/QSDK and u-boot_mod project
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <config.h>
#include <asm/asm.h>
#include <asm/regdef.h>
#include <asm/mipsregs.h>
#include <asm/addrspace.h>
#include <mach/ar71xx_regs.h>
#define SET_BIT(val, bit) ((val) | (1 << (bit)))
#define SET_PLL_PD(val) SET_BIT(val, 30)
#define AHB_DIV_TO_4(val) SET_BIT(SET_BIT(val, 15), 16)
#define PLL_BYPASS(val) SET_BIT(val, 2)
#define MK_PLL_CONF(divint, refdiv, range, outdiv) \
(((0x3F & divint) << 10) | \
((0x1F & refdiv) << 16) | \
((0x1 & range) << 21) | \
((0x7 & outdiv) << 23) )
#define MK_CLK_CNTL(cpudiv, ddrdiv, ahbdiv) \
(((0x3 & (cpudiv - 1)) << 5) | \
((0x3 & (ddrdiv - 1)) << 10) | \
((0x3 & (ahbdiv - 1)) << 15) )
/*
* PLL_CPU_CONFIG_VAL
*
* Bit30 is set (CPU_PLLPWD = 1 -> power down control for CPU PLL)
* After PLL configuration we need to clear this bit
*
* Values written into CPU PLL Configuration (CPU_PLL_CONFIG)
*
* bits 10..15 (6bit) DIV_INT (Integer part of the DIV to CPU PLL)
* => 32 (0x20) VCOOUT = XTAL * DIV_INT
* bits 16..20 (5bit) REFDIV (Reference clock divider)
* => 1 (0x1) [Must start at values 1]
* bits 21 (1bit) RANGE (VCO frequency range of the CPU PLL)
* => 0 (0x0) [Doesn't impact clock values]
* bits 23..25 (3bit) OUTDIV (Ratio between VCO and PLL output)
* => 1 (0x1) [0 is illegal!]
* PLLOUT = VCOOUT * (1/2^OUTDIV)
*/
/* DIV_INT=32 (25MHz*32/2=400MHz), REFDIV=1, RANGE=0, OUTDIV=1 */
#define PLL_CPU_CONFIG_VAL_40M MK_PLL_CONF(20, 1, 0, 1)
/* DIV_INT=20 (40MHz*20/2=400MHz), REFDIV=1, RANGE=0, OUTDIV=1 */
#define PLL_CPU_CONFIG_VAL_25M MK_PLL_CONF(32, 1, 0, 1)
/*
* PLL_CLK_CONTROL_VAL
*
* In PLL_CLK_CONTROL_VAL bit 2 is set (BYPASS = 1 -> bypass PLL)
* After PLL configuration we need to clear this bit
*
* Values written into CPU Clock Control Register CLOCK_CONTROL
*
* bits 2 (1bit) BYPASS (Bypass PLL. This defaults to 1 for test.
* Software must enable the CPU PLL for normal and
* then set this bit to 0)
* bits 5..6 (2bit) CPU_POST_DIV => 0 (DEFAULT, Ratio = 1)
* CPU_CLK = PLLOUT / CPU_POST_DIV
* bits 10..11 (2bit) DDR_POST_DIV => 0 (DEFAULT, Ratio = 1)
* DDR_CLK = PLLOUT / DDR_POST_DIV
* bits 15..16 (2bit) AHB_POST_DIV => 1 (DEFAULT, Ratio = 2)
* AHB_CLK = PLLOUT / AHB_POST_DIV
*
*/
#define PLL_CLK_CONTROL_VAL MK_CLK_CNTL(1, 1, 2)
.text
.set noreorder
LEAF(lowlevel_init)
/* These three WLAN_RESET will avoid original issue */
li t3, 0x03
1:
li t0, CKSEG1ADDR(AR71XX_RESET_BASE)
lw t1, AR933X_RESET_REG_RESET_MODULE(t0)
ori t1, t1, 0x0800
sw t1, AR933X_RESET_REG_RESET_MODULE(t0)
nop
lw t1, AR933X_RESET_REG_RESET_MODULE(t0)
li t2, 0xfffff7ff
and t1, t1, t2
sw t1, AR933X_RESET_REG_RESET_MODULE(t0)
nop
addi t3, t3, -1
bnez t3, 1b
nop
li t2, 0x20
2:
beqz t2, 1b
nop
addi t2, t2, -1
lw t5, AR933X_RESET_REG_BOOTSTRAP(t0)
andi t1, t5, 0x10
bnez t1, 2b
nop
li t1, 0x02110E
sw t1, AR933X_RESET_REG_BOOTSTRAP(t0)
nop
/* RTC Force Wake */
li t0, CKSEG1ADDR(AR933X_RTC_BASE)
li t1, 0x03
sw t1, AR933X_RTC_REG_FORCE_WAKE(t0)
nop
nop
/* RTC Reset */
li t1, 0x00
sw t1, AR933X_RTC_REG_RESET(t0)
nop
nop
li t1, 0x01
sw t1, AR933X_RTC_REG_RESET(t0)
nop
nop
/* Wait for RTC in on state */
1:
lw t1, AR933X_RTC_REG_STATUS(t0)
andi t1, t1, 0x02
beqz t1, 1b
nop
/* Program ki/kd */
li t0, CKSEG1ADDR(AR933X_SRIF_BASE)
andi t1, t5, 0x01 # t5 BOOT_STRAP
bnez t1, 1f
nop
li t1, 0x19e82f01
b 2f
nop
1:
li t1, 0x18e82f01
2:
sw t1, AR933X_SRIF_DDR_DPLL2_REG(t0)
/* Program phase shift */
lw t1, AR933X_SRIF_DDR_DPLL3_REG(t0)
li t2, 0xc07fffff
and t1, t1, t2
li t2, 0x800000
or t1, t1, t2
sw t1, AR933X_SRIF_DDR_DPLL3_REG(t0)
nop
/* in some cases, the SoC doesn't start with higher clock on AHB */
li t0, CKSEG1ADDR(AR71XX_PLL_BASE)
li t1, AHB_DIV_TO_4(PLL_BYPASS(PLL_CLK_CONTROL_VAL))
sw t1, AR933X_PLL_CLK_CTRL_REG(t0)
nop
/* Set SETTLE_TIME in CPU PLL */
andi t1, t5, 0x01 # t5 BOOT_STRAP
bnez t1, 1f
nop
li t1, 0x0352
b 2f
nop
1:
li t1, 0x0550
2:
sw t1, AR71XX_PLL_REG_SEC_CONFIG(t0)
nop
/* Set nint, frac, refdiv, outdiv, range according to xtal */
0:
andi t1, t5, 0x01 # t5 BOOT_STRAP
bnez t1, 1f
nop
li t1, SET_PLL_PD(PLL_CPU_CONFIG_VAL_25M)
b 2f
nop
1:
li t1, SET_PLL_PD(PLL_CPU_CONFIG_VAL_40M)
2:
sw t1, AR933X_PLL_CPU_CONFIG_REG(t0)
nop
1:
lw t1, AR933X_PLL_CPU_CONFIG_REG(t0)
li t2, 0x80000000
and t1, t1, t2
bnez t1, 1b
nop
/* Put frac bit19:10 configuration */
li t1, 0x1003E8
sw t1, AR933X_PLL_DITHER_FRAC_REG(t0)
nop
/* Clear PLL power down bit in CPU PLL configuration */
andi t1, t5, 0x01 # t5 BOOT_STRAP
bnez t1, 1f
nop
li t1, PLL_CPU_CONFIG_VAL_25M
b 2f
nop
1:
li t1, PLL_CPU_CONFIG_VAL_40M
2:
sw t1, AR933X_PLL_CPU_CONFIG_REG(t0)
nop
/* Wait for PLL update -> bit 31 in CPU_PLL_CONFIG should be 0 */
1:
lw t1, AR933X_PLL_CPU_CONFIG_REG(t0)
li t2, 0x80000000
and t1, t1, t2
bnez t1, 1b
nop
/* Confirm DDR PLL lock */
li t3, 100
li t4, 0
2:
addi t4, t4, 1
bgt t4, t3, 0b
nop
li t3, 5
3:
/* Clear do_meas */
li t0, CKSEG1ADDR(AR933X_SRIF_BASE)
lw t1, AR933X_SRIF_DDR_DPLL3_REG(t0)
li t2, 0xBFFFFFFF
and t1, t1, t2
sw t1, AR933X_SRIF_DDR_DPLL3_REG(t0)
nop
li t2, 10
1:
subu t2, t2, 1
bnez t2, 1b
nop
/* Set do_meas */
li t2, 0x40000000
or t1, t1, t2
sw t1, AR933X_SRIF_DDR_DPLL3_REG(t0)
nop
/* Check meas_done */
1:
lw t1, AR933X_SRIF_DDR_DPLL4_REG(t0)
andi t1, t1, 0x8
beqz t1, 1b
nop
lw t1, AR933X_SRIF_DDR_DPLL3_REG(t0)
li t2, 0x007FFFF8
and t1, t1, t2
srl t1, t1, 3
li t2, 0x4000
bgt t1, t2, 2b
nop
addi t3, t3, -1
bnez t3, 3b
nop
/* clear PLL bypass (bit 2) in CPU CLOCK CONTROL register */
li t0, CKSEG1ADDR(AR71XX_PLL_BASE)
li t1, PLL_CLK_CONTROL_VAL
sw t1, AR933X_PLL_CLK_CTRL_REG(t0)
nop
nop
jr ra
nop
END(lowlevel_init)
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