Dropped becuase - driver and related configs not used any board. - no dm conversion. Cc: Heiko Schocher <hs@denx.de> Cc: Sergey Kostanbaev <sergey.kostanbaev@gmail.com> Signed-off-by: Jagan Teki <jagan@openedev.com>master
Jagan Teki
8 years ago
parent
70c1e0474a
commit
ee86e0d2fe
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/*
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* SPI Driver for EP93xx |
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* |
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* Copyright (C) 2013 Sergey Kostanabev <sergey.kostanbaev <at> fairwaves.ru> |
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* |
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* Inspired form linux kernel driver and atmel uboot driver |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <spi.h> |
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#include <malloc.h> |
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#include <asm/io.h> |
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#include <asm/arch/ep93xx.h> |
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#define SSPBASE SPI_BASE |
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#define SSPCR0 0x0000 |
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#define SSPCR0_MODE_SHIFT 6 |
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#define SSPCR0_SCR_SHIFT 8 |
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#define SSPCR0_SPH BIT(7) |
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#define SSPCR0_SPO BIT(6) |
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#define SSPCR0_FRF_SPI 0 |
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#define SSPCR0_DSS_8BIT 7 |
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#define SSPCR1 0x0004 |
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#define SSPCR1_RIE BIT(0) |
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#define SSPCR1_TIE BIT(1) |
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#define SSPCR1_RORIE BIT(2) |
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#define SSPCR1_LBM BIT(3) |
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#define SSPCR1_SSE BIT(4) |
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#define SSPCR1_MS BIT(5) |
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#define SSPCR1_SOD BIT(6) |
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#define SSPDR 0x0008 |
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#define SSPSR 0x000c |
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#define SSPSR_TFE BIT(0) |
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#define SSPSR_TNF BIT(1) |
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#define SSPSR_RNE BIT(2) |
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#define SSPSR_RFF BIT(3) |
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#define SSPSR_BSY BIT(4) |
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#define SSPCPSR 0x0010 |
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#define SSPIIR 0x0014 |
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#define SSPIIR_RIS BIT(0) |
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#define SSPIIR_TIS BIT(1) |
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#define SSPIIR_RORIS BIT(2) |
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#define SSPICR SSPIIR |
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#define SSPCLOCK 14745600 |
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#define SSP_MAX_RATE (SSPCLOCK / 2) |
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#define SSP_MIN_RATE (SSPCLOCK / (254 * 256)) |
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/* timeout in milliseconds */ |
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#define SPI_TIMEOUT 5 |
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/* maximum depth of RX/TX FIFO */ |
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#define SPI_FIFO_SIZE 8 |
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struct ep93xx_spi_slave { |
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struct spi_slave slave; |
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unsigned sspcr0; |
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unsigned sspcpsr; |
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}; |
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static inline struct ep93xx_spi_slave *to_ep93xx_spi(struct spi_slave *slave) |
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{ |
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return container_of(slave, struct ep93xx_spi_slave, slave); |
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} |
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void spi_init() |
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{ |
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} |
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static inline void ep93xx_spi_write_u8(u16 reg, u8 value) |
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{ |
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writel(value, (unsigned int *)(SSPBASE + reg)); |
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} |
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static inline u8 ep93xx_spi_read_u8(u16 reg) |
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{ |
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return readl((unsigned int *)(SSPBASE + reg)); |
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} |
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static inline void ep93xx_spi_write_u16(u16 reg, u16 value) |
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{ |
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writel(value, (unsigned int *)(SSPBASE + reg)); |
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} |
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static inline u16 ep93xx_spi_read_u16(u16 reg) |
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{ |
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return (u16)readl((unsigned int *)(SSPBASE + reg)); |
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} |
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static int ep93xx_spi_init_hw(unsigned int rate, unsigned int mode, |
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struct ep93xx_spi_slave *slave) |
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{ |
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unsigned cpsr, scr; |
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if (rate > SSP_MAX_RATE) |
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rate = SSP_MAX_RATE; |
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if (rate < SSP_MIN_RATE) |
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return -1; |
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/* Calculate divisors so that we can get speed according the
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* following formula: |
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* rate = spi_clock_rate / (cpsr * (1 + scr)) |
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* |
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* cpsr must be even number and starts from 2, scr can be any number |
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* between 0 and 255. |
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*/ |
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for (cpsr = 2; cpsr <= 254; cpsr += 2) { |
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for (scr = 0; scr <= 255; scr++) { |
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if ((SSPCLOCK / (cpsr * (scr + 1))) <= rate) { |
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/* Set CHPA and CPOL, SPI format and 8bit */ |
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unsigned sspcr0 = (scr << SSPCR0_SCR_SHIFT) | |
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SSPCR0_FRF_SPI | SSPCR0_DSS_8BIT; |
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if (mode & SPI_CPHA) |
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sspcr0 |= SSPCR0_SPH; |
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if (mode & SPI_CPOL) |
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sspcr0 |= SSPCR0_SPO; |
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slave->sspcr0 = sspcr0; |
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slave->sspcpsr = cpsr; |
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return 0; |
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} |
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} |
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} |
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return -1; |
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} |
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void spi_set_speed(struct spi_slave *slave, unsigned int hz) |
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{ |
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struct ep93xx_spi_slave *as = to_ep93xx_spi(slave); |
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unsigned int mode = 0; |
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if (as->sspcr0 & SSPCR0_SPH) |
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mode |= SPI_CPHA; |
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if (as->sspcr0 & SSPCR0_SPO) |
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mode |= SPI_CPOL; |
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ep93xx_spi_init_hw(hz, mode, as); |
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} |
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struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, |
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unsigned int max_hz, unsigned int mode) |
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{ |
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struct ep93xx_spi_slave *as; |
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if (!spi_cs_is_valid(bus, cs)) |
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return NULL; |
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as = spi_alloc_slave(struct ep93xx_spi_slave, bus, cs); |
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if (!as) |
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return NULL; |
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if (ep93xx_spi_init_hw(max_hz, mode, as)) { |
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free(as); |
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return NULL; |
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} |
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return &as->slave; |
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} |
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void spi_free_slave(struct spi_slave *slave) |
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{ |
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struct ep93xx_spi_slave *as = to_ep93xx_spi(slave); |
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free(as); |
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} |
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int spi_claim_bus(struct spi_slave *slave) |
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{ |
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struct ep93xx_spi_slave *as = to_ep93xx_spi(slave); |
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/* Enable the SPI hardware */ |
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ep93xx_spi_write_u8(SSPCR1, SSPCR1_SSE); |
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ep93xx_spi_write_u8(SSPCPSR, as->sspcpsr); |
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ep93xx_spi_write_u16(SSPCR0, as->sspcr0); |
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debug("Select CS:%d SSPCPSR=%02x SSPCR0=%04x\n", |
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slave->cs, as->sspcpsr, as->sspcr0); |
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return 0; |
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} |
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void spi_release_bus(struct spi_slave *slave) |
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{ |
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/* Disable the SPI hardware */ |
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ep93xx_spi_write_u8(SSPCR1, 0); |
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} |
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int spi_xfer(struct spi_slave *slave, unsigned int bitlen, |
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const void *dout, void *din, unsigned long flags) |
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{ |
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unsigned int len_tx; |
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unsigned int len_rx; |
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unsigned int len; |
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u32 status; |
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const u8 *txp = dout; |
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u8 *rxp = din; |
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u8 value; |
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debug("spi_xfer: slave %u:%u dout %p din %p bitlen %u\n", |
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slave->bus, slave->cs, (uint *)dout, (uint *)din, bitlen); |
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if (bitlen == 0) |
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/* Finish any previously submitted transfers */ |
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goto out; |
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if (bitlen % 8) { |
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/* Errors always terminate an ongoing transfer */ |
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flags |= SPI_XFER_END; |
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goto out; |
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} |
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len = bitlen / 8; |
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if (flags & SPI_XFER_BEGIN) { |
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/* Empty RX FIFO */ |
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while ((ep93xx_spi_read_u8(SSPSR) & SSPSR_RNE)) |
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ep93xx_spi_read_u8(SSPDR); |
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spi_cs_activate(slave); |
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} |
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for (len_tx = 0, len_rx = 0; len_rx < len; ) { |
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status = ep93xx_spi_read_u8(SSPSR); |
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if ((len_tx < len) && (status & SSPSR_TNF)) { |
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if (txp) |
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value = *txp++; |
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else |
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value = 0xff; |
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ep93xx_spi_write_u8(SSPDR, value); |
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len_tx++; |
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} |
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if (status & SSPSR_RNE) { |
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value = ep93xx_spi_read_u8(SSPDR); |
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if (rxp) |
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*rxp++ = value; |
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len_rx++; |
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} |
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} |
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out: |
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if (flags & SPI_XFER_END) { |
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/*
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* Wait until the transfer is completely done before |
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* we deactivate CS. |
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*/ |
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do { |
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status = ep93xx_spi_read_u8(SSPSR); |
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} while (status & SSPSR_BSY); |
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spi_cs_deactivate(slave); |
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} |
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return 0; |
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} |
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