Unify and move code in arch/mips/cpu/mips[32|64]/ to arch/mips/cpu/. The CPU specific config.mk files need to remain until CONFIG_STANDALONE_LOAD_ADDR is converted to a global Kconfig symbol. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>master
Daniel Schwierzeck
10 years ago
parent
d9a4a6223c
commit
eef88dfb3e
@ -0,0 +1,9 @@ |
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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extra-y = start.o
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obj-y += time.o
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obj-y += interrupts.o
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obj-y += cpu.o
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@ -1,9 +0,0 @@ |
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#
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# (C) Copyright 2003-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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extra-y = start.o
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obj-y = cpu.o interrupts.o time.o
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@ -1,34 +0,0 @@ |
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/*
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* (C) Copyright 2003 |
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* Wolfgang Denk, DENX Software Engineering, <wd@denx.de> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <command.h> |
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#include <netdev.h> |
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#include <asm/mipsregs.h> |
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#include <asm/reboot.h> |
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void __attribute__((weak)) _machine_restart(void) |
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{ |
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} |
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int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) |
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{ |
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_machine_restart(); |
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fprintf(stderr, "*** reset failed ***\n"); |
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return 0; |
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} |
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void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0, u32 low1) |
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{ |
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write_c0_entrylo0(low0); |
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write_c0_pagemask(pagemask); |
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write_c0_entrylo1(low1); |
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write_c0_entryhi(hi); |
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write_c0_index(index); |
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tlb_write_indexed(); |
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} |
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@ -1,9 +0,0 @@ |
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#
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# (C) Copyright 2003-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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extra-y = start.o
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obj-y = cpu.o interrupts.o time.o
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@ -1,22 +0,0 @@ |
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/*
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* (C) Copyright 2003 |
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* Wolfgang Denk, DENX Software Engineering, <wd@denx.de> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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int interrupt_init(void) |
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{ |
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return 0; |
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} |
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void enable_interrupts(void) |
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{ |
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} |
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int disable_interrupts(void) |
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{ |
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return 0; |
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} |
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@ -1,291 +0,0 @@ |
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/* |
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* Startup Code for MIPS64 CPU-core |
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* |
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* Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <asm-offsets.h> |
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#include <config.h> |
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#include <asm/regdef.h> |
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#include <asm/mipsregs.h> |
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#ifndef CONFIG_SYS_MIPS_CACHE_MODE |
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#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT |
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#endif |
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#ifndef CONFIG_SYS_INIT_SP_ADDR |
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#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \ |
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CONFIG_SYS_INIT_SP_OFFSET) |
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#endif |
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#ifdef CONFIG_SYS_LITTLE_ENDIAN |
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#define MIPS64_R_INFO(ssym, r_type3, r_type2, r_type) \ |
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(((r_type) << 24) | ((r_type2) << 16) | ((r_type3) << 8) | (ssym)) |
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#else |
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#define MIPS64_R_INFO(ssym, r_type3, r_type2, r_type) \ |
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((r_type) | ((r_type2) << 8) | ((r_type3) << 16) | (ssym) << 24) |
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#endif |
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/* |
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* For the moment disable interrupts, mark the kernel mode and |
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* set ST0_KX so that the CPU does not spit fire when using |
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* 64-bit addresses. |
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*/ |
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.macro setup_c0_status set clr |
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.set push
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mfc0 t0, CP0_STATUS |
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or t0, ST0_CU0 | \set | 0x1f | \clr |
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xor t0, 0x1f | \clr |
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mtc0 t0, CP0_STATUS |
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.set noreorder
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sll zero, 3 # ehb |
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.set pop
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.endm |
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.set noreorder
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.globl _start
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.text |
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_start: |
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/* U-boot entry point */ |
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b reset |
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nop |
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.org 0x200
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/* TLB refill, 32 bit task */ |
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1: b 1b |
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nop |
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.org 0x280
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/* XTLB refill, 64 bit task */ |
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1: b 1b |
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nop |
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.org 0x300
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/* Cache error exception */ |
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1: b 1b |
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nop |
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.org 0x380
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/* General exception */ |
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1: b 1b |
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nop |
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.org 0x400
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/* Catch interrupt exceptions */ |
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1: b 1b |
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nop |
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.org 0x480
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/* EJTAG debug exception */ |
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1: b 1b |
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nop |
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.align 4
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reset: |
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/* Clear watch registers */ |
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dmtc0 zero, CP0_WATCHLO |
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dmtc0 zero, CP0_WATCHHI |
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/* WP(Watch Pending), SW0/1 should be cleared */ |
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mtc0 zero, CP0_CAUSE |
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setup_c0_status ST0_KX 0 |
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/* Init Timer */ |
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mtc0 zero, CP0_COUNT |
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mtc0 zero, CP0_COMPARE |
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#ifndef CONFIG_SKIP_LOWLEVEL_INIT |
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/* CONFIG0 register */ |
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dli t0, CONF_CM_UNCACHED |
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mtc0 t0, CP0_CONFIG |
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#endif |
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/* |
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* Initialize $gp, force 8 byte alignment of bal instruction to forbid |
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* the compiler to put nop's between bal and _gp. This is required to |
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* keep _gp and ra aligned to 8 byte. |
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*/ |
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.align 3
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bal 1f |
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nop |
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.dword _gp
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1: |
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ld gp, 0(ra) |
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#ifndef CONFIG_SKIP_LOWLEVEL_INIT |
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/* Initialize any external memory */ |
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dla t9, lowlevel_init |
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jalr t9 |
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nop |
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/* Initialize caches... */ |
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dla t9, mips_cache_reset |
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jalr t9 |
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nop |
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/* ... and enable them */ |
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dli t0, CONFIG_SYS_MIPS_CACHE_MODE |
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mtc0 t0, CP0_CONFIG |
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#endif |
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/* Set up temporary stack */ |
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dli t0, -16 |
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dli t1, CONFIG_SYS_INIT_SP_ADDR |
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and sp, t1, t0 # force 16 byte alignment |
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dsub sp, sp, GD_SIZE # reserve space for gd |
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and sp, sp, t0 # force 16 byte alignment |
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move k0, sp # save gd pointer |
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#ifdef CONFIG_SYS_MALLOC_F_LEN |
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dli t2, CONFIG_SYS_MALLOC_F_LEN |
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dsub sp, sp, t2 # reserve space for early malloc |
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and sp, sp, t0 # force 16 byte alignment |
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#endif |
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move fp, sp |
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/* Clear gd */ |
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move t0, k0 |
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1: |
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sw zero, 0(t0) |
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blt t0, t1, 1b |
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daddi t0, 4 |
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#ifdef CONFIG_SYS_MALLOC_F_LEN |
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daddu t0, k0, GD_MALLOC_BASE # gd->malloc_base offset |
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sw sp, 0(t0) |
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#endif |
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dla t9, board_init_f |
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jr t9 |
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move ra, zero |
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/* |
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* void relocate_code (addr_sp, gd, addr_moni) |
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* |
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* This "function" does not return, instead it continues in RAM |
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* after relocating the monitor code. |
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* |
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* a0 = addr_sp |
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* a1 = gd |
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* a2 = destination address |
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*/ |
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.globl relocate_code
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.ent relocate_code
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relocate_code: |
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move sp, a0 # set new stack pointer |
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move fp, sp |
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move s0, a1 # save gd in s0 |
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move s2, a2 # save destination address in s2 |
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dli t0, CONFIG_SYS_MONITOR_BASE |
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dsub s1, s2, t0 # s1 <-- relocation offset |
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dla t3, in_ram |
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ld t2, -24(t3) # t2 <-- __image_copy_end |
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move t1, a2 |
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dadd gp, s1 # adjust gp |
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/* |
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* t0 = source address |
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* t1 = target address |
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* t2 = source end address |
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*/ |
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1: |
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lw t3, 0(t0) |
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sw t3, 0(t1) |
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daddu t0, 4 |
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blt t0, t2, 1b |
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daddu t1, 4 |
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/* If caches were enabled, we would have to flush them here. */ |
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dsub a1, t1, s2 # a1 <-- size |
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dla t9, flush_cache |
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jalr t9 |
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move a0, s2 # a0 <-- destination address |
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/* Jump to where we've relocated ourselves */ |
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daddi t0, s2, in_ram - _start |
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jr t0 |
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nop |
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.dword __rel_dyn_end
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.dword __rel_dyn_start
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.dword __image_copy_end
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.dword _GLOBAL_OFFSET_TABLE_
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.dword num_got_entries
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in_ram: |
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/* |
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* Now we want to update GOT. |
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* |
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* GOT[0] is reserved. GOT[1] is also reserved for the dynamic object |
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* generated by GNU ld. Skip these reserved entries from relocation. |
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*/ |
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ld t3, -8(t0) # t3 <-- num_got_entries |
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ld t8, -16(t0) # t8 <-- _GLOBAL_OFFSET_TABLE_ |
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dadd t8, s1 # t8 now holds relocated _G_O_T_ |
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daddi t8, t8, 16 # skipping first two entries |
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dli t2, 2 |
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1: |
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ld t1, 0(t8) |
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beqz t1, 2f |
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dadd t1, s1 |
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sd t1, 0(t8) |
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2: |
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daddi t2, 1 |
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blt t2, t3, 1b |
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daddi t8, 8 |
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/* Update dynamic relocations */ |
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ld t1, -32(t0) # t1 <-- __rel_dyn_start |
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ld t2, -40(t0) # t2 <-- __rel_dyn_end |
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b 2f # skip first reserved entry |
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daddi t1, 16 |
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1: |
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lw t8, -4(t1) # t8 <-- relocation info |
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dli t3, MIPS64_R_INFO(0x00, 0x00, 0x12, 0x03) |
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bne t8, t3, 2f # skip non R_MIPS_REL32 entries |
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nop |
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ld t3, -16(t1) # t3 <-- location to fix up in FLASH |
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ld t8, 0(t3) # t8 <-- original pointer |
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dadd t8, s1 # t8 <-- adjusted pointer |
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dadd t3, s1 # t3 <-- location to fix up in RAM |
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sd t8, 0(t3) |
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2: |
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blt t1, t2, 1b |
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daddi t1, 16 # each rel.dyn entry is 16 bytes |
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/* |
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* Clear BSS |
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* |
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* GOT is now relocated. Thus __bss_start and __bss_end can be |
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* accessed directly via $gp. |
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*/ |
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dla t1, __bss_start # t1 <-- __bss_start |
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dla t2, __bss_end # t2 <-- __bss_end |
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1: |
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sd zero, 0(t1) |
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blt t1, t2, 1b |
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daddi t1, 8 |
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move a0, s0 # a0 <-- gd |
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move a1, s2 |
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dla t9, board_init_r |
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jr t9 |
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move ra, zero |
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.end relocate_code
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@ -1,19 +0,0 @@ |
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/*
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* (C) Copyright 2003 |
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <asm/mipsregs.h> |
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unsigned long notrace timer_read_counter(void) |
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{ |
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return read_c0_count(); |
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} |
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ulong notrace get_tbclk(void) |
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{ |
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return CONFIG_SYS_MIPS_TIMER_FREQ; |
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} |
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