Intel's Graphics Media Accelerator (GMA) is a generic name for a wide range of video devices. Add code to set up the hardware on ivybridge. Part of the init happens in native code, part of it happens in a 16-bit option ROM for those nostalgic for the 1970s. Signed-off-by: Simon Glass <sjg@chromium.org>master
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/*
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* From Coreboot file of the same name |
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* |
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* Copyright (C) 2011 Chromium OS Authors |
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* |
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* SPDX-License-Identifier: GPL-2.0 |
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*/ |
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#include <common.h> |
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#include <bios_emul.h> |
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#include <errno.h> |
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#include <fdtdec.h> |
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#include <pci_rom.h> |
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#include <asm/io.h> |
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#include <asm/pci.h> |
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#include <asm/arch/pch.h> |
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#include <asm/arch/sandybridge.h> |
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struct gt_powermeter { |
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u16 reg; |
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u32 value; |
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}; |
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static const struct gt_powermeter snb_pm_gt1[] = { |
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{ 0xa200, 0xcc000000 }, |
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{ 0xa204, 0x07000040 }, |
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{ 0xa208, 0x0000fe00 }, |
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{ 0xa20c, 0x00000000 }, |
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{ 0xa210, 0x17000000 }, |
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{ 0xa214, 0x00000021 }, |
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{ 0xa218, 0x0817fe19 }, |
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{ 0xa21c, 0x00000000 }, |
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{ 0xa220, 0x00000000 }, |
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{ 0xa224, 0xcc000000 }, |
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{ 0xa228, 0x07000040 }, |
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{ 0xa22c, 0x0000fe00 }, |
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{ 0xa230, 0x00000000 }, |
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{ 0xa234, 0x17000000 }, |
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{ 0xa238, 0x00000021 }, |
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{ 0xa23c, 0x0817fe19 }, |
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{ 0xa240, 0x00000000 }, |
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{ 0xa244, 0x00000000 }, |
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{ 0xa248, 0x8000421e }, |
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{ 0 } |
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}; |
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static const struct gt_powermeter snb_pm_gt2[] = { |
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{ 0xa200, 0x330000a6 }, |
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{ 0xa204, 0x402d0031 }, |
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{ 0xa208, 0x00165f83 }, |
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{ 0xa20c, 0xf1000000 }, |
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{ 0xa210, 0x00000000 }, |
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{ 0xa214, 0x00160016 }, |
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{ 0xa218, 0x002a002b }, |
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{ 0xa21c, 0x00000000 }, |
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{ 0xa220, 0x00000000 }, |
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{ 0xa224, 0x330000a6 }, |
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{ 0xa228, 0x402d0031 }, |
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{ 0xa22c, 0x00165f83 }, |
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{ 0xa230, 0xf1000000 }, |
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{ 0xa234, 0x00000000 }, |
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{ 0xa238, 0x00160016 }, |
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{ 0xa23c, 0x002a002b }, |
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{ 0xa240, 0x00000000 }, |
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{ 0xa244, 0x00000000 }, |
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{ 0xa248, 0x8000421e }, |
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{ 0 } |
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}; |
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static const struct gt_powermeter ivb_pm_gt1[] = { |
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{ 0xa800, 0x00000000 }, |
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{ 0xa804, 0x00021c00 }, |
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{ 0xa808, 0x00000403 }, |
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{ 0xa80c, 0x02001700 }, |
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{ 0xa810, 0x05000200 }, |
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{ 0xa814, 0x00000000 }, |
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{ 0xa818, 0x00690500 }, |
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{ 0xa81c, 0x0000007f }, |
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{ 0xa820, 0x01002501 }, |
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{ 0xa824, 0x00000300 }, |
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{ 0xa828, 0x01000331 }, |
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{ 0xa82c, 0x0000000c }, |
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{ 0xa830, 0x00010016 }, |
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{ 0xa834, 0x01100101 }, |
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{ 0xa838, 0x00010103 }, |
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{ 0xa83c, 0x00041300 }, |
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{ 0xa840, 0x00000b30 }, |
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{ 0xa844, 0x00000000 }, |
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{ 0xa848, 0x7f000000 }, |
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{ 0xa84c, 0x05000008 }, |
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{ 0xa850, 0x00000001 }, |
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{ 0xa854, 0x00000004 }, |
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{ 0xa858, 0x00000007 }, |
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{ 0xa85c, 0x00000000 }, |
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{ 0xa860, 0x00010000 }, |
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{ 0xa248, 0x0000221e }, |
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{ 0xa900, 0x00000000 }, |
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{ 0xa904, 0x00001c00 }, |
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{ 0xa908, 0x00000000 }, |
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{ 0xa90c, 0x06000000 }, |
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{ 0xa910, 0x09000200 }, |
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{ 0xa914, 0x00000000 }, |
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{ 0xa918, 0x00590000 }, |
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{ 0xa91c, 0x00000000 }, |
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{ 0xa920, 0x04002501 }, |
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{ 0xa924, 0x00000100 }, |
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{ 0xa928, 0x03000410 }, |
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{ 0xa92c, 0x00000000 }, |
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{ 0xa930, 0x00020000 }, |
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{ 0xa934, 0x02070106 }, |
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{ 0xa938, 0x00010100 }, |
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{ 0xa93c, 0x00401c00 }, |
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{ 0xa940, 0x00000000 }, |
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{ 0xa944, 0x00000000 }, |
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{ 0xa948, 0x10000e00 }, |
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{ 0xa94c, 0x02000004 }, |
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{ 0xa950, 0x00000001 }, |
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{ 0xa954, 0x00000004 }, |
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{ 0xa960, 0x00060000 }, |
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{ 0xaa3c, 0x00001c00 }, |
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{ 0xaa54, 0x00000004 }, |
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{ 0xaa60, 0x00060000 }, |
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{ 0 } |
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}; |
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static const struct gt_powermeter ivb_pm_gt2[] = { |
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{ 0xa800, 0x10000000 }, |
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{ 0xa804, 0x00033800 }, |
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{ 0xa808, 0x00000902 }, |
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{ 0xa80c, 0x0c002f00 }, |
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{ 0xa810, 0x12000400 }, |
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{ 0xa814, 0x00000000 }, |
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{ 0xa818, 0x00d20800 }, |
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{ 0xa81c, 0x00000002 }, |
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{ 0xa820, 0x03004b02 }, |
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{ 0xa824, 0x00000600 }, |
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{ 0xa828, 0x07000773 }, |
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{ 0xa82c, 0x00000000 }, |
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{ 0xa830, 0x00010032 }, |
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{ 0xa834, 0x1520040d }, |
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{ 0xa838, 0x00020105 }, |
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{ 0xa83c, 0x00083700 }, |
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{ 0xa840, 0x0000151d }, |
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{ 0xa844, 0x00000000 }, |
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{ 0xa848, 0x20001b00 }, |
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{ 0xa84c, 0x0a000010 }, |
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{ 0xa850, 0x00000000 }, |
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{ 0xa854, 0x00000008 }, |
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{ 0xa858, 0x00000008 }, |
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{ 0xa85c, 0x00000000 }, |
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{ 0xa860, 0x00020000 }, |
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{ 0xa248, 0x0000221e }, |
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{ 0xa900, 0x00000000 }, |
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{ 0xa904, 0x00003500 }, |
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{ 0xa908, 0x00000000 }, |
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{ 0xa90c, 0x0c000000 }, |
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{ 0xa910, 0x12000500 }, |
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{ 0xa914, 0x00000000 }, |
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{ 0xa918, 0x00b20000 }, |
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{ 0xa91c, 0x00000000 }, |
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{ 0xa920, 0x08004b02 }, |
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{ 0xa924, 0x00000200 }, |
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{ 0xa928, 0x07000820 }, |
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{ 0xa92c, 0x00000000 }, |
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{ 0xa930, 0x00030000 }, |
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{ 0xa934, 0x050f020d }, |
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{ 0xa938, 0x00020300 }, |
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{ 0xa93c, 0x00903900 }, |
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{ 0xa940, 0x00000000 }, |
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{ 0xa944, 0x00000000 }, |
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{ 0xa948, 0x20001b00 }, |
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{ 0xa94c, 0x0a000010 }, |
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{ 0xa950, 0x00000000 }, |
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{ 0xa954, 0x00000008 }, |
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{ 0xa960, 0x00110000 }, |
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{ 0xaa3c, 0x00003900 }, |
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{ 0xaa54, 0x00000008 }, |
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{ 0xaa60, 0x00110000 }, |
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{ 0 } |
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}; |
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static const struct gt_powermeter ivb_pm_gt2_17w[] = { |
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{ 0xa800, 0x20000000 }, |
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{ 0xa804, 0x000e3800 }, |
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{ 0xa808, 0x00000806 }, |
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{ 0xa80c, 0x0c002f00 }, |
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{ 0xa810, 0x0c000800 }, |
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{ 0xa814, 0x00000000 }, |
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{ 0xa818, 0x00d20d00 }, |
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{ 0xa81c, 0x000000ff }, |
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{ 0xa820, 0x03004b02 }, |
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{ 0xa824, 0x00000600 }, |
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{ 0xa828, 0x07000773 }, |
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{ 0xa82c, 0x00000000 }, |
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{ 0xa830, 0x00020032 }, |
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{ 0xa834, 0x1520040d }, |
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{ 0xa838, 0x00020105 }, |
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{ 0xa83c, 0x00083700 }, |
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{ 0xa840, 0x000016ff }, |
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{ 0xa844, 0x00000000 }, |
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{ 0xa848, 0xff000000 }, |
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{ 0xa84c, 0x0a000010 }, |
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{ 0xa850, 0x00000002 }, |
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{ 0xa854, 0x00000008 }, |
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{ 0xa858, 0x0000000f }, |
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{ 0xa85c, 0x00000000 }, |
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{ 0xa860, 0x00020000 }, |
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{ 0xa248, 0x0000221e }, |
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{ 0xa900, 0x00000000 }, |
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{ 0xa904, 0x00003800 }, |
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{ 0xa908, 0x00000000 }, |
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{ 0xa90c, 0x0c000000 }, |
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{ 0xa910, 0x12000800 }, |
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{ 0xa914, 0x00000000 }, |
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{ 0xa918, 0x00b20000 }, |
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{ 0xa91c, 0x00000000 }, |
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{ 0xa920, 0x08004b02 }, |
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{ 0xa924, 0x00000300 }, |
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{ 0xa928, 0x01000820 }, |
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{ 0xa92c, 0x00000000 }, |
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{ 0xa930, 0x00030000 }, |
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{ 0xa934, 0x15150406 }, |
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{ 0xa938, 0x00020300 }, |
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{ 0xa93c, 0x00903900 }, |
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{ 0xa940, 0x00000000 }, |
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{ 0xa944, 0x00000000 }, |
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{ 0xa948, 0x20001b00 }, |
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{ 0xa94c, 0x0a000010 }, |
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{ 0xa950, 0x00000000 }, |
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{ 0xa954, 0x00000008 }, |
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{ 0xa960, 0x00110000 }, |
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{ 0xaa3c, 0x00003900 }, |
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{ 0xaa54, 0x00000008 }, |
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{ 0xaa60, 0x00110000 }, |
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{ 0 } |
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}; |
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static const struct gt_powermeter ivb_pm_gt2_35w[] = { |
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{ 0xa800, 0x00000000 }, |
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{ 0xa804, 0x00030400 }, |
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{ 0xa808, 0x00000806 }, |
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{ 0xa80c, 0x0c002f00 }, |
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{ 0xa810, 0x0c000300 }, |
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{ 0xa814, 0x00000000 }, |
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{ 0xa818, 0x00d20d00 }, |
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{ 0xa81c, 0x000000ff }, |
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{ 0xa820, 0x03004b02 }, |
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{ 0xa824, 0x00000600 }, |
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{ 0xa828, 0x07000773 }, |
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{ 0xa82c, 0x00000000 }, |
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{ 0xa830, 0x00020032 }, |
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{ 0xa834, 0x1520040d }, |
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{ 0xa838, 0x00020105 }, |
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{ 0xa83c, 0x00083700 }, |
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{ 0xa840, 0x000016ff }, |
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{ 0xa844, 0x00000000 }, |
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{ 0xa848, 0xff000000 }, |
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{ 0xa84c, 0x0a000010 }, |
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{ 0xa850, 0x00000001 }, |
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{ 0xa854, 0x00000008 }, |
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{ 0xa858, 0x00000008 }, |
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{ 0xa85c, 0x00000000 }, |
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{ 0xa860, 0x00020000 }, |
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{ 0xa248, 0x0000221e }, |
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{ 0xa900, 0x00000000 }, |
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{ 0xa904, 0x00003800 }, |
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{ 0xa908, 0x00000000 }, |
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{ 0xa90c, 0x0c000000 }, |
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{ 0xa910, 0x12000800 }, |
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{ 0xa914, 0x00000000 }, |
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{ 0xa918, 0x00b20000 }, |
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{ 0xa91c, 0x00000000 }, |
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{ 0xa920, 0x08004b02 }, |
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{ 0xa924, 0x00000300 }, |
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{ 0xa928, 0x01000820 }, |
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{ 0xa92c, 0x00000000 }, |
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{ 0xa930, 0x00030000 }, |
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{ 0xa934, 0x15150406 }, |
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{ 0xa938, 0x00020300 }, |
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{ 0xa93c, 0x00903900 }, |
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{ 0xa940, 0x00000000 }, |
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{ 0xa944, 0x00000000 }, |
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{ 0xa948, 0x20001b00 }, |
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{ 0xa94c, 0x0a000010 }, |
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{ 0xa950, 0x00000000 }, |
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{ 0xa954, 0x00000008 }, |
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{ 0xa960, 0x00110000 }, |
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{ 0xaa3c, 0x00003900 }, |
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{ 0xaa54, 0x00000008 }, |
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{ 0xaa60, 0x00110000 }, |
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{ 0 } |
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}; |
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/*
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* Some vga option roms are used for several chipsets but they only have one |
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* PCI ID in their header. If we encounter such an option rom, we need to do |
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* the mapping ourselves. |
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*/ |
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u32 map_oprom_vendev(u32 vendev) |
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{ |
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u32 new_vendev = vendev; |
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switch (vendev) { |
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case 0x80860102: /* GT1 Desktop */ |
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case 0x8086010a: /* GT1 Server */ |
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case 0x80860112: /* GT2 Desktop */ |
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case 0x80860116: /* GT2 Mobile */ |
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case 0x80860122: /* GT2 Desktop >=1.3GHz */ |
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case 0x80860126: /* GT2 Mobile >=1.3GHz */ |
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case 0x80860156: /* IVB */ |
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case 0x80860166: /* IVB */ |
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/* Set to GT1 Mobile */ |
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new_vendev = 0x80860106; |
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break; |
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} |
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return new_vendev; |
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} |
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static inline u32 gtt_read(void *bar, u32 reg) |
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{ |
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return readl(bar + reg); |
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} |
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static inline void gtt_write(void *bar, u32 reg, u32 data) |
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{ |
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writel(data, bar + reg); |
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} |
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static void gtt_write_powermeter(void *bar, const struct gt_powermeter *pm) |
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{ |
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for (; pm && pm->reg; pm++) |
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gtt_write(bar, pm->reg, pm->value); |
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} |
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#define GTT_RETRY 1000 |
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static int gtt_poll(void *bar, u32 reg, u32 mask, u32 value) |
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{ |
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unsigned try = GTT_RETRY; |
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u32 data; |
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while (try--) { |
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data = gtt_read(bar, reg); |
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if ((data & mask) == value) |
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return 1; |
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udelay(10); |
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} |
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printf("GT init timeout\n"); |
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return 0; |
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} |
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static int gma_pm_init_pre_vbios(void *gtt_bar) |
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{ |
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u32 reg32; |
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debug("GT Power Management Init, silicon = %#x\n", |
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bridge_silicon_revision()); |
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if (bridge_silicon_revision() < IVB_STEP_C0) { |
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/* 1: Enable force wake */ |
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gtt_write(gtt_bar, 0xa18c, 0x00000001); |
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gtt_poll(gtt_bar, 0x130090, (1 << 0), (1 << 0)); |
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} else { |
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gtt_write(gtt_bar, 0xa180, 1 << 5); |
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gtt_write(gtt_bar, 0xa188, 0xffff0001); |
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gtt_poll(gtt_bar, 0x130040, (1 << 0), (1 << 0)); |
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} |
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if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) { |
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/* 1d: Set GTT+0x42004 [15:14]=11 (SnB C1+) */ |
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reg32 = gtt_read(gtt_bar, 0x42004); |
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reg32 |= (1 << 14) | (1 << 15); |
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gtt_write(gtt_bar, 0x42004, reg32); |
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} |
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if (bridge_silicon_revision() >= IVB_STEP_A0) { |
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/* Display Reset Acknowledge Settings */ |
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reg32 = gtt_read(gtt_bar, 0x45010); |
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reg32 |= (1 << 1) | (1 << 0); |
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gtt_write(gtt_bar, 0x45010, reg32); |
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} |
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/* 2: Get GT SKU from GTT+0x911c[13] */ |
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reg32 = gtt_read(gtt_bar, 0x911c); |
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if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) { |
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if (reg32 & (1 << 13)) { |
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debug("SNB GT1 Power Meter Weights\n"); |
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gtt_write_powermeter(gtt_bar, snb_pm_gt1); |
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} else { |
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debug("SNB GT2 Power Meter Weights\n"); |
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gtt_write_powermeter(gtt_bar, snb_pm_gt2); |
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} |
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} else { |
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u32 unit = readl(MCHBAR_REG(0x5938)) & 0xf; |
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if (reg32 & (1 << 13)) { |
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/* GT1 SKU */ |
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debug("IVB GT1 Power Meter Weights\n"); |
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gtt_write_powermeter(gtt_bar, ivb_pm_gt1); |
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} else { |
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/* GT2 SKU */ |
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u32 tdp = readl(MCHBAR_REG(0x5930)) & 0x7fff; |
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tdp /= (1 << unit); |
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if (tdp <= 17) { |
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/* <=17W ULV */ |
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debug("IVB GT2 17W Power Meter Weights\n"); |
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gtt_write_powermeter(gtt_bar, ivb_pm_gt2_17w); |
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} else if ((tdp >= 25) && (tdp <= 35)) { |
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/* 25W-35W */ |
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debug("IVB GT2 25W-35W Power Meter Weights\n"); |
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gtt_write_powermeter(gtt_bar, ivb_pm_gt2_35w); |
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} else { |
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/* All others */ |
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debug("IVB GT2 35W Power Meter Weights\n"); |
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gtt_write_powermeter(gtt_bar, ivb_pm_gt2_35w); |
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} |
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} |
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} |
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/* 3: Gear ratio map */ |
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gtt_write(gtt_bar, 0xa004, 0x00000010); |
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/* 4: GFXPAUSE */ |
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gtt_write(gtt_bar, 0xa000, 0x00070020); |
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/* 5: Dynamic EU trip control */ |
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gtt_write(gtt_bar, 0xa080, 0x00000004); |
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/* 6: ECO bits */ |
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reg32 = gtt_read(gtt_bar, 0xa180); |
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reg32 |= (1 << 26) | (1 << 31); |
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/* (bit 20=1 for SNB step D1+ / IVB A0+) */ |
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if (bridge_silicon_revision() >= SNB_STEP_D1) |
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reg32 |= (1 << 20); |
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gtt_write(gtt_bar, 0xa180, reg32); |
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/* 6a: for SnB step D2+ only */ |
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if (((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) && |
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(bridge_silicon_revision() >= SNB_STEP_D2)) { |
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reg32 = gtt_read(gtt_bar, 0x9400); |
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reg32 |= (1 << 7); |
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gtt_write(gtt_bar, 0x9400, reg32); |
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reg32 = gtt_read(gtt_bar, 0x941c); |
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reg32 &= 0xf; |
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reg32 |= (1 << 1); |
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gtt_write(gtt_bar, 0x941c, reg32); |
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gtt_poll(gtt_bar, 0x941c, (1 << 1), (0 << 1)); |
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} |
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if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_IVB) { |
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reg32 = gtt_read(gtt_bar, 0x907c); |
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reg32 |= (1 << 16); |
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gtt_write(gtt_bar, 0x907c, reg32); |
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/* 6b: Clocking reset controls */ |
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gtt_write(gtt_bar, 0x9424, 0x00000001); |
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} else { |
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/* 6b: Clocking reset controls */ |
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gtt_write(gtt_bar, 0x9424, 0x00000000); |
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} |
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/* 7 */ |
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if (gtt_poll(gtt_bar, 0x138124, (1 << 31), (0 << 31))) { |
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gtt_write(gtt_bar, 0x138128, 0x00000029); /* Mailbox Data */ |
||||
/* Mailbox Cmd for RC6 VID */ |
||||
gtt_write(gtt_bar, 0x138124, 0x80000004); |
||||
if (gtt_poll(gtt_bar, 0x138124, (1 << 31), (0 << 31))) |
||||
gtt_write(gtt_bar, 0x138124, 0x8000000a); |
||||
gtt_poll(gtt_bar, 0x138124, (1 << 31), (0 << 31)); |
||||
} |
||||
|
||||
/* 8 */ |
||||
gtt_write(gtt_bar, 0xa090, 0x00000000); /* RC Control */ |
||||
gtt_write(gtt_bar, 0xa098, 0x03e80000); /* RC1e Wake Rate Limit */ |
||||
gtt_write(gtt_bar, 0xa09c, 0x0028001e); /* RC6/6p Wake Rate Limit */ |
||||
gtt_write(gtt_bar, 0xa0a0, 0x0000001e); /* RC6pp Wake Rate Limit */ |
||||
gtt_write(gtt_bar, 0xa0a8, 0x0001e848); /* RC Evaluation Interval */ |
||||
gtt_write(gtt_bar, 0xa0ac, 0x00000019); /* RC Idle Hysteresis */ |
||||
|
||||
/* 9 */ |
||||
gtt_write(gtt_bar, 0x2054, 0x0000000a); /* Render Idle Max Count */ |
||||
gtt_write(gtt_bar, 0x12054, 0x0000000a); /* Video Idle Max Count */ |
||||
gtt_write(gtt_bar, 0x22054, 0x0000000a); /* Blitter Idle Max Count */ |
||||
|
||||
/* 10 */ |
||||
gtt_write(gtt_bar, 0xa0b0, 0x00000000); /* Unblock Ack to Busy */ |
||||
gtt_write(gtt_bar, 0xa0b4, 0x000003e8); /* RC1e Threshold */ |
||||
gtt_write(gtt_bar, 0xa0b8, 0x0000c350); /* RC6 Threshold */ |
||||
gtt_write(gtt_bar, 0xa0bc, 0x000186a0); /* RC6p Threshold */ |
||||
gtt_write(gtt_bar, 0xa0c0, 0x0000fa00); /* RC6pp Threshold */ |
||||
|
||||
/* 11 */ |
||||
gtt_write(gtt_bar, 0xa010, 0x000f4240); /* RP Down Timeout */ |
||||
gtt_write(gtt_bar, 0xa014, 0x12060000); /* RP Interrupt Limits */ |
||||
gtt_write(gtt_bar, 0xa02c, 0x00015f90); /* RP Up Threshold */ |
||||
gtt_write(gtt_bar, 0xa030, 0x000186a0); /* RP Down Threshold */ |
||||
gtt_write(gtt_bar, 0xa068, 0x000186a0); /* RP Up EI */ |
||||
gtt_write(gtt_bar, 0xa06c, 0x000493e0); /* RP Down EI */ |
||||
gtt_write(gtt_bar, 0xa070, 0x0000000a); /* RP Idle Hysteresis */ |
||||
|
||||
/* 11a: Enable Render Standby (RC6) */ |
||||
if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_IVB) { |
||||
/*
|
||||
* IvyBridge should also support DeepRenderStandby. |
||||
* |
||||
* Unfortunately it does not work reliably on all SKUs so |
||||
* disable it here and it can be enabled by the kernel. |
||||
*/ |
||||
gtt_write(gtt_bar, 0xa090, 0x88040000); /* HW RC Control */ |
||||
} else { |
||||
gtt_write(gtt_bar, 0xa090, 0x88040000); /* HW RC Control */ |
||||
} |
||||
|
||||
/* 12: Normal Frequency Request */ |
||||
/* RPNFREQ_VAL comes from MCHBAR 0x5998 23:16 (8 bits!? use 7) */ |
||||
reg32 = readl(MCHBAR_REG(0x5998)); |
||||
reg32 >>= 16; |
||||
reg32 &= 0xef; |
||||
reg32 <<= 25; |
||||
gtt_write(gtt_bar, 0xa008, reg32); |
||||
|
||||
/* 13: RP Control */ |
||||
gtt_write(gtt_bar, 0xa024, 0x00000592); |
||||
|
||||
/* 14: Enable PM Interrupts */ |
||||
gtt_write(gtt_bar, 0x4402c, 0x03000076); |
||||
|
||||
/* Clear 0x6c024 [8:6] */ |
||||
reg32 = gtt_read(gtt_bar, 0x6c024); |
||||
reg32 &= ~0x000001c0; |
||||
gtt_write(gtt_bar, 0x6c024, reg32); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int gma_pm_init_post_vbios(void *gtt_bar, const void *blob, int node) |
||||
{ |
||||
u32 reg32, cycle_delay; |
||||
|
||||
debug("GT Power Management Init (post VBIOS)\n"); |
||||
|
||||
/* 15: Deassert Force Wake */ |
||||
if (bridge_silicon_revision() < IVB_STEP_C0) { |
||||
gtt_write(gtt_bar, 0xa18c, gtt_read(gtt_bar, 0xa18c) & ~1); |
||||
gtt_poll(gtt_bar, 0x130090, (1 << 0), (0 << 0)); |
||||
} else { |
||||
gtt_write(gtt_bar, 0xa188, 0x1fffe); |
||||
if (gtt_poll(gtt_bar, 0x130040, (1 << 0), (0 << 0))) { |
||||
gtt_write(gtt_bar, 0xa188, |
||||
gtt_read(gtt_bar, 0xa188) | 1); |
||||
} |
||||
} |
||||
|
||||
/* 16: SW RC Control */ |
||||
gtt_write(gtt_bar, 0xa094, 0x00060000); |
||||
|
||||
/* Setup Digital Port Hotplug */ |
||||
reg32 = gtt_read(gtt_bar, 0xc4030); |
||||
if (!reg32) { |
||||
u32 dp_hotplug[3]; |
||||
|
||||
if (fdtdec_get_int_array(blob, node, "intel,dp_hotplug", |
||||
dp_hotplug, ARRAY_SIZE(dp_hotplug))) |
||||
return -EINVAL; |
||||
|
||||
reg32 = (dp_hotplug[0] & 0x7) << 2; |
||||
reg32 |= (dp_hotplug[0] & 0x7) << 10; |
||||
reg32 |= (dp_hotplug[0] & 0x7) << 18; |
||||
gtt_write(gtt_bar, 0xc4030, reg32); |
||||
} |
||||
|
||||
/* Setup Panel Power On Delays */ |
||||
reg32 = gtt_read(gtt_bar, 0xc7208); |
||||
if (!reg32) { |
||||
reg32 = (unsigned)fdtdec_get_int(blob, node, |
||||
"panel-port-select", 0) << 30; |
||||
reg32 |= fdtdec_get_int(blob, node, "panel-power-up-delay", 0) |
||||
<< 16; |
||||
reg32 |= fdtdec_get_int(blob, node, |
||||
"panel-power-backlight-on-delay", 0); |
||||
gtt_write(gtt_bar, 0xc7208, reg32); |
||||
} |
||||
|
||||
/* Setup Panel Power Off Delays */ |
||||
reg32 = gtt_read(gtt_bar, 0xc720c); |
||||
if (!reg32) { |
||||
reg32 = fdtdec_get_int(blob, node, "panel-power-down-delay", 0) |
||||
<< 16; |
||||
reg32 |= fdtdec_get_int(blob, node, |
||||
"panel-power-backlight-off-delay", 0); |
||||
gtt_write(gtt_bar, 0xc720c, reg32); |
||||
} |
||||
|
||||
/* Setup Panel Power Cycle Delay */ |
||||
cycle_delay = fdtdec_get_int(blob, node, |
||||
"intel,panel-power-cycle-delay", 0); |
||||
if (cycle_delay) { |
||||
reg32 = gtt_read(gtt_bar, 0xc7210); |
||||
reg32 &= ~0xff; |
||||
reg32 |= cycle_delay; |
||||
gtt_write(gtt_bar, 0xc7210, reg32); |
||||
} |
||||
|
||||
/* Enable Backlight if needed */ |
||||
reg32 = fdtdec_get_int(blob, node, "intel,cpu-backlight", 0); |
||||
if (reg32) { |
||||
gtt_write(gtt_bar, 0x48250, (1 << 31)); |
||||
gtt_write(gtt_bar, 0x48254, reg32); |
||||
} |
||||
reg32 = fdtdec_get_int(blob, node, "intel,pch-backlight", 0); |
||||
if (reg32) { |
||||
gtt_write(gtt_bar, 0xc8250, (1 << 31)); |
||||
gtt_write(gtt_bar, 0xc8254, reg32); |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
/*
|
||||
* Some vga option roms are used for several chipsets but they only have one |
||||
* PCI ID in their header. If we encounter such an option rom, we need to do |
||||
* the mapping ourselves. |
||||
*/ |
||||
|
||||
uint32_t board_map_oprom_vendev(uint32_t vendev) |
||||
{ |
||||
switch (vendev) { |
||||
case 0x80860102: /* GT1 Desktop */ |
||||
case 0x8086010a: /* GT1 Server */ |
||||
case 0x80860112: /* GT2 Desktop */ |
||||
case 0x80860116: /* GT2 Mobile */ |
||||
case 0x80860122: /* GT2 Desktop >=1.3GHz */ |
||||
case 0x80860126: /* GT2 Mobile >=1.3GHz */ |
||||
case 0x80860156: /* IVB */ |
||||
case 0x80860166: /* IVB */ |
||||
return 0x80860106; /* GT1 Mobile */ |
||||
} |
||||
|
||||
return vendev; |
||||
} |
||||
|
||||
static int int15_handler(void) |
||||
{ |
||||
int res = 0; |
||||
|
||||
debug("%s: INT15 function %04x!\n", __func__, M.x86.R_AX); |
||||
|
||||
switch (M.x86.R_AX) { |
||||
case 0x5f34: |
||||
/*
|
||||
* Set Panel Fitting Hook: |
||||
* bit 2 = Graphics Stretching |
||||
* bit 1 = Text Stretching |
||||
* bit 0 = Centering (do not set with bit1 or bit2) |
||||
* 0 = video bios default |
||||
*/ |
||||
M.x86.R_AX = 0x005f; |
||||
M.x86.R_CL = 0x00; /* Use video bios default */ |
||||
res = 1; |
||||
break; |
||||
case 0x5f35: |
||||
/*
|
||||
* Boot Display Device Hook: |
||||
* bit 0 = CRT |
||||
* bit 1 = TV (eDP) |
||||
* bit 2 = EFP |
||||
* bit 3 = LFP |
||||
* bit 4 = CRT2 |
||||
* bit 5 = TV2 (eDP) |
||||
* bit 6 = EFP2 |
||||
* bit 7 = LFP2 |
||||
*/ |
||||
M.x86.R_AX = 0x005f; |
||||
M.x86.R_CX = 0x0000; /* Use video bios default */ |
||||
res = 1; |
||||
break; |
||||
case 0x5f51: |
||||
/*
|
||||
* Hook to select active LFP configuration: |
||||
* 00h = No LVDS, VBIOS does not enable LVDS |
||||
* 01h = Int-LVDS, LFP driven by integrated LVDS decoder |
||||
* 02h = SVDO-LVDS, LFP driven by SVDO decoder |
||||
* 03h = eDP, LFP Driven by Int-DisplayPort encoder |
||||
*/ |
||||
M.x86.R_AX = 0x005f; |
||||
M.x86.R_CX = 0x0003; /* eDP */ |
||||
res = 1; |
||||
break; |
||||
case 0x5f70: |
||||
switch (M.x86.R_CH) { |
||||
case 0: |
||||
/* Get Mux */ |
||||
M.x86.R_AX = 0x005f; |
||||
M.x86.R_CX = 0x0000; |
||||
res = 1; |
||||
break; |
||||
case 1: |
||||
/* Set Mux */ |
||||
M.x86.R_AX = 0x005f; |
||||
M.x86.R_CX = 0x0000; |
||||
res = 1; |
||||
break; |
||||
case 2: |
||||
/* Get SG/Non-SG mode */ |
||||
M.x86.R_AX = 0x005f; |
||||
M.x86.R_CX = 0x0000; |
||||
res = 1; |
||||
break; |
||||
default: |
||||
/* Interrupt was not handled */ |
||||
debug("Unknown INT15 5f70 function: 0x%02x\n", |
||||
M.x86.R_CH); |
||||
break; |
||||
} |
||||
break; |
||||
case 0x5fac: |
||||
res = 1; |
||||
break; |
||||
default: |
||||
debug("Unknown INT15 function %04x!\n", M.x86.R_AX); |
||||
break; |
||||
} |
||||
return res; |
||||
} |
||||
|
||||
int gma_func0_init(pci_dev_t dev, struct pci_controller *hose, |
||||
const void *blob, int node) |
||||
{ |
||||
void *gtt_bar; |
||||
u32 reg32; |
||||
int ret; |
||||
|
||||
/* IGD needs to be Bus Master */ |
||||
reg32 = pci_read_config32(dev, PCI_COMMAND); |
||||
reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; |
||||
pci_write_config32(dev, PCI_COMMAND, reg32); |
||||
|
||||
gtt_bar = (void *)pci_read_bar32(pci_bus_to_hose(0), dev, 0); |
||||
debug("GT bar %p\n", gtt_bar); |
||||
ret = gma_pm_init_pre_vbios(gtt_bar); |
||||
if (ret) |
||||
return ret; |
||||
|
||||
ret = pci_run_vga_bios(dev, int15_handler, false); |
||||
|
||||
/* Post VBIOS init */ |
||||
ret = gma_pm_init_post_vbios(gtt_bar, blob, node); |
||||
if (ret) |
||||
return ret; |
||||
|
||||
return 0; |
||||
} |
@ -0,0 +1,156 @@ |
||||
/*
|
||||
* From Coreboot file of the same name |
||||
* |
||||
* Copyright (C) 2012 Chromium OS Authors |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0 |
||||
*/ |
||||
|
||||
/* mailbox 0: header */ |
||||
__packed struct opregion_header { |
||||
u8 signature[16]; |
||||
u32 size; |
||||
u32 version; |
||||
u8 sbios_version[32]; |
||||
u8 vbios_version[16]; |
||||
u8 driver_version[16]; |
||||
u32 mailboxes; |
||||
u8 reserved[164]; |
||||
}; |
||||
|
||||
#define IGD_OPREGION_SIGNATURE "IntelGraphicsMem" |
||||
#define IGD_OPREGION_VERSION 2 |
||||
|
||||
#define IGD_MBOX1 (1 << 0) |
||||
#define IGD_MBOX2 (1 << 1) |
||||
#define IGD_MBOX3 (1 << 2) |
||||
#define IGD_MBOX4 (1 << 3) |
||||
#define IGD_MBOX5 (1 << 4) |
||||
|
||||
#define MAILBOXES_MOBILE (IGD_MBOX1 | IGD_MBOX2 | IGD_MBOX3 | \ |
||||
IGD_MBOX4 | IGD_MBOX5) |
||||
#define MAILBOXES_DESKTOP (IGD_MBOX2 | IGD_MBOX4) |
||||
|
||||
#define SBIOS_VERSION_SIZE 32 |
||||
|
||||
/* mailbox 1: public acpi methods */ |
||||
__packed struct opregion_mailbox1 { |
||||
u32 drdy; |
||||
u32 csts; |
||||
u32 cevt; |
||||
u8 reserved1[20]; |
||||
u32 didl[8]; |
||||
u32 cpdl[8]; |
||||
u32 cadl[8]; |
||||
u32 nadl[8]; |
||||
u32 aslp; |
||||
u32 tidx; |
||||
u32 chpd; |
||||
u32 clid; |
||||
u32 cdck; |
||||
u32 sxsw; |
||||
u32 evts; |
||||
u32 cnot; |
||||
u32 nrdy; |
||||
u8 reserved2[60]; |
||||
}; |
||||
|
||||
/* mailbox 2: software sci interface */ |
||||
__packed struct opregion_mailbox2 { |
||||
u32 scic; |
||||
u32 parm; |
||||
u32 dslp; |
||||
u8 reserved[244]; |
||||
}; |
||||
|
||||
/* mailbox 3: power conservation */ |
||||
__packed struct opregion_mailbox3 { |
||||
u32 ardy; |
||||
u32 aslc; |
||||
u32 tche; |
||||
u32 alsi; |
||||
u32 bclp; |
||||
u32 pfit; |
||||
u32 cblv; |
||||
u16 bclm[20]; |
||||
u32 cpfm; |
||||
u32 epfm; |
||||
u8 plut[74]; |
||||
u32 pfmb; |
||||
u32 ccdv; |
||||
u32 pcft; |
||||
u8 reserved[94]; |
||||
}; |
||||
|
||||
#define IGD_BACKLIGHT_BRIGHTNESS 0xff |
||||
#define IGD_INITIAL_BRIGHTNESS 0x64 |
||||
|
||||
#define IGD_FIELD_VALID (1 << 31) |
||||
#define IGD_WORD_FIELD_VALID (1 << 15) |
||||
#define IGD_PFIT_STRETCH 6 |
||||
|
||||
/* mailbox 4: vbt */ |
||||
__packed struct { |
||||
u8 gvd1[7168]; |
||||
} opregion_vbt_t; |
||||
|
||||
/* IGD OpRegion */ |
||||
__packed struct igd_opregion { |
||||
opregion_header_t header; |
||||
opregion_mailbox1_t mailbox1; |
||||
opregion_mailbox2_t mailbox2; |
||||
opregion_mailbox3_t mailbox3; |
||||
opregion_vbt_t vbt; |
||||
}; |
||||
|
||||
/* Intel Video BIOS (Option ROM) */ |
||||
__packed struct optionrom_header { |
||||
u16 signature; |
||||
u8 size; |
||||
u8 reserved[21]; |
||||
u16 pcir_offset; |
||||
u16 vbt_offset; |
||||
}; |
||||
|
||||
#define OPROM_SIGNATURE 0xaa55 |
||||
|
||||
__packed struct optionrom_pcir { |
||||
u32 signature; |
||||
u16 vendor; |
||||
u16 device; |
||||
u16 reserved1; |
||||
u16 length; |
||||
u8 revision; |
||||
u8 classcode[3]; |
||||
u16 imagelength; |
||||
u16 coderevision; |
||||
u8 codetype; |
||||
u8 indicator; |
||||
u16 reserved2; |
||||
}; |
||||
|
||||
__packed struct optionrom_vbt { |
||||
u8 hdr_signature[20]; |
||||
u16 hdr_version; |
||||
u16 hdr_size; |
||||
u16 hdr_vbt_size; |
||||
u8 hdr_vbt_checksum; |
||||
u8 hdr_reserved; |
||||
u32 hdr_vbt_datablock; |
||||
u32 hdr_aim[4]; |
||||
u8 datahdr_signature[16]; |
||||
u16 datahdr_version; |
||||
u16 datahdr_size; |
||||
u16 datahdr_datablocksize; |
||||
u8 coreblock_id; |
||||
u16 coreblock_size; |
||||
u16 coreblock_biossize; |
||||
u8 coreblock_biostype; |
||||
u8 coreblock_releasestatus; |
||||
u8 coreblock_hwsupported; |
||||
u8 coreblock_integratedhw; |
||||
u8 coreblock_biosbuild[4]; |
||||
u8 coreblock_biossignon[155]; |
||||
}; |
||||
|
||||
#define VBT_SIGNATURE 0x54425624 |
@ -0,0 +1,40 @@ |
||||
Intel GMA Bindings |
||||
================== |
||||
|
||||
This is the Intel Graphics Media Accelerator. This binding supports selection |
||||
of display parameters only. |
||||
|
||||
|
||||
Required properties: |
||||
- compatible : "intel,gma"; |
||||
|
||||
Optional properties: |
||||
- intel,dp-hotplug : values for digital port hotplug, one cell per value for |
||||
ports B, C and D |
||||
- intel,panel-port-select : output port to use: 0=LVDS 1=DP_B 2=DP_C 3=DP_D |
||||
- intel,panel-power-cycle-delay : T4 time sequence (6 = 500ms) |
||||
|
||||
The following delays are in units of 0.1ms: |
||||
- intel,panel-power-up-delay : T1+T2 time sequence |
||||
- intel,panel-power-down-delay : T3 time sequence |
||||
- intel,panel-power-backlight-on-delay : T5 time sequence |
||||
- intel,panel-power-backlight-off-delay : Tx time sequence |
||||
|
||||
- intel,cpu-backlight : Value for CPU Backlight PWM |
||||
- intel,pch-backlight : Value for PCH Backlight PWM |
||||
|
||||
Example |
||||
------- |
||||
|
||||
gma { |
||||
compatible = "intel,gma"; |
||||
intel,dp_hotplug = <0 0 0x06>; |
||||
intel,panel-port-select = <1>; |
||||
intel,panel-power-cycle-delay = <6>; |
||||
intel,panel-power-up-delay = <2000>; |
||||
intel,panel-power-down-delay = <500>; |
||||
intel,panel-power-backlight-on-delay = <2000>; |
||||
intel,panel-power-backlight-off-delay = <2000>; |
||||
intel,cpu-backlight = <0x00000200>; |
||||
intel,pch-backlight = <0x04000000>; |
||||
}; |
Loading…
Reference in new issue