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mpc8xx: remove NETVIA board support

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This board is still a non-generic board.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Pantelis Antoniou <panto@intracom.gr>
master
Masahiro Yamada 10 years ago committed by Tom Rini
parent 79cbecb81b
commit f017cd7f71
14 changed files with 1 additions and 1564 deletions
Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL
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  1. 4
      arch/powerpc/cpu/mpc8xx/Kconfig
  2. 20
      arch/powerpc/cpu/mpc8xx/scc.c
  3. 9
      board/netvia/Kconfig
  4. 7
      board/netvia/MAINTAINERS
  5. 8
      board/netvia/Makefile
  6. 495
      board/netvia/flash.c
  7. 401
      board/netvia/netvia.c
  8. 121
      board/netvia/u-boot.lds.debug
  9. 4
      configs/NETVIA_V2_defconfig
  10. 4
      configs/NETVIA_defconfig
  11. 1
      doc/README.scrapyard
  12. 33
      include/commproc.h
  13. 435
      include/configs/NETVIA.h
  14. 23
      include/status_led.h

4
arch/powerpc/cpu/mpc8xx/Kconfig
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@ -25,9 +25,6 @@ config TARGET_IVMS8
config TARGET_LWMON
bool "Support lwmon"
config TARGET_NETVIA
bool "Support NETVIA"
config TARGET_TQM823L
bool "Support TQM823L"
@ -71,7 +68,6 @@ source "board/esteem192e/Kconfig"
source "board/ip860/Kconfig"
source "board/ivm/Kconfig"
source "board/lwmon/Kconfig"
source "board/netvia/Kconfig"
source "board/tqc/tqm8xx/Kconfig"
endmenu

20
arch/powerpc/cpu/mpc8xx/scc.c
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@ -448,26 +448,6 @@ static int scc_init (struct eth_device *dev, bd_t * bis)
#error Configuration Error: exactly ONE of PB_ENET_TENA, PC_ENET_TENA must be defined
#endif
#if defined(CONFIG_NETVIA)
#if defined(PA_ENET_PDN)
immr->im_ioport.iop_papar &= ~PA_ENET_PDN;
immr->im_ioport.iop_padir |= PA_ENET_PDN;
immr->im_ioport.iop_padat |= PA_ENET_PDN;
#elif defined(PB_ENET_PDN)
immr->im_cpm.cp_pbpar &= ~PB_ENET_PDN;
immr->im_cpm.cp_pbdir |= PB_ENET_PDN;
immr->im_cpm.cp_pbdat |= PB_ENET_PDN;
#elif defined(PC_ENET_PDN)
immr->im_ioport.iop_pcpar &= ~PC_ENET_PDN;
immr->im_ioport.iop_pcdir |= PC_ENET_PDN;
immr->im_ioport.iop_pcdat |= PC_ENET_PDN;
#elif defined(PD_ENET_PDN)
immr->im_ioport.iop_pdpar &= ~PD_ENET_PDN;
immr->im_ioport.iop_pddir |= PD_ENET_PDN;
immr->im_ioport.iop_pddat |= PD_ENET_PDN;
#endif
#endif
/*
* Set the ENT/ENR bits in the GSMR Low -- Enable Transmit/Receive
*/

9
board/netvia/Kconfig
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@ -1,9 +0,0 @@
if TARGET_NETVIA
config SYS_BOARD
default "netvia"
config SYS_CONFIG_NAME
default "NETVIA"
endif

7
board/netvia/MAINTAINERS
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@ -1,7 +0,0 @@
NETVIA BOARD
M: Pantelis Antoniou <panto@intracom.gr>
S: Maintained
F: board/netvia/
F: include/configs/NETVIA.h
F: configs/NETVIA_defconfig
F: configs/NETVIA_V2_defconfig

8
board/netvia/Makefile
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@ -1,8 +0,0 @@
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y = netvia.o flash.o

495
board/netvia/flash.c
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@ -1,495 +0,0 @@
/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <mpc8xx.h>
flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
/*-----------------------------------------------------------------------
* Functions
*/
static ulong flash_get_size(vu_long * addr, flash_info_t * info);
static int write_byte(flash_info_t * info, ulong dest, uchar data);
static void flash_get_offsets(ulong base, flash_info_t * info);
/*-----------------------------------------------------------------------
*/
unsigned long flash_init(void)
{
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
unsigned long size;
int i;
/* Init: no FLASHes known */
for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i)
flash_info[i].flash_id = FLASH_UNKNOWN;
size = flash_get_size((vu_long *) FLASH_BASE0_PRELIM, &flash_info[0]);
if (flash_info[0].flash_id == FLASH_UNKNOWN) {
printf("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", size, size << 20);
}
/* Remap FLASH according to real size */
memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size & 0xFFFF8000);
memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | (memctl->memc_br0 & ~(BR_BA_MSK));
/* Re-do sizing to get full correct info */
size = flash_get_size((vu_long *) CONFIG_SYS_FLASH_BASE, &flash_info[0]);
flash_get_offsets(CONFIG_SYS_FLASH_BASE, &flash_info[0]);
/* monitor protection ON by default */
flash_protect(FLAG_PROTECT_SET,
CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1,
&flash_info[0]);
flash_protect ( FLAG_PROTECT_SET,
CONFIG_ENV_ADDR,
CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
&flash_info[0]);
#ifdef CONFIG_ENV_ADDR_REDUND
flash_protect ( FLAG_PROTECT_SET,
CONFIG_ENV_ADDR_REDUND,
CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
&flash_info[0]);
#endif
flash_info[0].size = size;
return (size);
}
/*-----------------------------------------------------------------------
*/
static void flash_get_offsets(ulong base, flash_info_t * info)
{
int i;
/* set up sector start address table */
if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) {
for (i = 0; i < info->sector_count; i++) {
info->start[i] = base + (i * 0x00010000);
}
} else if (info->flash_id & FLASH_BTYPE) {
/* set sector offsets for bottom boot block type */
info->start[0] = base + 0x00000000;
info->start[1] = base + 0x00004000;
info->start[2] = base + 0x00006000;
info->start[3] = base + 0x00008000;
for (i = 4; i < info->sector_count; i++) {
info->start[i] = base + (i * 0x00010000) - 0x00030000;
}
} else {
/* set sector offsets for top boot block type */
i = info->sector_count - 1;
info->start[i--] = base + info->size - 0x00004000;
info->start[i--] = base + info->size - 0x00006000;
info->start[i--] = base + info->size - 0x00008000;
for (; i >= 0; i--) {
info->start[i] = base + i * 0x00010000;
}
}
}
/*-----------------------------------------------------------------------
*/
void flash_print_info(flash_info_t * info)
{
int i;
if (info->flash_id == FLASH_UNKNOWN) {
printf("missing or unknown FLASH type\n");
return;
}
switch (info->flash_id & FLASH_VENDMASK) {
case FLASH_MAN_AMD:
printf("AMD ");
break;
case FLASH_MAN_FUJ:
printf("FUJITSU ");
break;
case FLASH_MAN_MX:
printf("MXIC ");
break;
default:
printf("Unknown Vendor ");
break;
}
switch (info->flash_id & FLASH_TYPEMASK) {
case FLASH_AM040:
printf("AM29LV040B (4 Mbit, bottom boot sect)\n");
break;
case FLASH_AM400B:
printf("AM29LV400B (4 Mbit, bottom boot sect)\n");
break;
case FLASH_AM400T:
printf("AM29LV400T (4 Mbit, top boot sector)\n");
break;
case FLASH_AM800B:
printf("AM29LV800B (8 Mbit, bottom boot sect)\n");
break;
case FLASH_AM800T:
printf("AM29LV800T (8 Mbit, top boot sector)\n");
break;
case FLASH_AM160B:
printf("AM29LV160B (16 Mbit, bottom boot sect)\n");
break;
case FLASH_AM160T:
printf("AM29LV160T (16 Mbit, top boot sector)\n");
break;
case FLASH_AM320B:
printf("AM29LV320B (32 Mbit, bottom boot sect)\n");
break;
case FLASH_AM320T:
printf("AM29LV320T (32 Mbit, top boot sector)\n");
break;
default:
printf("Unknown Chip Type\n");
break;
}
printf(" Size: %ld MB in %d Sectors\n", info->size >> 20, info->sector_count);
printf(" Sector Start Addresses:");
for (i = 0; i < info->sector_count; ++i) {
if ((i % 5) == 0)
printf("\n ");
printf(" %08lX%s", info->start[i], info->protect[i] ? " (RO)" : " ");
}
printf("\n");
}
/*-----------------------------------------------------------------------
*/
/*-----------------------------------------------------------------------
*/
/*
* The following code cannot be run from FLASH!
*/
static ulong flash_get_size(vu_long * addr, flash_info_t * info)
{
short i;
uchar mid;
uchar pid;
vu_char *caddr = (vu_char *) addr;
ulong base = (ulong) addr;
/* Write auto select command: read Manufacturer ID */
caddr[0x0555] = 0xAA;
caddr[0x02AA] = 0x55;
caddr[0x0555] = 0x90;
mid = caddr[0];
switch (mid) {
case (AMD_MANUFACT & 0xFF):
info->flash_id = FLASH_MAN_AMD;
break;
case (FUJ_MANUFACT & 0xFF):
info->flash_id = FLASH_MAN_FUJ;
break;
case (MX_MANUFACT & 0xFF):
info->flash_id = FLASH_MAN_MX;
break;
case (STM_MANUFACT & 0xFF):
info->flash_id = FLASH_MAN_STM;
break;
default:
info->flash_id = FLASH_UNKNOWN;
info->sector_count = 0;
info->size = 0;
return (0); /* no or unknown flash */
}
pid = caddr[1]; /* device ID */
switch (pid) {
case (AMD_ID_LV400T & 0xFF):
info->flash_id += FLASH_AM400T;
info->sector_count = 11;
info->size = 0x00080000;
break; /* => 512 kB */
case (AMD_ID_LV400B & 0xFF):
info->flash_id += FLASH_AM400B;
info->sector_count = 11;
info->size = 0x00080000;
break; /* => 512 kB */
case (AMD_ID_LV800T & 0xFF):
info->flash_id += FLASH_AM800T;
info->sector_count = 19;
info->size = 0x00100000;
break; /* => 1 MB */
case (AMD_ID_LV800B & 0xFF):
info->flash_id += FLASH_AM800B;
info->sector_count = 19;
info->size = 0x00100000;
break; /* => 1 MB */
case (AMD_ID_LV160T & 0xFF):
info->flash_id += FLASH_AM160T;
info->sector_count = 35;
info->size = 0x00200000;
break; /* => 2 MB */
case (AMD_ID_LV160B & 0xFF):
info->flash_id += FLASH_AM160B;
info->sector_count = 35;
info->size = 0x00200000;
break; /* => 2 MB */
case (AMD_ID_LV040B & 0xFF):
info->flash_id += FLASH_AM040;
info->sector_count = 8;
info->size = 0x00080000;
break;
case (STM_ID_M29W040B & 0xFF):
info->flash_id += FLASH_AM040;
info->sector_count = 8;
info->size = 0x00080000;
break;
#if 0 /* enable when device IDs are available */
case (AMD_ID_LV320T & 0xFF):
info->flash_id += FLASH_AM320T;
info->sector_count = 67;
info->size = 0x00400000;
break; /* => 4 MB */
case (AMD_ID_LV320B & 0xFF):
info->flash_id += FLASH_AM320B;
info->sector_count = 67;
info->size = 0x00400000;
break; /* => 4 MB */
#endif
default:
info->flash_id = FLASH_UNKNOWN;
return (0); /* => no or unknown flash */
}
printf(" ");
/* set up sector start address table */
if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) {
for (i = 0; i < info->sector_count; i++) {
info->start[i] = base + (i * 0x00010000);
}
} else if (info->flash_id & FLASH_BTYPE) {
/* set sector offsets for bottom boot block type */
info->start[0] = base + 0x00000000;
info->start[1] = base + 0x00004000;
info->start[2] = base + 0x00006000;
info->start[3] = base + 0x00008000;
for (i = 4; i < info->sector_count; i++) {
info->start[i] = base + (i * 0x00010000) - 0x00030000;
}
} else {
/* set sector offsets for top boot block type */
i = info->sector_count - 1;
info->start[i--] = base + info->size - 0x00004000;
info->start[i--] = base + info->size - 0x00006000;
info->start[i--] = base + info->size - 0x00008000;
for (; i >= 0; i--) {
info->start[i] = base + i * 0x00010000;
}
}
/* check for protected sectors */
for (i = 0; i < info->sector_count; i++) {
/* read sector protection: D0 = 1 if protected */
caddr = (volatile unsigned char *)(info->start[i]);
info->protect[i] = caddr[2] & 1;
}
/*
* Prevent writes to uninitialized FLASH.
*/
if (info->flash_id != FLASH_UNKNOWN) {
caddr = (vu_char *) info->start[0];
caddr[0x0555] = 0xAA;
caddr[0x02AA] = 0x55;
caddr[0x0555] = 0xF0;
udelay(20000);
}
return (info->size);
}
/*-----------------------------------------------------------------------
*/
int flash_erase(flash_info_t * info, int s_first, int s_last)
{
vu_char *addr = (vu_char *) (info->start[0]);
int flag, prot, sect, l_sect;
ulong start, now, last;
if ((s_first < 0) || (s_first > s_last)) {
if (info->flash_id == FLASH_UNKNOWN) {
printf("- missing\n");
} else {
printf("- no sectors to erase\n");
}
return 1;
}
if ((info->flash_id == FLASH_UNKNOWN) ||
(info->flash_id > FLASH_AMD_COMP)) {
printf("Can't erase unknown flash type %08lx - aborted\n", info->flash_id);
return 1;
}
prot = 0;
for (sect = s_first; sect <= s_last; ++sect) {
if (info->protect[sect]) {
prot++;
}
}
if (prot) {
printf("- Warning: %d protected sectors will not be erased!\n", prot);
} else {
printf("\n");
}
l_sect = -1;
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
addr[0x0555] = 0xAA;
addr[0x02AA] = 0x55;
addr[0x0555] = 0x80;
addr[0x0555] = 0xAA;
addr[0x02AA] = 0x55;
/* Start erase on unprotected sectors */
for (sect = s_first; sect <= s_last; sect++) {
if (info->protect[sect] == 0) { /* not protected */
addr = (vu_char *) (info->start[sect]);
addr[0] = 0x30;
l_sect = sect;
}
}
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts();
/* wait at least 80us - let's wait 1 ms */
udelay(1000);
/*
* We wait for the last triggered sector
*/
if (l_sect < 0)
goto DONE;
start = get_timer(0);
last = start;
addr = (vu_char *) (info->start[l_sect]);
while ((addr[0] & 0x80) != 0x80) {
if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
printf("Timeout\n");
return 1;
}
/* show that we're waiting */
if ((now - last) > 1000) { /* every second */
putc('.');
last = now;
}
}
DONE:
/* reset to read mode */
addr = (vu_char *) info->start[0];
addr[0] = 0xF0; /* reset bank */
printf(" done\n");
return 0;
}
/*-----------------------------------------------------------------------
* Copy memory to flash, returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
*/
int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
{
int rc;
while (cnt > 0) {
if ((rc = write_byte(info, addr++, *src++)) != 0) {
return (rc);
}
--cnt;
}
return (0);
}
/*-----------------------------------------------------------------------
* Write a word to Flash, returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
*/
static int write_byte(flash_info_t * info, ulong dest, uchar data)
{
vu_char *addr = (vu_char *) (info->start[0]);
ulong start;
int flag;
/* Check if Flash is (sufficiently) erased */
if ((*((vu_char *) dest) & data) != data) {
return (2);
}
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
addr[0x0555] = 0xAA;
addr[0x02AA] = 0x55;
addr[0x0555] = 0xA0;
*((vu_char *) dest) = data;
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts();
/* data polling for D7 */
start = get_timer(0);
while ((*((vu_char *) dest) & 0x80) != (data & 0x80)) {
if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
return (1);
}
}
return (0);
}
/*-----------------------------------------------------------------------
*/

401
board/netvia/netvia.c
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@ -1,401 +0,0 @@
/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*/
/*
* Pantelis Antoniou, Intracom S.A., panto@intracom.gr
* U-Boot port on NetVia board
*/
#include <common.h>
#include "mpc8xx.h"
/****************************************************************/
#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
/* last value written to the external register; we cannot read back */
unsigned int last_er_val;
#endif
/****************************************************************/
/****************************************************************/
/* some sane bit macros */
#define _BD(_b) (1U << (31-(_b)))
#define _BDR(_l, _h) (((((1U << (31-(_l))) - 1) << 1) | 1) & ~((1U << (31-(_h))) - 1))
#define _BW(_b) (1U << (15-(_b)))
#define _BWR(_l, _h) (((((1U << (15-(_l))) - 1) << 1) | 1) & ~((1U << (15-(_h))) - 1))
#define _BB(_b) (1U << (7-(_b)))
#define _BBR(_l, _h) (((((1U << (7-(_l))) - 1) << 1) | 1) & ~((1U << (7-(_h))) - 1))
#define _B(_b) _BD(_b)
#define _BR(_l, _h) _BDR(_l, _h)
/****************************************************************/
#define _NOT_USED_ 0xFFFFFFFF
/****************************************************************/
#define CS_0000 0x00000000
#define CS_0001 0x10000000
#define CS_0010 0x20000000
#define CS_0011 0x30000000
#define CS_0100 0x40000000
#define CS_0101 0x50000000
#define CS_0110 0x60000000
#define CS_0111 0x70000000
#define CS_1000 0x80000000
#define CS_1001 0x90000000
#define CS_1010 0xA0000000
#define CS_1011 0xB0000000
#define CS_1100 0xC0000000
#define CS_1101 0xD0000000
#define CS_1110 0xE0000000
#define CS_1111 0xF0000000
#define BS_0000 0x00000000
#define BS_0001 0x01000000
#define BS_0010 0x02000000
#define BS_0011 0x03000000
#define BS_0100 0x04000000
#define BS_0101 0x05000000
#define BS_0110 0x06000000
#define BS_0111 0x07000000
#define BS_1000 0x08000000
#define BS_1001 0x09000000
#define BS_1010 0x0A000000
#define BS_1011 0x0B000000
#define BS_1100 0x0C000000
#define BS_1101 0x0D000000
#define BS_1110 0x0E000000
#define BS_1111 0x0F000000
#define A10_AAAA 0x00000000
#define A10_AAA0 0x00200000
#define A10_AAA1 0x00300000
#define A10_000A 0x00800000
#define A10_0000 0x00A00000
#define A10_0001 0x00B00000
#define A10_111A 0x00C00000
#define A10_1110 0x00E00000
#define A10_1111 0x00F00000
#define RAS_0000 0x00000000
#define RAS_0001 0x00040000
#define RAS_1110 0x00080000
#define RAS_1111 0x000C0000
#define CAS_0000 0x00000000
#define CAS_0001 0x00010000
#define CAS_1110 0x00020000
#define CAS_1111 0x00030000
#define WE_0000 0x00000000
#define WE_0001 0x00004000
#define WE_1110 0x00008000
#define WE_1111 0x0000C000
#define GPL4_0000 0x00000000
#define GPL4_0001 0x00001000
#define GPL4_1110 0x00002000
#define GPL4_1111 0x00003000
#define GPL5_0000 0x00000000
#define GPL5_0001 0x00000400
#define GPL5_1110 0x00000800
#define GPL5_1111 0x00000C00
#define LOOP 0x00000080
#define EXEN 0x00000040
#define AMX_COL 0x00000000
#define AMX_ROW 0x00000020
#define AMX_MAR 0x00000030
#define NA 0x00000008
#define UTA 0x00000004
#define TODT 0x00000002
#define LAST 0x00000001
const uint sdram_table[0x40] = {
/* RSS */
CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
CS_0000 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */
CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */
CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */
_NOT_USED_, _NOT_USED_,
/* RBS */
CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
CS_0001 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */
CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL, /* PALL */
CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | TODT | LAST, /* NOP */
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/* WSS */
CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA,
CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,
CS_0000 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL | UTA,
CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/* WBS */
CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL, /* WRITE */
CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
CS_1111 | BS_0001 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */
CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_,
/* UPT */
CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_0001 | WE_1111 | AMX_COL | LOOP,
CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,
CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL,
CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | LOOP,
CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | LAST,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_,
/* EXC */
CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL,
CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | TODT | LAST,
/* REG */
CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1110 | AMX_MAR,
CS_0001 | BS_1111 | A10_0001 | RAS_0001 | CAS_0001 | WE_0001 | AMX_MAR | TODT | LAST,
};
/* ------------------------------------------------------------------------- */
/*
* Check Board Identity:
*
* Test ETX ID string (ETX_xxx...)
*
* Return 1 always.
*/
int checkboard(void)
{
#if !defined(CONFIG_NETVIA_VERSION) || CONFIG_NETVIA_VERSION == 1
printf ("NETVIA v1\n");
#else
printf ("NETVIA v2+\n");
#endif
return (0);
}
/* ------------------------------------------------------------------------- */
/* 0xC8 = 0b11001000 , CAS3, >> 2 = 0b00 11 0 010 */
#define MAR_SDRAM_INIT 0x000000C8LU
#define MCR_OP(x) ((unsigned long)((x) & 3) << (31-1))
#define MCR_OP_MASK MCR_OP(3)
#define MCR_UM(x) ((unsigned long)((x) & 1) << (31 - 8))
#define MCR_UM_MASK MCR_UM(1)
#define MCR_UM_UPMA MCR_UM(0)
#define MCR_UM_UPMB MCR_UM(1)
#define MCR_MB(x) ((unsigned long)((x) & 7) << (31 - 18))
#define MCR_MB_MASK MCR_MB(7)
#define MCR_MB_CS(x) MCR_MB(x)
#define MCR_MCLF(x) ((unsigned long)((x) & 15) << (31 - 23))
#define MCR_MCLF_MASK MCR_MCLF(15)
phys_size_t initdram(int board_type)
{
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
long int size;
upmconfig(UPMA, (uint *) sdram_table, sizeof(sdram_table) / sizeof(uint));
/*
* Preliminary prescaler for refresh
*/
memctl->memc_mptpr = CONFIG_SYS_MPTPR_1BK_8K;
memctl->memc_mar = MAR_SDRAM_INIT; /* 32-bit address to be output on the address bus if AMX = 0b11 */
/*
* Map controller bank 3 to the SDRAM bank at preliminary address.
*/
memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM;
memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM;
memctl->memc_mamr = CONFIG_SYS_MAMR_9COL & ~MAMR_PTAE; /* no refresh yet */
udelay(200);
/* perform SDRAM initialisation sequence */
memctl->memc_mcr = MCR_OP_RUN | MCR_UM_UPMA | MCR_MB_CS3 | MCR_MCLF(1) | MCR_MAD(0x3C); /* precharge all */
udelay(1);
memctl->memc_mcr = MCR_OP_RUN | MCR_UM_UPMA | MCR_MB_CS3 | MCR_MCLF(0) | MCR_MAD(0x30); /* refresh 16 times(0) */
udelay(1);
memctl->memc_mcr = MCR_OP_RUN | MCR_UM_UPMA | MCR_MB_CS3 | MCR_MCLF(1) | MCR_MAD(0x3E); /* exception program (write mar) */
udelay(1);
memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
udelay(1000);
memctl->memc_mamr = CONFIG_SYS_MAMR_9COL;
size = SDRAM_MAX_SIZE;
udelay(10000);
return (size);
}
/* ------------------------------------------------------------------------- */
int misc_init_r(void)
{
#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
last_er_val = 0xffffffff;
#endif
return(0);
}
/* ------------------------------------------------------------------------- */
/* GP = general purpose, SP = special purpose (on chip peripheral) */
/* bits that can have a special purpose or can be configured as inputs/outputs */
#define PA_GP_INMASK 0
#define PA_GP_OUTMASK (_BW(5) | _BWR(14, 15))
#define PA_SP_MASK (_BW(4) | _BWR(6, 13))
#define PA_ODR_VAL 0
#define PA_GP_OUTVAL _BW(5)
#define PA_SP_DIRVAL 0
#define PB_GP_INMASK _B(28)
#define PB_GP_OUTMASK (_BR(16, 19) | _BR(26, 27) | _BR(29, 31))
#define PB_SP_MASK _BR(22, 25)
#define PB_ODR_VAL 0
#define PB_GP_OUTVAL (_BR(16, 19) | _BR(26, 27) | _BR(29, 31))
#define PB_SP_DIRVAL 0
#if !defined(CONFIG_NETVIA_VERSION) || CONFIG_NETVIA_VERSION == 1
#define PC_GP_INMASK (_BWR(5, 7) | _BWR(9, 10) | _BW(13))
#define PC_GP_OUTMASK _BW(12)
#define PC_SP_MASK (_BW(4) | _BW(8))
#define PC_SOVAL 0
#define PC_INTVAL 0
#define PC_GP_OUTVAL 0
#define PC_SP_DIRVAL 0
#define PD_GP_INMASK 0
#define PD_GP_OUTMASK _BWR(3, 15)
#define PD_SP_MASK 0
#define PD_GP_OUTVAL (_BW(3) | _BW(5) | _BW(7) | _BWR(8, 15))
#define PD_SP_DIRVAL 0
#elif CONFIG_NETVIA_VERSION >= 2
#define PC_GP_INMASK (_BW(5) | _BW(7) | _BWR(9, 11) | _BWR(13, 15))
#define PC_GP_OUTMASK (_BW(6) | _BW(12))
#define PC_SP_MASK (_BW(4) | _BW(8))
#define PC_SOVAL 0
#define PC_INTVAL _BW(7)
#define PC_GP_OUTVAL (_BW(6) | _BW(12))
#define PC_SP_DIRVAL 0
#define PD_GP_INMASK 0
#define PD_GP_OUTMASK _BWR(3, 15)
#define PD_SP_MASK 0
#define PD_GP_OUTVAL (_BW(3) | _BW(5) | _BW(9) | _BW(11))
#define PD_SP_DIRVAL 0
#else
#error Unknown NETVIA board version.
#endif
int board_early_init_f(void)
{
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
volatile iop8xx_t *ioport = &immap->im_ioport;
volatile cpm8xx_t *cpm = &immap->im_cpm;
volatile memctl8xx_t *memctl = &immap->im_memctl;
/* DSP0 chip select */
memctl->memc_or4 = ((0xFFFFFFFFLU & ~(DSP_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_ACS_DIV2 | OR_SETA | OR_TRLX);
memctl->memc_br4 = ((DSP0_BASE & BR_BA_MSK) | BR_PS_16 | BR_V);
/* DSP1 chip select */
memctl->memc_or5 = ((0xFFFFFFFFLU & ~(DSP_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_ACS_DIV2 | OR_SETA | OR_TRLX);
memctl->memc_br5 = ((DSP1_BASE & BR_BA_MSK) | BR_PS_16 | BR_V);
/* FPGA chip select */
memctl->memc_or6 = ((0xFFFFFFFFLU & ~(FPGA_SIZE - 1)) | OR_BI | OR_SCY_1_CLK);
memctl->memc_br6 = ((FPGA_BASE & BR_BA_MSK) | BR_PS_8 | BR_V);
#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
/* NAND chip select */
memctl->memc_or1 = ((0xFFFFFFFFLU & ~(NAND_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_SCY_8_CLK | OR_EHTR | OR_TRLX);
memctl->memc_br1 = ((NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_V);
/* kill this chip select */
memctl->memc_br2 &= ~BR_V; /* invalid */
/* external reg chip select */
memctl->memc_or7 = ((0xFFFFFFFFLU & ~(ER_SIZE - 1)) | OR_BI | OR_SCY_4_CLK);
memctl->memc_br7 = ((ER_BASE & BR_BA_MSK) | BR_PS_32 | BR_V);
#endif
ioport->iop_padat = PA_GP_OUTVAL;
ioport->iop_paodr = PA_ODR_VAL;
ioport->iop_padir = PA_GP_OUTMASK | PA_SP_DIRVAL;
ioport->iop_papar = PA_SP_MASK;
cpm->cp_pbdat = PB_GP_OUTVAL;
cpm->cp_pbodr = PB_ODR_VAL;
cpm->cp_pbdir = PB_GP_OUTMASK | PB_SP_DIRVAL;
cpm->cp_pbpar = PB_SP_MASK;
ioport->iop_pcdat = PC_GP_OUTVAL;
ioport->iop_pcdir = PC_GP_OUTMASK | PC_SP_DIRVAL;
ioport->iop_pcso = PC_SOVAL;
ioport->iop_pcint = PC_INTVAL;
ioport->iop_pcpar = PC_SP_MASK;
ioport->iop_pddat = PD_GP_OUTVAL;
ioport->iop_pddir = PD_GP_OUTMASK | PD_SP_DIRVAL;
ioport->iop_pdpar = PD_SP_MASK;
#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
/* external register init */
*(volatile uint *)ER_BASE = 0xFFFFFFFF;
#endif
return 0;
}

121
board/netvia/u-boot.lds.debug
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@ -1,121 +0,0 @@
/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*/
OUTPUT_ARCH(powerpc)
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
arch/powerpc/cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
lib/vsprintf.o (.text)
lib/crc32.o (.text)
. = env_offset;
common/env_embedded.o(.text)
*(.text)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
*(.eh_frame)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x0FFF) & 0xFFFFF000;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
. = ALIGN(4);
.u_boot_list : {
KEEP(*(SORT(.u_boot_list*)));
}
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(4096);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(4096);
__init_end = .;
__bss_start = .;
.bss :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
}
__bss_end = . ;
PROVIDE (end = .);
}

4
configs/NETVIA_V2_defconfig
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@ -1,4 +0,0 @@
CONFIG_SYS_EXTRA_OPTIONS="NETVIA_VERSION=2"
CONFIG_PPC=y
CONFIG_8xx=y
CONFIG_TARGET_NETVIA=y

4
configs/NETVIA_defconfig
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@ -1,4 +0,0 @@
CONFIG_SYS_EXTRA_OPTIONS="NETVIA_VERSION=1"
CONFIG_PPC=y
CONFIG_8xx=y
CONFIG_TARGET_NETVIA=y

1
doc/README.scrapyard
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@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order.
Board Arch CPU Commit Removed Last known maintainer/contact
=================================================================================================
NETVIA powerpc mpc8xx - - Pantelis Antoniou <panto@intracom.gr>
R360MPI powerpc mpc8xx - - Wolfgang Denk <wd@denx.de>
RRvision powerpc mpc8xx - - Wolfgang Denk <wd@denx.de>
SPD823TS powerpc mpc8xx - - Wolfgang Denk <wd@denx.de>

33
include/commproc.h
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@ -594,39 +594,6 @@ typedef struct scc_enet {
#define SICR_ENET_CLKRT ((uint)0x00250000)
#endif /* CONFIG_KM8XX */
/*** NETVIA *******************************************************/
#if defined(CONFIG_NETVIA)
/* Bits in parallel I/O port registers that have to be set/cleared
* to configure the pins for SCC2 use.
*/
#define PROFF_ENET PROFF_SCC2
#define CPM_CR_ENET CPM_CR_CH_SCC2
#define SCC_ENET 1
#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */
#define PA_ENET_TCLK ((ushort)0x0800) /* PA 4 */
#if !defined(CONFIG_NETVIA_VERSION) || CONFIG_NETVIA_VERSION == 1
# define PB_ENET_PDN ((ushort)0x4000) /* PB 17 */
#elif CONFIG_NETVIA_VERSION >= 2
# define PC_ENET_PDN ((ushort)0x0008) /* PC 12 */
#endif
#define PB_ENET_TENA ((ushort)0x2000) /* PB 18 */
#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
* SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
*/
#define SICR_ENET_MASK ((uint)0x0000ff00)
#define SICR_ENET_CLKRT ((uint)0x00002f00)
#endif /* CONFIG_NETVIA */
/*** MVS1, TQM823L/M, TQM850L/M, TQM885D, R360MPI **********/
#if (defined(CONFIG_MVS) && CONFIG_MVS < 2) || \

435
include/configs/NETVIA.h
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@ -1,435 +0,0 @@
/*
* (C) Copyright 2000-2010
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* SPDX-License-Identifier: GPL-2.0+
*/
/*
* Pantelis Antoniou, Intracom S.A., panto@intracom.gr
* U-Boot port on NetVia board
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_MPC850 1 /* This is a MPC850 CPU */
#define CONFIG_NETVIA 1 /* ...on a NetVia board */
#define CONFIG_SYS_TEXT_BASE 0x40000000
#if !defined(CONFIG_NETVIA_VERSION) || CONFIG_NETVIA_VERSION == 1
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
#undef CONFIG_8xx_CONS_SMC2
#undef CONFIG_8xx_CONS_NONE
#else
#define CONFIG_8xx_CONS_NONE
#define CONFIG_MAX3100_SERIAL
#endif
#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
#define CONFIG_XIN 10000000
#define CONFIG_8xx_GCLK_FREQ 80000000
#if 0
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
#else
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#endif
#undef CONFIG_CLOCKS_IN_MHZ /* clocks NOT passsed to Linux in MHz */
#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
#undef CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND \
"tftpboot; " \
"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
"bootm"
#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CONFIG_STATUS_LED 1 /* Status LED enabled */
#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
#define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */
#endif
#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
/*
* BOOTP options
*/
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_NISDOMAIN
#undef CONFIG_MAC_PARTITION
#undef CONFIG_DOS_PARTITION
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_PING
#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
/* #define CONFIG_CMD_NAND */ /* disabled */
#endif
#define CONFIG_BOARD_EARLY_INIT_F 1
#define CONFIG_MISC_INIT_R
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
#define CONFIG_SYS_MEMTEST_START 0x0300000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x0700000 /* 3 ... 7 MB in DRAM */
#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
/*
* Low Level Configuration Settings
* (address mappings, register initial values, etc.)
* You should know what you are doing if you make changes here.
*/
/*-----------------------------------------------------------------------
* Internal Memory Mapped Register
*/
#define CONFIG_SYS_IMMR 0xFF000000
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
#define CONFIG_SYS_INIT_RAM_SIZE 0x3000 /* Size of used area in DPRAM */
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
*/
#define CONFIG_SYS_SDRAM_BASE 0x00000000
#define CONFIG_SYS_FLASH_BASE 0x40000000
#if defined(DEBUG)
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
#else
#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
#endif
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
* FLASH organization
*/
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
#define CONFIG_SYS_MAX_FLASH_SECT 8 /* max number of sectors on one chip */
#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_SECT_SIZE 0x10000
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x60000)
#define CONFIG_ENV_SIZE 0x4000
#define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE + 0x70000)
#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
/*-----------------------------------------------------------------------
* SYPCR - System Protection Control 11-9
* SYPCR can only be written once after reset!
*-----------------------------------------------------------------------
* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
*/
#if defined(CONFIG_WATCHDOG)
#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
#else
#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
#endif
/*-----------------------------------------------------------------------
* SIUMCR - SIU Module Configuration 11-6
*-----------------------------------------------------------------------
* PCMCIA config., multi-function pin tri-state
*/
#ifndef CONFIG_CAN_DRIVER
#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC)
#else /* we must activate GPL5 in the SIUMCR for CAN */
#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC)
#endif /* CONFIG_CAN_DRIVER */
/*-----------------------------------------------------------------------
* TBSCR - Time Base Status and Control 11-26
*-----------------------------------------------------------------------
* Clear Reference Interrupt Status, Timebase freezing enabled
*/
#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
/*-----------------------------------------------------------------------
* RTCSC - Real-Time Clock Status and Control Register 11-27
*-----------------------------------------------------------------------
*/
#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
/*-----------------------------------------------------------------------
* PISCR - Periodic Interrupt Status and Control 11-31
*-----------------------------------------------------------------------
* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
*/
#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
/*-----------------------------------------------------------------------
* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
*-----------------------------------------------------------------------
* Reset PLL lock status sticky bit, timer expired status bit and timer
* interrupt status bit
*
*
*-----------------------------------------------------------------------
* SCCR - System Clock and reset Control Register 15-27
*-----------------------------------------------------------------------
* Set clock output, timebase and RTC source and divider,
* power management and some other internal clocks
*/
#define SCCR_MASK SCCR_EBDF11
#if CONFIG_8xx_GCLK_FREQ == 50000000
#define CONFIG_SYS_PLPRCR ( ((5 - 1) << PLPRCR_MF_SHIFT) | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
#define CONFIG_SYS_SCCR (SCCR_TBS | \
SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
SCCR_DFALCD00)
#elif CONFIG_8xx_GCLK_FREQ == 80000000
#define CONFIG_SYS_PLPRCR ( ((8 - 1) << PLPRCR_MF_SHIFT) | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
#define CONFIG_SYS_SCCR (SCCR_TBS | \
SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
SCCR_DFALCD00 | SCCR_EBDF01)
#endif
/*-----------------------------------------------------------------------
*
*-----------------------------------------------------------------------
*
*/
/*#define CONFIG_SYS_DER 0x2002000F*/
#define CONFIG_SYS_DER 0
/*
* Init Memory Controller:
*
* BR0/1 and OR0/1 (FLASH)
*/
#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
/* used to re-map FLASH both when starting from SRAM or FLASH:
* restrict access enough to keep SRAM working (if any)
* but not too much to meddle with FLASH accesses
*/
#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */
#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_BI | OR_SCY_5_CLK | OR_TRLX)
#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
/*
* BR3 and OR3 (SDRAM)
*
*/
#define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank #0 */
#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
#define CONFIG_SYS_OR_TIMING_SDRAM (OR_CSNT_SAM | OR_G5LS)
#define CONFIG_SYS_OR3_PRELIM ((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) | CONFIG_SYS_OR_TIMING_SDRAM)
#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_PS_32 | BR_V)
/*
* Memory Periodic Timer Prescaler
*/
/* periodic timer for refresh */
#define CONFIG_SYS_MAMR_PTA 208
/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
/*
* MAMR settings for SDRAM
*/
/* 9 column SDRAM */
#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
/* Ethernet at SCC2 */
#define CONFIG_SCC2_ENET
/****************************************************************/
#define DSP_SIZE 0x00010000 /* 64K */
#define FPGA_SIZE 0x00010000 /* 64K */
#define DSP0_BASE 0xF1000000
#define DSP1_BASE (DSP0_BASE + DSP_SIZE)
#define FPGA_BASE (DSP1_BASE + DSP_SIZE)
#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
#define ER_SIZE 0x00010000 /* 64K */
#define ER_BASE (FPGA_BASE + FPGA_SIZE)
#define NAND_SIZE 0x00010000 /* 64K */
#define NAND_BASE (ER_BASE + ER_SIZE)
#endif
/****************************************************************/
#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
#define STATUS_LED_BIT 0x00000001 /* bit 31 */
#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
#define STATUS_LED_STATE STATUS_LED_BLINKING
#define STATUS_LED_BIT1 0x00000002 /* bit 30 */
#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2)
#define STATUS_LED_STATE1 STATUS_LED_OFF
#define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */
#define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
#endif
/*****************************************************************************/
#ifndef __ASSEMBLY__
#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
/* LEDs */
/* last value written to the external register; we cannot read back */
extern unsigned int last_er_val;
/* led_id_t is unsigned long mask */
typedef unsigned int led_id_t;
static inline void __led_init(led_id_t mask, int state)
{
unsigned int new_er_val;
if (state)
new_er_val = last_er_val & ~mask;
else
new_er_val = last_er_val | mask;
*(volatile unsigned int *)ER_BASE = new_er_val;
last_er_val = new_er_val;
}
static inline void __led_toggle(led_id_t mask)
{
unsigned int new_er_val;
new_er_val = last_er_val ^ mask;
*(volatile unsigned int *)ER_BASE = new_er_val;
last_er_val = new_er_val;
}
static inline void __led_set(led_id_t mask, int state)
{
unsigned int new_er_val;
if (state)
new_er_val = last_er_val & ~mask;
else
new_er_val = last_er_val | mask;
*(volatile unsigned int *)ER_BASE = new_er_val;
last_er_val = new_er_val;
}
/* MAX3100 console */
#define MAX3100_SPI_RXD_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat)
#define MAX3100_SPI_RXD_BIT 0x00000008
#define MAX3100_SPI_TXD_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat)
#define MAX3100_SPI_TXD_BIT 0x00000004
#define MAX3100_SPI_CLK_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat)
#define MAX3100_SPI_CLK_BIT 0x00000002
#define MAX3100_CS_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat)
#define MAX3100_CS_BIT 0x0010
#endif
#endif
/*************************************************************************************************/
#endif /* __CONFIG_H */

23
include/status_led.h
Unescape View File

@ -122,29 +122,6 @@ void status_led_set (int led, int state);
* filling this file up with lots of custom board stuff.
*/
/***** NetVia ********************************************************/
#elif defined(CONFIG_NETVIA)
#if !defined(CONFIG_NETVIA_VERSION) || CONFIG_NETVIA_VERSION == 1
#define STATUS_LED_PAR im_ioport.iop_pdpar
#define STATUS_LED_DIR im_ioport.iop_pddir
#undef STATUS_LED_ODR
#define STATUS_LED_DAT im_ioport.iop_pddat
# define STATUS_LED_BIT 0x0080 /* PD.8 */
# define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
# define STATUS_LED_STATE STATUS_LED_BLINKING
# define STATUS_LED_BIT1 0x0040 /* PD.9 */
# define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2)
# define STATUS_LED_STATE1 STATUS_LED_OFF
# define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */
# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
#endif
/***** CMI ********************************************************/
#elif defined(CONFIG_CMI)
# define STATUS_LED_DIR im_mios.mios_mpiosm32ddr

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