From f02c1f695e13ee0ce01f111952ceaac094700de1 Mon Sep 17 00:00:00 2001
From: Marek Vasut <marek.vasut+renesas@gmail.com>
Date: Fri, 24 Aug 2018 21:43:17 +0200
Subject: [PATCH] sh: tmu: Clean up register usage

The code uses all in all three TMU registers, drop the massive
register layout structures and just define the required timer
registers and use them throughout the code.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
---
 arch/sh/lib/time.c | 54 +++++++++++-------------------------------------------
 1 file changed, 11 insertions(+), 43 deletions(-)

diff --git a/arch/sh/lib/time.c b/arch/sh/lib/time.c
index a650c94..d531a49 100644
--- a/arch/sh/lib/time.c
+++ b/arch/sh/lib/time.c
@@ -15,52 +15,20 @@
 #include <asm/io.h>
 
 #if defined(CONFIG_CPU_SH3)
-struct tmu_regs {
-	u8	tocr;
-	u8	reserved0;
-	u8	tstr;
-	u8	reserved1;
-	u32	tcor0;
-	u32	tcnt0;
-	u16	tcr0;
-	u16	reserved2;
-	u32	tcor1;
-	u32	tcnt1;
-	u16	tcr1;
-	u16	reserved3;
-	u32	tcor2;
-	u32	tcnt2;
-	u16	tcr2;
-	u16	reserved4;
-	u32	tcpr2;
-};
+#define TSTR	0x2
+#define TCNT0	0x8
+#define TCR0	0xc
 #endif /* CONFIG_CPU_SH3 */
 
 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_RMOBILE)
-struct tmu_regs {
-	u32	reserved;
-	u8	tstr;
-	u8	reserved2[3];
-	u32	tcor0;
-	u32	tcnt0;
-	u16	tcr0;
-	u16	reserved3;
-	u32	tcor1;
-	u32	tcnt1;
-	u16	tcr1;
-	u16	reserved4;
-	u32	tcor2;
-	u32	tcnt2;
-	u16	tcr2;
-	u16	reserved5;
-};
+#define TSTR	0x4
+#define TCNT0	0xc
+#define TCR0	0x10
 #endif /* CONFIG_CPU_SH4 */
 
-#define TCR_TPSC 0x07
+#define TCR_TPSC	0x07
 #define TSTR_STR0	BIT(0)
 
-static struct tmu_regs *tmu = (struct tmu_regs *)TMU_BASE;
-
 unsigned long get_tbclk(void)
 {
 #ifdef CONFIG_RCAR_GEN2
@@ -72,14 +40,14 @@ unsigned long get_tbclk(void)
 
 unsigned long timer_read_counter(void)
 {
-	return ~readl(&tmu->tcnt0);
+	return ~readl(TMU_BASE + TCNT0);
 }
 
 int timer_init(void)
 {
-	writew(readw(&tmu->tcr0) & ~TCR_TPSC, &tmu->tcr0);
-	writeb(readb(&tmu->tstr) & ~TSTR_STR0, &tmu->tstr);
-	writeb(readb(&tmu->tstr) | TSTR_STR0, &tmu->tstr);
+	writew(readw(TMU_BASE + TCR0) & ~TCR_TPSC, TMU_BASE + TCR0);
+	writeb(readb(TMU_BASE + TSTR) & ~TSTR_STR0, TMU_BASE + TSTR);
+	writeb(readb(TMU_BASE + TSTR) | TSTR_STR0, TMU_BASE + TSTR);
 
 	return 0;
 }