From 1947c2d2a08fb07330d15fc30416969afbe61bbc Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Thu, 22 Feb 2018 12:30:41 +0100 Subject: [PATCH 01/51] bootcount: flush after storing the bootcounter If the bootcounter address is in a cached memory, a flush of dcache must occur after updateing the bootcounter. Issue found on i.MX6 where bootcounter is put into the internal (cached) IRAM. Signed-off-by: Stefano Babic --- drivers/bootcount/bootcount.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/bootcount/bootcount.c b/drivers/bootcount/bootcount.c index e00d81c..a3162c9 100644 --- a/drivers/bootcount/bootcount.c +++ b/drivers/bootcount/bootcount.c @@ -18,6 +18,9 @@ __weak void bootcount_store(ulong a) raw_bootcount_store(reg, a); raw_bootcount_store(reg + 4, BOOTCOUNT_MAGIC); #endif /* defined(CONFIG_SYS_BOOTCOUNT_SINGLEWORD */ + flush_dcache_range(CONFIG_SYS_BOOTCOUNT_ADDR, + CONFIG_SYS_BOOTCOUNT_ADDR + + CONFIG_SYS_CACHELINE_SIZE); } __weak ulong bootcount_load(void) From c7f367bc8d6b1b5da79aa430c4449c9f505b9577 Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Wed, 30 May 2018 19:01:44 +0200 Subject: [PATCH 02/51] mtd: nand: mxs_nand: add device tree support for i.MX 6 Support i.MX 6 NAND GPMI driver data from device tree. Signed-off-by: Stefan Agner --- drivers/mtd/nand/mxs_nand_dt.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/mtd/nand/mxs_nand_dt.c b/drivers/mtd/nand/mxs_nand_dt.c index f89eb09..44dec5d 100644 --- a/drivers/mtd/nand/mxs_nand_dt.c +++ b/drivers/mtd/nand/mxs_nand_dt.c @@ -21,12 +21,20 @@ struct mxs_nand_dt_data { unsigned int max_ecc_strength_supported; }; +static const struct mxs_nand_dt_data mxs_nand_imx6q_data = { + .max_ecc_strength_supported = 40, +}; + static const struct mxs_nand_dt_data mxs_nand_imx7d_data = { .max_ecc_strength_supported = 62, }; static const struct udevice_id mxs_nand_dt_ids[] = { { + .compatible = "fsl,imx6q-gpmi-nand", + .data = (unsigned long)&mxs_nand_imx6q_data, + }, + { .compatible = "fsl,imx7d-gpmi-nand", .data = (unsigned long)&mxs_nand_imx7d_data, }, From 23eaf4180f9ff6f3898e0199e56cfcb563d2eb74 Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Wed, 30 May 2018 19:01:45 +0200 Subject: [PATCH 03/51] imx: add macro to detect whether USB has been initialized This macro allows to detect whether the boot ROM initialized USB already (serial downloader). This is helpful to reliably detect if the system has been recovered via USB serial downloader. Signed-off-by: Stefan Agner Acked-by: Marcel Ziswiler --- arch/arm/include/asm/arch-mx6/imx-regs.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index 4314392..4f01b20 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -996,5 +996,12 @@ struct pwm_regs { u32 pr; u32 cnr; }; + +/* + * If ROM fail back to USB recover mode, USBPH0_PWD will be clear to use USB + * If boot from the other mode, USB0_PWD will keep reset value + */ +#define is_boot_from_usb(void) (!(readl(USB_PHY0_BASE_ADDR) & (1<<20))) + #endif /* __ASSEMBLER__*/ #endif /* __ASM_ARCH_MX6_IMX_REGS_H__ */ From 55f34f3a9ef0caad100793a2cd0ea0b8875a67a1 Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Wed, 30 May 2018 19:01:46 +0200 Subject: [PATCH 04/51] ARM: dts: imx6ull: use same compatible string as Linux is using The GPMI NAND IP seems to be the same as used in i.MX 6Quad. Use the fsl,imx6q-gpmi-nand compatible string like Linux devices trees are. Signed-off-by: Stefan Agner --- arch/arm/dts/imx6ull.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/dts/imx6ull.dtsi b/arch/arm/dts/imx6ull.dtsi index f8ec649..97236d8 100644 --- a/arch/arm/dts/imx6ull.dtsi +++ b/arch/arm/dts/imx6ull.dtsi @@ -190,7 +190,7 @@ }; gpmi: gpmi-nand@01806000{ - compatible = "fsl,imx6ull-gpmi-nand", "fsl, imx6ul-gpmi-nand"; + compatible = "fsl,imx6q-gpmi-nand"; #address-cells = <1>; #size-cells = <1>; reg = <0x01806000 0x2000>, <0x01808000 0x4000>; From d826b8751925aa535fd692f157b6d0dbfbea490a Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Wed, 30 May 2018 19:01:47 +0200 Subject: [PATCH 05/51] board: toradex: add new and upcoming SKUs Signed-off-by: Stefan Agner --- board/toradex/common/tdx-cfg-block.c | 7 +++++++ board/toradex/common/tdx-cfg-block.h | 7 +++++++ 2 files changed, 14 insertions(+) diff --git a/board/toradex/common/tdx-cfg-block.c b/board/toradex/common/tdx-cfg-block.c index f6231ff..57edb6c 100644 --- a/board/toradex/common/tdx-cfg-block.c +++ b/board/toradex/common/tdx-cfg-block.c @@ -91,6 +91,13 @@ const char * const toradex_modules[] = { [33] = "Colibri iMX7 Dual 512MB", [34] = "Apalis TK1 2GB", [35] = "Apalis iMX6 Dual 1GB IT", + [36] = "Colibri iMX6ULL 256MB", + [37] = "Apalis iMX8 QuadMax 4GB Wi-Fi / Bluetooth", + [38] = "Colibri iMX8X", + [39] = "Colibri iMX7 Dual 1GB (eMMC)", + [40] = "Colibri iMX6ULL 512MB Wi-Fi / Bluetooth IT", + [41] = "Colibri iMX7 Dual 512MB EPDC", + [42] = "Apalis TK1 4GB", }; #ifdef CONFIG_TDX_CFG_BLOCK_IS_IN_MMC diff --git a/board/toradex/common/tdx-cfg-block.h b/board/toradex/common/tdx-cfg-block.h index 29b933c..da60e78 100644 --- a/board/toradex/common/tdx-cfg-block.h +++ b/board/toradex/common/tdx-cfg-block.h @@ -54,6 +54,13 @@ enum { COLIBRI_IMX7D, APALIS_TK1_2GB, APALIS_IMX6D_IT, + COLIBRI_IMX6ULL, + APALIS_IMX8QM, /* 37 */ + COLIBRI_IMX8X, + COLIBRI_IMX7D_EMMC, + COLIBRI_IMX6ULL_WIFI_BT_IT, /* 40 */ + COLIBRI_IMX7D_EPDC, + APALIS_TK1_4GB, }; extern const char * const toradex_modules[]; From 31b1e17f444c013083d6b09864f2f63067506492 Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Wed, 30 May 2018 19:01:48 +0200 Subject: [PATCH 06/51] board: toradex: add Colibri iMX6ULL support Add support for the Colibri iMX6ULL module which comes with on-board raw NAND. Signed-off-by: Stefan Agner --- arch/arm/dts/imx6ull-colibri.dts | 550 ++++++++++++++++++++++++ arch/arm/mach-imx/mx6/Kconfig | 8 + board/toradex/colibri-imx6ull/Kconfig | 29 ++ board/toradex/colibri-imx6ull/MAINTAINERS | 10 + board/toradex/colibri-imx6ull/Makefile | 4 + board/toradex/colibri-imx6ull/colibri-imx6ull.c | 408 ++++++++++++++++++ board/toradex/colibri-imx6ull/imximage.cfg | 106 +++++ configs/colibri-imx6ull_defconfig | 76 ++++ include/configs/colibri-imx6ull.h | 199 +++++++++ 9 files changed, 1390 insertions(+) create mode 100644 arch/arm/dts/imx6ull-colibri.dts create mode 100644 board/toradex/colibri-imx6ull/Kconfig create mode 100644 board/toradex/colibri-imx6ull/MAINTAINERS create mode 100644 board/toradex/colibri-imx6ull/Makefile create mode 100644 board/toradex/colibri-imx6ull/colibri-imx6ull.c create mode 100644 board/toradex/colibri-imx6ull/imximage.cfg create mode 100644 configs/colibri-imx6ull_defconfig create mode 100644 include/configs/colibri-imx6ull.h diff --git a/arch/arm/dts/imx6ull-colibri.dts b/arch/arm/dts/imx6ull-colibri.dts new file mode 100644 index 0000000..95c67be --- /dev/null +++ b/arch/arm/dts/imx6ull-colibri.dts @@ -0,0 +1,550 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2018 Toradex AG + */ + +/dts-v1/; +#include +#include "imx6ull.dtsi" + +/ { + model = "Toradex Colibri iMX6ULL"; + compatible = "toradex,imx6ull-colibri", "fsl,imx6ull"; + + chosen { + stdout-path = &uart1; + }; + + reg_module_3v3: regulator-module-3v3 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-name = "+V3.3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_module_3v3_avdd: regulator-module-3v3-avdd { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-name = "+V3.3_AVDD_AUDIO"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_sd1_vmmc: regulator-sd1-vmmc { + compatible = "regulator-gpio"; + gpio = <&gpio5 9 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_snvs_reg_sd>; + regulator-always-on; + regulator-name = "+V3.3_1.8_SD"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + states = <1800000 0x1 3300000 0x0>; + vin-supply = <®_module_3v3>; + }; +}; + +&adc1 { + num-channels = <10>; + vref-supply = <®_module_3v3_avdd>; +}; + +/* Colibri SPI */ +&ecspi1 { + cs-gpios = <&gpio3 26 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2>; + phy-mode = "rmii"; + phy-handle = <ðphy1>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy1: ethernet-phy@2 { + compatible = "ethernet-phy-ieee802.3-c22"; + max-speed = <100>; + reg = <2>; + }; + }; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + nand-on-flash-bbt; + nand-ecc-mode = "hw"; + nand-ecc-strength = <8>; + nand-ecc-step-size = <512>; + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + sda-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>; + scl-gpios = <&gpio1 28 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&i2c2 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + sda-gpios = <&gpio1 31 GPIO_ACTIVE_LOW>; + scl-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; + status = "okay"; + + ad7879@2c { + compatible = "adi,ad7879-1"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_snvs_ad7879_int>; + reg = <0x2c>; + interrupt-parent = <&gpio5>; + interrupts = <7 IRQ_TYPE_EDGE_FALLING>; + touchscreen-max-pressure = <4096>; + adi,resistance-plate-x = <120>; + adi,first-conversion-delay = /bits/ 8 <3>; + adi,acquisition-time = /bits/ 8 <1>; + adi,median-filter-size = /bits/ 8 <2>; + adi,averaging = /bits/ 8 <1>; + adi,conversion-interval = /bits/ 8 <255>; + }; +}; + +&lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif_dat + &pinctrl_lcdif_ctrl>; +}; + +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + #pwm-cells = <3>; +}; + +&pwm5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm5>; + #pwm-cells = <3>; +}; + +&pwm6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm6>; + #pwm-cells = <3>; +}; + +&pwm7 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm7>; + #pwm-cells = <3>; +}; + +&sdma { + status = "okay"; +}; + +&snvs_pwrkey { + status = "disabled"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_ctrl1>; + fsl,uart-has-rtscts; + fsl,dte-mode; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + fsl,uart-has-rtscts; + fsl,dte-mode; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + fsl,dte-mode; +}; + +&usbotg1 { + dr_mode = "otg"; + srp-disable; + hnp-disable; + adp-disable; +}; + +&usbotg2 { + dr_mode = "host"; +}; + +&usdhc1 { + assigned-clocks = <&clks IMX6UL_CLK_USDHC1_SEL>, <&clks IMX6UL_CLK_USDHC1>; + assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>; + assigned-clock-rates = <0>, <198000000>; +}; + +&iomuxc { + pinctrl_gpio1: gpio1-grp { + fsl,pins = < + MX6UL_PAD_ENET1_RX_DATA0__GPIO2_IO00 0x74 /* SODIMM 55 */ + MX6UL_PAD_ENET1_RX_DATA1__GPIO2_IO01 0x74 /* SODIMM 63 */ + MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0X14 /* SODIMM 77 */ + MX6UL_PAD_JTAG_TCK__GPIO1_IO14 0x14 /* SODIMM 99 */ + MX6UL_PAD_NAND_CE1_B__GPIO4_IO14 0x14 /* SODIMM 133 */ + MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24 0x14 /* SODIMM 135 */ + MX6UL_PAD_UART3_CTS_B__GPIO1_IO26 0x14 /* SODIMM 100 */ + MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15 0x14 /* SODIMM 102 */ + MX6UL_PAD_ENET1_RX_ER__GPIO2_IO07 0x14 /* SODIMM 104 */ + MX6UL_PAD_UART3_RTS_B__GPIO1_IO27 0x14 /* SODIMM 186 */ + >; + }; + + pinctrl_gpio2: gpio2-grp { /* Camera */ + fsl,pins = < + MX6UL_PAD_CSI_DATA04__GPIO4_IO25 0x74 /* SODIMM 69 */ + MX6UL_PAD_CSI_MCLK__GPIO4_IO17 0x14 /* SODIMM 75 */ + MX6UL_PAD_CSI_DATA06__GPIO4_IO27 0x14 /* SODIMM 85 */ + MX6UL_PAD_CSI_PIXCLK__GPIO4_IO18 0x14 /* SODIMM 96 */ + MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x14 /* SODIMM 98 */ + >; + }; + + pinctrl_gpio3: gpio3-grp { /* CAN2 */ + fsl,pins = < + MX6UL_PAD_ENET1_RX_EN__GPIO2_IO02 0x14 /* SODIMM 178 */ + MX6UL_PAD_ENET1_TX_DATA0__GPIO2_IO03 0x14 /* SODIMM 188 */ + >; + }; + + pinctrl_gpio4: gpio4-grp { + fsl,pins = < + MX6UL_PAD_CSI_DATA07__GPIO4_IO28 0x74 /* SODIMM 65 */ + >; + }; + + pinctrl_gpio5: gpio5-grp { /* ATMEL MXT TOUCH */ + fsl,pins = < + MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x74 /* SODIMM 106 */ + >; + }; + + pinctrl_gpio6: gpio6-grp { /* Wifi pins */ + fsl,pins = < + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x14 /* SODIMM 89 */ + MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x14 /* SODIMM 79 */ + MX6UL_PAD_CSI_VSYNC__GPIO4_IO19 0x14 /* SODIMM 81 */ + MX6UL_PAD_CSI_DATA03__GPIO4_IO24 0x14 /* SODIMM 97 */ + MX6UL_PAD_CSI_DATA00__GPIO4_IO21 0x14 /* SODIMM 101 */ + MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x14 /* SODIMM 103 */ + MX6UL_PAD_CSI_HSYNC__GPIO4_IO20 0x14 /* SODIMM 94 */ + >; + }; + + pinctrl_can_int: canint-grp { + fsl,pins = < + MX6UL_PAD_ENET1_TX_DATA1__GPIO2_IO04 0X14 /* SODIMM 73 */ + >; + }; + + pinctrl_enet2: enet2-grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 + MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 + MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 + MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 + MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 + MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 + >; + }; + + pinctrl_ecspi1_cs: ecspi1-cs-grp { + fsl,pins = < + MX6UL_PAD_LCD_DATA21__GPIO3_IO26 0x000a0 + >; + }; + + pinctrl_ecspi1: ecspi1-grp { + fsl,pins = < + MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK 0x000a0 + MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI 0x000a0 + MX6UL_PAD_LCD_DATA23__ECSPI1_MISO 0x100a0 + >; + }; + + pinctrl_flexcan2: flexcan2-grp { + fsl,pins = < + MX6UL_PAD_ENET1_TX_DATA0__FLEXCAN2_RX 0x1b020 + MX6UL_PAD_ENET1_RX_EN__FLEXCAN2_TX 0x1b020 + >; + }; + + pinctrl_gpio_bl_on: gpio-bl-on-grp { + fsl,pins = < + MX6UL_PAD_JTAG_TMS__GPIO1_IO11 0x000a0 + >; + }; + + pinctrl_gpmi_nand: gpmi-nand-grp { + fsl,pins = < + MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x100a9 + MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x100a9 + MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x100a9 + MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x100a9 + MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x100a9 + MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x100a9 + MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x100a9 + MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x100a9 + MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x100a9 + MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x100a9 + MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x100a9 + MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x100a9 + MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x100a9 + MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x100a9 + >; + }; + + pinctrl_i2c1: i2c1-grp { + fsl,pins = < + MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 + MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 + >; + }; + + pinctrl_i2c1_gpio: i2c1-gpio-grp { + fsl,pins = < + MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x4001b8b0 + MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x4001b8b0 + >; + }; + + pinctrl_i2c2: i2c2-grp { + fsl,pins = < + MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0 + MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0 + >; + }; + + pinctrl_i2c2_gpio: i2c2-gpio-grp { + fsl,pins = < + MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x4001b8b0 + MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x4001b8b0 + >; + }; + + pinctrl_lcdif_dat: lcdif-dat-grp { + fsl,pins = < + MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x00079 + MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x00079 + MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x00079 + MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x00079 + MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x00079 + MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x00079 + MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x00079 + MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x00079 + MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x00079 + MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x00079 + MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x00079 + MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x00079 + MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x00079 + MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x00079 + MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x00079 + MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x00079 + MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x00079 + MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x00079 + >; + }; + + pinctrl_lcdif_ctrl: lcdif-ctrl-grp { + fsl,pins = < + MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x00079 + MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x00079 + MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x00079 + MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x00079 + >; + }; + + pinctrl_pwm4: pwm4-grp { + fsl,pins = < + MX6UL_PAD_NAND_WP_B__PWM4_OUT 0x00079 + >; + }; + + pinctrl_pwm5: pwm5-grp { + fsl,pins = < + MX6UL_PAD_NAND_DQS__PWM5_OUT 0x00079 + >; + }; + + pinctrl_pwm6: pwm6-grp { + fsl,pins = < + MX6UL_PAD_ENET1_TX_EN__PWM6_OUT 0x00079 + >; + }; + + pinctrl_pwm7: pwm7-grp { + fsl,pins = < + MX6UL_PAD_ENET1_TX_CLK__PWM7_OUT 0x00079 + >; + }; + + pinctrl_uart1: uart1-grp { + fsl,pins = < + MX6UL_PAD_UART1_TX_DATA__UART1_DTE_RX 0x1b0b1 + MX6UL_PAD_UART1_RX_DATA__UART1_DTE_TX 0x1b0b1 + MX6UL_PAD_UART1_RTS_B__UART1_DTE_CTS 0x1b0b1 + MX6UL_PAD_UART1_CTS_B__UART1_DTE_RTS 0x1b0b1 + >; + }; + + pinctrl_uart1_ctrl1: uart1-ctrl1-grp { /* Additional DTR, DCD */ + fsl,pins = < + MX6UL_PAD_JTAG_TDI__GPIO1_IO13 0x1b0b1 /* DCD */ + MX6UL_PAD_LCD_DATA18__GPIO3_IO23 0x1b0b1 /* DSR */ + MX6UL_PAD_JTAG_TDO__GPIO1_IO12 0x1b0b1 /* DTR */ + MX6UL_PAD_LCD_DATA19__GPIO3_IO24 0x1b0b1 /* RI */ + >; + }; + + pinctrl_uart2: uart2-grp { + fsl,pins = < + MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX 0x1b0b1 + MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x1b0b1 + MX6UL_PAD_UART2_CTS_B__UART2_DTE_RTS 0x1b0b1 + MX6UL_PAD_UART2_RTS_B__UART2_DTE_CTS 0x1b0b1 + >; + }; + pinctrl_uart5: uart5-grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO04__UART5_DTE_RX 0x1b0b1 + MX6UL_PAD_GPIO1_IO05__UART5_DTE_TX 0x1b0b1 + >; + }; + + pinctrl_usbh_reg: gpio-usbh-reg { + fsl,pins = < + MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x1b0b1 /* SODIMM 129 USBH PEN */ + >; + }; + + pinctrl_usdhc1: usdhc1-grp { + fsl,pins = < + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x17059 + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x10059 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhz-grp { + fsl,pins = < + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x170b9 + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x100b9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhz-grp { + fsl,pins = < + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x170f9 + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x100f9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc2: usdhc2-grp { + fsl,pins = < + MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x17059 + MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x17059 + MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x17059 + MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x17059 + MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x17059 + MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x17059 + >; + }; +}; + +&iomuxc_snvs { + pinctrl_snvs_gpio1: snvs-gpio1-grp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x14 /* SODIMM 93 */ + MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x14 /* SODIMM 95 */ + MX6ULL_PAD_BOOT_MODE0__GPIO5_IO10 0x74 /* SODIMM 105 */ + MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x14 /* SODIMM 131 USBH OC */ + MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x74 /* SODIMM 138 */ + >; + }; + + pinctrl_snvs_gpio2: snvs-gpio2-grp { /* ATMEL MXT TOUCH */ + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x74 /* SODIMM 107 */ + >; + }; + + pinctrl_snvs_gpio3: snvs-gpio3-grp { /* Wifi pins */ + fsl,pins = < + MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x14 /* SODIMM 127 */ + >; + }; + + pinctrl_snvs_ad7879_int: snvs-ad7879-int { /* TOUCH Interrupt */ + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x1b0b0 + >; + }; + + pinctrl_snvs_reg_sd: snvs-reg-sd-grp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x4001b8b0 + >; + }; + + pinctrl_snvs_usbc_det: snvs-usbc-det-grp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0 + >; + }; + + pinctrl_snvs_gpiokeys: snvs-gpiokeys-grp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x130b0 + >; + }; + + pinctrl_snvs_usdhc1_cd: snvs-usdhc1-cd-grp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0b0 /* CD */ + >; + }; + + pinctrl_snvs_wifi_pdn: snvs-wifi-pdn-grp { + fsl,pins = < + MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x14 + >; + }; +}; + diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index 521fad7..3c87ece 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -148,6 +148,13 @@ config TARGET_COLIBRI_IMX6 select DM_SERIAL select DM_THERMAL +config TARGET_COLIBRI_IMX6ULL + bool "Toradex Colibri iMX6ULL" + select BOARD_LATE_INIT + select DM + select DM_THERMAL + select MX6ULL + config TARGET_DHCOMIMX6 bool "dh_imx6" select MX6QDL @@ -530,6 +537,7 @@ source "board/tbs/tbs2910/Kconfig" source "board/tqc/tqma6/Kconfig" source "board/toradex/apalis_imx6/Kconfig" source "board/toradex/colibri_imx6/Kconfig" +source "board/toradex/colibri-imx6ull/Kconfig" source "board/k+p/kp_imx6q_tpc/Kconfig" source "board/udoo/Kconfig" source "board/udoo/neo/Kconfig" diff --git a/board/toradex/colibri-imx6ull/Kconfig b/board/toradex/colibri-imx6ull/Kconfig new file mode 100644 index 0000000..3ce9885 --- /dev/null +++ b/board/toradex/colibri-imx6ull/Kconfig @@ -0,0 +1,29 @@ +if TARGET_COLIBRI_IMX6ULL + +config SYS_BOARD + default "colibri-imx6ull" + +config SYS_VENDOR + default "toradex" + +config SYS_CONFIG_NAME + default "colibri-imx6ull" + +config TDX_CFG_BLOCK + default y + +config TDX_HAVE_NAND + default y + +config TDX_CFG_BLOCK_OFFSET + default "2048" + +config TDX_CFG_BLOCK_OFFSET2 + default "133120" + +config TDX_CFG_BLOCK_2ND_ETHADDR + default y + +source "board/toradex/common/Kconfig" + +endif diff --git a/board/toradex/colibri-imx6ull/MAINTAINERS b/board/toradex/colibri-imx6ull/MAINTAINERS new file mode 100644 index 0000000..7cda555 --- /dev/null +++ b/board/toradex/colibri-imx6ull/MAINTAINERS @@ -0,0 +1,10 @@ +Colibri iMX6ULL +M: Stefan Agner +M: Toradex ARM Support +W: http://developer.toradex.com/software/linux/linux-software +W: https://www.toradex.com/community +S: Maintained +F: arch/arm/dts/imx6ull-colibri.dts +F: board/toradex/colibri-imx6ull/ +F: configs/colibri-imx6ull_defconfig +F: include/configs/colibri-imx6ull.h diff --git a/board/toradex/colibri-imx6ull/Makefile b/board/toradex/colibri-imx6ull/Makefile new file mode 100644 index 0000000..f478e68 --- /dev/null +++ b/board/toradex/colibri-imx6ull/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0+ +# Copyright (C) 2018 Toradex AG + +obj-y := colibri-imx6ull.o diff --git a/board/toradex/colibri-imx6ull/colibri-imx6ull.c b/board/toradex/colibri-imx6ull/colibri-imx6ull.c new file mode 100644 index 0000000..fcb49a0 --- /dev/null +++ b/board/toradex/colibri-imx6ull/colibri-imx6ull.c @@ -0,0 +1,408 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Toradex AG + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../common/tdx-common.h" + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ + PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) +#define ENET_PAD_CTRL_MII (PAD_CTL_DSE_40ohm) + +#define ENET_RX_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_48ohm) + +#define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | \ + PAD_CTL_DSE_48ohm) + +#define NAND_PAD_CTRL (PAD_CTL_DSE_48ohm | PAD_CTL_SRE_SLOW | PAD_CTL_HYS) + +#define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_48ohm | PAD_CTL_PUS_22K_UP) + +#define USB_CDET_GPIO IMX_GPIO_NR(7, 14) + +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); + + return 0; +} + +static iomux_v3_cfg_t const uart1_pads[] = { + MX6_PAD_UART1_TX_DATA__UART1_DTE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_UART1_RX_DATA__UART1_DTE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_UART1_RTS_B__UART1_DTE_CTS | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_UART1_CTS_B__UART1_DTE_RTS | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +#ifdef CONFIG_FSL_ESDHC +static iomux_v3_cfg_t const usdhc1_pads[] = { + MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + + MX6_PAD_SNVS_TAMPER0__GPIO5_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; +#endif + +static iomux_v3_cfg_t const usb_cdet_pads[] = { + MX6_PAD_SNVS_TAMPER2__GPIO5_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +#ifdef CONFIG_NAND_MXS +static iomux_v3_cfg_t const gpmi_pads[] = { + MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(NAND_PAD_READY0_CTRL), +}; + +static void setup_gpmi_nand(void) +{ + imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads)); + + setup_gpmi_io_clk((3 << MXC_CCM_CSCDR1_BCH_PODF_OFFSET) | + (3 << MXC_CCM_CSCDR1_GPMI_PODF_OFFSET)); +} +#endif + +#ifdef CONFIG_VIDEO_MXS +static iomux_v3_cfg_t const lcd_pads[] = { + MX6_PAD_LCD_CLK__LCDIF_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_ENABLE__LCDIF_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_HSYNC__LCDIF_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_CLK__LCDIF_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA00__LCDIF_DATA00 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA01__LCDIF_DATA01 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA02__LCDIF_DATA02 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA03__LCDIF_DATA03 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA04__LCDIF_DATA04 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA05__LCDIF_DATA05 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA06__LCDIF_DATA06 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA07__LCDIF_DATA07 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA08__LCDIF_DATA08 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA09__LCDIF_DATA09 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA10__LCDIF_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA11__LCDIF_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA12__LCDIF_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA13__LCDIF_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA14__LCDIF_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA15__LCDIF_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA16__LCDIF_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA17__LCDIF_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL), +}; + +static iomux_v3_cfg_t const backlight_pads[] = { + /* Backlight On */ + MX6_PAD_JTAG_TMS__GPIO1_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* Backlight PWM (multiplexed pin) */ + MX6_PAD_NAND_WP_B__GPIO4_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +#define GPIO_BL_ON IMX_GPIO_NR(1, 11) +#define GPIO_PWM_A IMX_GPIO_NR(4, 11) + +static int setup_lcd(void) +{ + imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads)); + + imx_iomux_v3_setup_multiple_pads(backlight_pads, ARRAY_SIZE(backlight_pads)); + + /* Set BL_ON */ + gpio_request(GPIO_BL_ON, "BL_ON"); + gpio_direction_output(GPIO_BL_ON, 1); + + /* Set PWM to full brightness (assuming inversed polarity) */ + gpio_request(GPIO_PWM_A, "PWM"); + gpio_direction_output(GPIO_PWM_A, 0); + + return 0; +} +#endif + +#ifdef CONFIG_FEC_MXC +static iomux_v3_cfg_t const fec2_pads[] = { + MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_PAD_CTRL(ENET_PAD_CTRL) | MUX_MODE_SION, + MX6_PAD_GPIO1_IO06__ENET2_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII), + MX6_PAD_GPIO1_IO07__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL_MII), + MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), +}; + +static void setup_iomux_fec(void) +{ + imx_iomux_v3_setup_multiple_pads(fec2_pads, ARRAY_SIZE(fec2_pads)); +} +#endif + +static void setup_iomux_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); +} + +#ifdef CONFIG_FSL_ESDHC + +#define USDHC1_CD_GPIO IMX_GPIO_NR(5, 0) + +static struct fsl_esdhc_cfg usdhc_cfg[] = { + {USDHC1_BASE_ADDR, 0, 4}, +}; + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC1_BASE_ADDR: + ret = !gpio_get_value(USDHC1_CD_GPIO); + break; + } + + return ret; +} + +int board_mmc_init(bd_t *bis) +{ + int i, ret; + + /* USDHC1 is mmc0 */ + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + imx_iomux_v3_setup_multiple_pads(usdhc1_pads, + ARRAY_SIZE(usdhc1_pads)); + gpio_request(USDHC1_CD_GPIO, "usdhc1_cd"); + gpio_direction_input(USDHC1_CD_GPIO); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + break; + default: + printf("Warning: you configured more USDHC controllers" + "(%d) than supported by the board\n", i + 1); + return -EINVAL; + } + + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + if (ret) + return ret; + } + + return 0; +} +#endif + +#ifdef CONFIG_FEC_MXC + +static int setup_fec(void) +{ + struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; + int ret; + + setup_iomux_fec(); + + /* provide the PHY clock from the i.MX 6 */ + ret = enable_fec_anatop_clock(1, ENET_50MHZ); + if (ret) + return ret; + + /* Use 50M anatop REF_CLK and output it on the ENET2_TX_CLK */ + clrsetbits_le32(&iomuxc_regs->gpr[1], + IOMUX_GPR1_FEC2_CLOCK_MUX2_SEL_MASK, + IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK); + + return 0; +} + +int board_phy_config(struct phy_device *phydev) +{ + if (phydev->drv->config) + phydev->drv->config(phydev); + return 0; +} +#endif + +int board_early_init_f(void) +{ + setup_iomux_uart(); + + return 0; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + +#ifdef CONFIG_FEC_MXC + setup_fec(); +#endif + +#ifdef CONFIG_NAND_MXS + setup_gpmi_nand(); +#endif + +#ifdef CONFIG_VIDEO_MXS + setup_lcd(); +#endif + +#ifdef CONFIG_USB_EHCI_MX6 + imx_iomux_v3_setup_multiple_pads(usb_cdet_pads, ARRAY_SIZE(usb_cdet_pads)); + gpio_request(USB_CDET_GPIO, "usb-cdet-gpio"); +#endif + + return 0; +} + +#ifdef CONFIG_CMD_BMODE +/* TODO */ +static const struct boot_mode board_boot_modes[] = { + /* 4 bit bus width */ + {"nand", MAKE_CFGVAL(0x40, 0x34, 0x00, 0x00)}, + {"sd1", MAKE_CFGVAL(0x10, 0x10, 0x00, 0x00)}, + {NULL, 0}, +}; +#endif + +int board_late_init(void) +{ + int minc, maxc; + + if (get_cpu_temp_grade(&minc, &maxc) != TEMP_COMMERCIAL) + env_set("variant", "-wifi"); + +#ifdef CONFIG_CMD_BMODE + add_board_boot_modes(board_boot_modes); +#endif + +#ifdef CONFIG_CMD_USB_SDP + if (is_boot_from_usb()) { + printf("Serial Downloader recovery mode, using sdp command\n"); + env_set("bootdelay", "0"); + env_set("bootcmd", "sdp 0"); + } +#endif /* CONFIG_CMD_USB_SDP */ + + return 0; +} + +int checkboard(void) +{ + printf("Model: Toradex Colibri iMX6ULL\n"); + + return 0; +} + +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +int ft_board_setup(void *blob, bd_t *bd) +{ +#if defined(CONFIG_FDT_FIXUP_PARTITIONS) + static struct node_info nodes[] = { + { "fsl,imx6ull-gpmi-nand", MTD_DEV_TYPE_NAND, }, + { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, }, + }; + + /* Update partition nodes using info from mtdparts env var */ + puts(" Updating MTD partitions...\n"); + fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes)); +#endif + + return ft_common_board_setup(blob, bd); +} +#endif + +#ifdef CONFIG_USB_EHCI_MX6 +static iomux_v3_cfg_t const usb_otg2_pads[] = { + MX6_PAD_GPIO1_IO02__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +int board_ehci_hcd_init(int port) +{ + switch (port) { + case 0: + break; + case 1: + imx_iomux_v3_setup_multiple_pads(usb_otg2_pads, + ARRAY_SIZE(usb_otg2_pads)); + break; + default: + return -EINVAL; + } + return 0; +} + +int board_usb_phy_mode(int port) +{ + switch (port) { + case 0: + if (gpio_get_value(USB_CDET_GPIO)) + return USB_INIT_DEVICE; + else + return USB_INIT_HOST; + case 1: + default: + return USB_INIT_HOST; + } +} +#endif + +static struct mxc_serial_platdata mxc_serial_plat = { + .reg = (struct mxc_uart *)UART1_BASE, + .use_dte = 1, +}; + +U_BOOT_DEVICE(mxc_serial) = { + .name = "serial_mxc", + .platdata = &mxc_serial_plat, +}; diff --git a/board/toradex/colibri-imx6ull/imximage.cfg b/board/toradex/colibri-imx6ull/imximage.cfg new file mode 100644 index 0000000..2ce55a6 --- /dev/null +++ b/board/toradex/colibri-imx6ull/imximage.cfg @@ -0,0 +1,106 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright (C) 2018 Toradex AG + * + * Refer doc/README.imximage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : nand + */ + +BOOT_FROM nand + +/* + * Secure boot support + */ +#ifdef CONFIG_SECURE_BOOT +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +/* Enable all clocks */ +DATA 4 0x020c4068 0xffffffff +DATA 4 0x020c406c 0xffffffff +DATA 4 0x020c4070 0xffffffff +DATA 4 0x020c4074 0xffffffff +DATA 4 0x020c4078 0xffffffff +DATA 4 0x020c407c 0xffffffff +DATA 4 0x020c4080 0xffffffff + +DATA 4 0x020E04B4 0x000C0000 +DATA 4 0x020E04AC 0x00000000 +DATA 4 0x020E027C 0x00000030 +DATA 4 0x020E0250 0x00000030 +DATA 4 0x020E024C 0x00000030 +DATA 4 0x020E0490 0x00000030 +DATA 4 0x020E0288 0x000C0030 +DATA 4 0x020E0270 0x00000000 +DATA 4 0x020E0260 0x00000030 +DATA 4 0x020E0264 0x00000030 +DATA 4 0x020E04A0 0x00000030 +DATA 4 0x020E0494 0x00020000 +DATA 4 0x020E0280 0x00000030 +DATA 4 0x020E0284 0x00000030 +DATA 4 0x020E04B0 0x00020000 +DATA 4 0x020E0498 0x00000030 +DATA 4 0x020E04A4 0x00000030 +DATA 4 0x020E0244 0x00000030 +DATA 4 0x020E0248 0x00000030 +DATA 4 0x021B001C 0x00008000 +DATA 4 0x021B0800 0xA1390003 +DATA 4 0x021B080C 0x00000004 +DATA 4 0x021B083C 0x41640158 +DATA 4 0x021B0848 0x40403237 +DATA 4 0x021B0850 0x40403C33 +DATA 4 0x021B081C 0x33333333 +DATA 4 0x021B0820 0x33333333 +DATA 4 0x021B082C 0xf3333333 +DATA 4 0x021B0830 0xf3333333 +DATA 4 0x021B08C0 0x00944009 +DATA 4 0x021B08b8 0x00000800 +DATA 4 0x021B0004 0x0002002D +DATA 4 0x021B0008 0x1B333030 +DATA 4 0x021B000C 0x676B52F3 +DATA 4 0x021B0010 0xB66D0B63 +DATA 4 0x021B0014 0x01FF00DB +DATA 4 0x021B0018 0x00201740 +DATA 4 0x021B001C 0x00008000 +DATA 4 0x021B002C 0x000026D2 +DATA 4 0x021B0030 0x006B1023 +DATA 4 0x021B0040 0x0000004F +DATA 4 0x021B0000 0x84180000 +DATA 4 0x021B0890 0x00400000 +DATA 4 0x021B001C 0x02008032 +DATA 4 0x021B001C 0x00008033 +DATA 4 0x021B001C 0x00048031 +DATA 4 0x021B001C 0x15208030 +DATA 4 0x021B001C 0x04008040 +DATA 4 0x021B0020 0x00000800 +DATA 4 0x021B0818 0x00000227 +DATA 4 0x021B0004 0x0002552D +DATA 4 0x021B0404 0x00011006 +DATA 4 0x021B001C 0x00000000 + diff --git a/configs/colibri-imx6ull_defconfig b/configs/colibri-imx6ull_defconfig new file mode 100644 index 0000000..a6db0b8 --- /dev/null +++ b/configs/colibri-imx6ull_defconfig @@ -0,0 +1,76 @@ +CONFIG_ARM=y +CONFIG_SYS_THUMB_BUILD=y +# CONFIG_SPL_SYS_THUMB_BUILD is not set +CONFIG_ARCH_MX6=y +CONFIG_SYS_TEXT_BASE=0x87800000 +CONFIG_TARGET_COLIBRI_IMX6ULL=y +CONFIG_DEFAULT_DEVICE_TREE="imx6ull-colibri" +CONFIG_DISTRO_DEFAULTS=y +CONFIG_FIT=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/colibri-imx6ull/imximage.cfg,MX6ULL,IMX_NAND" +CONFIG_BOOTDELAY=1 +# CONFIG_USE_BOOTCOMMAND is not set +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_VERSION_VARIABLE=y +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SYS_PROMPT="Colibri iMX6ULL # " +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_XIMG is not set +CONFIG_CMD_ASKENV=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_DFU=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +# CONFIG_RANDOM_UUID is not set +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_NAND_TRIMFFS=y +CONFIG_CMD_NAND_TORTURE=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_UBI=y +# CONFIG_ISO_PARTITION is not set +CONFIG_OF_CONTROL=y +CONFIG_ENV_IS_IN_NAND=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_DFU_MMC=y +CONFIG_DFU_NAND=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MXC=y +CONFIG_FSL_ESDHC=y +CONFIG_MTD=y +CONFIG_NAND=y +CONFIG_NAND_MXS=y +CONFIG_NAND_MXS_DT=y +CONFIG_MTD_UBI_FASTMAP=y +CONFIG_PHYLIB=y +CONFIG_PHY_ADDR_ENABLE=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ90X1=y +CONFIG_NETDEVICES=y +CONFIG_FEC_MXC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_REGULATOR=y +# CONFIG_SPL_SERIAL_PRESENT is not set +CONFIG_DM_SERIAL=y +CONFIG_MXC_UART=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Toradex" +CONFIG_USB_GADGET_VENDOR_NUM=0x1b67 +CONFIG_USB_GADGET_PRODUCT_NUM=0x4000 +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_FUNCTION_SDP=y +CONFIG_VIDEO=y +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_FDT_FIXUP_PARTITIONS=y +# CONFIG_EFI_LOADER is not set diff --git a/include/configs/colibri-imx6ull.h b/include/configs/colibri-imx6ull.h new file mode 100644 index 0000000..7661000 --- /dev/null +++ b/include/configs/colibri-imx6ull.h @@ -0,0 +1,199 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 Toradex AG + * + * Configuration settings for the Colibri iMX6ULL module. + * + * based on colibri_imx7.h + */ + +#ifndef __COLIBRI_IMX6ULL_CONFIG_H +#define __COLIBRI_IMX6ULL_CONFIG_H + +#include "mx6_common.h" +#define CONFIG_IOMUX_LPSR + +/* #define CONFIG_DBG_MONITOR*/ +#define PHYS_SDRAM_SIZE SZ_512M + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M) + +/* Network */ +#define CONFIG_MII +#define CONFIG_FEC_XCV_TYPE RMII +#define CONFIG_ETHPRIME "FEC" +#define CONFIG_FEC_MXC_PHYADDR 0 + +#define CONFIG_IP_DEFRAG +#define CONFIG_TFTP_BLOCKSIZE 16352 +#define CONFIG_TFTP_TSIZE + +/* ENET1 */ +#define IMX_FEC_BASE ENET2_BASE_ADDR + +/* MMC Config*/ +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CONFIG_SYS_FSL_USDHC_NUM 1 + +#undef CONFIG_BOOTM_PLAN9 +#undef CONFIG_BOOTM_RTEMS + +/* I2C configs */ +#define CONFIG_SYS_I2C_SPEED 100000 + +#define CONFIG_IPADDR 192.168.10.2 +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_SERVERIP 192.168.10.1 + +#define FDT_FILE "imx6ull-colibri${variant}-${fdt_board}.dtb" + +#define MEM_LAYOUT_ENV_SETTINGS \ + "bootm_size=0x10000000\0" \ + "fdt_addr_r=0x82000000\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "kernel_addr_r=0x81000000\0" \ + "pxefile_addr_r=0x87100000\0" \ + "ramdisk_addr_r=0x82100000\0" \ + "scriptaddr=0x87000000\0" + +#define NFS_BOOTCMD \ + "nfsargs=ip=:::::eth0: root=/dev/nfs\0" \ + "nfsboot=run setup; " \ + "setenv bootargs ${defargs} ${nfsargs} " \ + "${setupargs} ${vidargs}; echo Booting from NFS...;" \ + "dhcp ${kernel_addr_r} && " \ + "tftp ${fdt_addr_r} " FDT_FILE " && " \ + "run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \ + +#define SD_BOOTCMD \ + "sdargs=root=/dev/mmcblk0p2 ro rootwait\0" \ + "sdboot=run setup; setenv bootargs ${defargs} ${sdargs} " \ + "${setupargs} ${vidargs}; echo Booting from MMC/SD card...; " \ + "load mmc 0:1 ${kernel_addr_r} ${kernel_file} && " \ + "load mmc 0:1 ${fdt_addr_r} " FDT_FILE " && " \ + "run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \ + +#define UBI_BOOTCMD \ + "ubiargs=ubi.mtd=ubi root=ubi0:rootfs rw rootfstype=ubifs " \ + "ubi.fm_autoconvert=1\0" \ + "ubiboot=run setup; " \ + "setenv bootargs ${defargs} ${ubiargs} " \ + "${setupargs} ${vidargs}; echo Booting from NAND...; " \ + "ubi part ubi &&" \ + "ubi read ${kernel_addr_r} kernel && " \ + "ubi read ${fdt_addr_r} dtb && " \ + "run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \ + +#define CONFIG_BOOTCOMMAND "run ubiboot; " \ + "setenv fdtfile " FDT_FILE " && run distro_bootcmd;" + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(USB, usb, 0) \ + func(DHCP, dhcp, na) +#include + +#define DFU_ALT_NAND_INFO "imx6ull-bcb part 0,1;u-boot1 part 0,2;u-boot2 part 0,3;u-boot-env part 0,4;ubi partubi 0,5" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + BOOTENV \ + MEM_LAYOUT_ENV_SETTINGS \ + NFS_BOOTCMD \ + SD_BOOTCMD \ + UBI_BOOTCMD \ + "console=ttymxc0\0" \ + "defargs=user_debug=30\0" \ + "dfu_alt_info=" DFU_ALT_NAND_INFO "\0" \ + "fdt_board=eval-v3\0" \ + "fdt_fixup=;\0" \ + "ip_dyn=yes\0" \ + "kernel_file=zImage\0" \ + "mtdparts=" MTDPARTS_DEFAULT "\0" \ + "setethupdate=if env exists ethaddr; then; else setenv ethaddr " \ + "00:14:2d:00:00:00; fi; tftpboot ${loadaddr} " \ + "${board}/flash_eth.img && source ${loadaddr}\0" \ + "setsdupdate=mmc rescan && setenv interface mmc && " \ + "fatload ${interface} 0:1 ${loadaddr} " \ + "${board}/flash_blk.img && source ${loadaddr}\0" \ + "setup=setenv setupargs " \ + "console=tty1 console=${console}" \ + ",${baudrate}n8 ${memargs} consoleblank=0\0" \ + "setupdate=run setsdupdate || run setusbupdate || run setethupdate\0" \ + "setusbupdate=usb start && setenv interface usb && " \ + "fatload ${interface} 0:1 ${loadaddr} " \ + "${board}/flash_blk.img && source ${loadaddr}\0" \ + "splashpos=m,m\0" \ + "videomode=video=ctfb:x:640,y:480,depth:18,pclk:39722,le:48,ri:16,up:33,lo:10,hs:96,vs:2,sync:0,vmode:0\0" \ + "vidargs=video=mxsfb:640x480-16@60" + +#define CONFIG_SYS_MEMTEST_START 0x80000000 +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x08000000) + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +#if defined(CONFIG_ENV_IS_IN_NAND) +#define CONFIG_ENV_SECT_SIZE (128 * 1024) +#define CONFIG_ENV_OFFSET (28 * CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE +#endif + +/* NAND stuff */ +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +/* used to initialize CONFIG_SYS_NAND_BASE_LIST which is unused */ +#define CONFIG_SYS_NAND_BASE -1 +#define CONFIG_SYS_NAND_ONFI_DETECTION +#define CONFIG_SYS_NAND_USE_FLASH_BBT + +/* Dynamic MTD partition support */ +#define CONFIG_MTD_PARTITIONS +#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ +#define MTDIDS_DEFAULT "nand0=gpmi-nand" +#define MTDPARTS_DEFAULT "mtdparts=gpmi-nand:" \ + "512k(mx6ull-bcb)," \ + "1536k(u-boot1)ro," \ + "1536k(u-boot2)ro," \ + "512k(u-boot-env)," \ + "-(ubi)" + +/* USB Configs */ +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET + +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 + +#define CONFIG_IMX_THERMAL + +#define CONFIG_USBD_HS + +/* USB Device Firmware Update support */ +#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_16M +#define DFU_DEFAULT_POLL_TIMEOUT 300 + +#ifdef CONFIG_VIDEO +#define CONFIG_VIDEO_MXS +#define MXS_LCDIF_BASE MX6UL_LCDIF1_BASE_ADDR +#define CONFIG_VIDEO_LOGO +#define CONFIG_SPLASH_SCREEN +#define CONFIG_SPLASH_SCREEN_ALIGN +#define CONFIG_BMP_16BPP +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_VIDEO_BMP_LOGO +#endif + +#endif From 31d9500498b9c9c4eff6a5b1075db7ea4a2db165 Mon Sep 17 00:00:00 2001 From: Baruch Siach Date: Mon, 11 Jun 2018 15:26:18 +0300 Subject: [PATCH 07/51] mmc: drop mention of IN_PROGRESS status The IN_PROGRESS macro has been removed in commit bd47c13583f (mmc: Fix splitting device initialization). Remove it from the mmc_start_init() function description. Signed-off-by: Baruch Siach --- include/mmc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/mmc.h b/include/mmc.h index 534c317..1729292 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -759,7 +759,7 @@ int mmc_set_bkops_enable(struct mmc *mmc); * initializatin. * * @param mmc Pointer to a MMC device struct - * @return 0 on success, IN_PROGRESS on waiting for OCR status, <0 on error. + * @return 0 on success, <0 on error. */ int mmc_start_init(struct mmc *mmc); From 6c09eba507f9f78cfc96db760d064d70d691e9b9 Mon Sep 17 00:00:00 2001 From: Jon Nettleton Date: Mon, 11 Jun 2018 15:26:19 +0300 Subject: [PATCH 08/51] mmc: break out get_op_cond code to its own function This code is useful for testing the existance of devices that do not have card detect capabilities. This breaks out the core functionality and leaves the actual init logic and error reporting in mmc_start_init(). Signed-off-by: Jon Nettleton Signed-off-by: Baruch Siach Reviewed-by: Stefano Babic --- drivers/mmc/mmc.c | 61 +++++++++++++++++++++++++++++++------------------------ include/mmc.h | 10 +++++++++ 2 files changed, 45 insertions(+), 26 deletions(-) diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index f7827f5..ad429f4 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -2491,36 +2491,11 @@ static int mmc_power_cycle(struct mmc *mmc) return mmc_power_on(mmc); } -int mmc_start_init(struct mmc *mmc) +int mmc_get_op_cond(struct mmc *mmc) { - bool no_card; bool uhs_en = supports_uhs(mmc->cfg->host_caps); int err; - /* - * all hosts are capable of 1 bit bus-width and able to use the legacy - * timings. - */ - mmc->host_caps = mmc->cfg->host_caps | MMC_CAP(SD_LEGACY) | - MMC_CAP(MMC_LEGACY) | MMC_MODE_1BIT; - -#if !defined(CONFIG_MMC_BROKEN_CD) - /* we pretend there's no card when init is NULL */ - no_card = mmc_getcd(mmc) == 0; -#else - no_card = 0; -#endif -#if !CONFIG_IS_ENABLED(DM_MMC) - no_card = no_card || (mmc->cfg->ops->init == NULL); -#endif - if (no_card) { - mmc->has_init = 0; -#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) - pr_err("MMC: no card present\n"); -#endif - return -ENOMEDIUM; - } - if (mmc->has_init) return 0; @@ -2597,6 +2572,40 @@ retry: } } + return err; +} + +int mmc_start_init(struct mmc *mmc) +{ + bool no_card; + int err = 0; + + /* + * all hosts are capable of 1 bit bus-width and able to use the legacy + * timings. + */ + mmc->host_caps = mmc->cfg->host_caps | MMC_CAP(SD_LEGACY) | + MMC_CAP(MMC_LEGACY) | MMC_MODE_1BIT; + +#if !defined(CONFIG_MMC_BROKEN_CD) + /* we pretend there's no card when init is NULL */ + no_card = mmc_getcd(mmc) == 0; +#else + no_card = 0; +#endif +#if !CONFIG_IS_ENABLED(DM_MMC) + no_card = no_card || (mmc->cfg->ops->init == NULL); +#endif + if (no_card) { + mmc->has_init = 0; +#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) + pr_err("MMC: no card present\n"); +#endif + return -ENOMEDIUM; + } + + err = mmc_get_op_cond(mmc); + if (!err) mmc->init_in_progress = 1; diff --git a/include/mmc.h b/include/mmc.h index 1729292..df4255b 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -754,6 +754,16 @@ int mmc_set_bkops_enable(struct mmc *mmc); /** * Start device initialization and return immediately; it does not block on + * polling OCR (operation condition register) status. Useful for checking + * the presence of SD/eMMC when no card detect logic is available. + * + * @param mmc Pointer to a MMC device struct + * @return 0 on success, <0 on error. + */ +int mmc_get_op_cond(struct mmc *mmc); + +/** + * Start device initialization and return immediately; it does not block on * polling OCR (operation condition register) status. Then you should call * mmc_init, which would block on polling OCR status and complete the device * initializatin. From 86e5a7fc13d4eb7e21630b9d421469c663dc8c77 Mon Sep 17 00:00:00 2001 From: Jon Nettleton Date: Mon, 11 Jun 2018 15:26:20 +0300 Subject: [PATCH 09/51] mx6cuboxi: Add support for eMMC booting The HB2 boards as well as rev 1.5 soms support eMMC booting as well as SDHC. Add the infrastructure to support booting these devices. Signed-off-by: Jon Nettleton Signed-off-by: Baruch Siach --- board/solidrun/mx6cuboxi/mx6cuboxi.c | 102 ++++++++++++++++++++++++++++++++--- 1 file changed, 94 insertions(+), 8 deletions(-) diff --git a/board/solidrun/mx6cuboxi/mx6cuboxi.c b/board/solidrun/mx6cuboxi/mx6cuboxi.c index 38d89f0..9324650 100644 --- a/board/solidrun/mx6cuboxi/mx6cuboxi.c +++ b/board/solidrun/mx6cuboxi/mx6cuboxi.c @@ -126,6 +126,20 @@ static iomux_v3_cfg_t const usdhc2_pads[] = { IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), }; +static iomux_v3_cfg_t const usdhc3_pads[] = { + IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL)), +}; + static iomux_v3_cfg_t const board_detect[] = { /* These pins are for sensing if it is a CuBox-i or a HummingBoard */ IOMUX_PADS(PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(UART_PAD_CTRL)), @@ -148,23 +162,95 @@ static void setup_iomux_uart(void) SETUP_IOMUX_PADS(uart1_pads); } -static struct fsl_esdhc_cfg usdhc_cfg[1] = { - {USDHC2_BASE_ADDR}, +static struct fsl_esdhc_cfg usdhc_cfg = { + .esdhc_base = USDHC2_BASE_ADDR, + .max_bus_width = 4, }; +static struct fsl_esdhc_cfg emmc_cfg = { + .esdhc_base = USDHC3_BASE_ADDR, + .max_bus_width = 8, +}; + +int board_mmc_get_env_dev(int devno) +{ + return devno - 1; +} + +#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4) + int board_mmc_getcd(struct mmc *mmc) { - return 1; /* uSDHC2 is always present */ + struct fsl_esdhc_cfg *cfg = mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC2_BASE_ADDR: + ret = !gpio_get_value(USDHC2_CD_GPIO); + break; + case USDHC3_BASE_ADDR: + ret = 1; /* eMMC/uSDHC3 has no CD GPIO */ + break; + } + + return ret; } -int board_mmc_init(bd_t *bis) +static int mmc_init_main(bd_t *bis) { + int ret; + + /* + * Following map is done: + * (U-Boot device node) (Physical Port) + * mmc0 Carrier board MicroSD + * mmc1 SOM eMMC + */ SETUP_IOMUX_PADS(usdhc2_pads); - usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR; - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); - gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; + usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + ret = fsl_esdhc_initialize(bis, &usdhc_cfg); + if (ret) + return ret; + + SETUP_IOMUX_PADS(usdhc3_pads); + emmc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + return fsl_esdhc_initialize(bis, &emmc_cfg); +} + +static int mmc_init_spl(bd_t *bis) +{ + struct src *psrc = (struct src *)SRC_BASE_ADDR; + unsigned reg = readl(&psrc->sbmr1) >> 11; + + /* + * Upon reading BOOT_CFG register the following map is done: + * Bit 11 and 12 of BOOT_CFG register can determine the current + * mmc port + * 0x1 SD2 + * 0x2 SD3 + */ + switch (reg & 0x3) { + case 0x1: + SETUP_IOMUX_PADS(usdhc2_pads); + usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + gd->arch.sdhc_clk = usdhc_cfg.sdhc_clk; + return fsl_esdhc_initialize(bis, &usdhc_cfg); + case 0x2: + SETUP_IOMUX_PADS(usdhc3_pads); + emmc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + gd->arch.sdhc_clk = emmc_cfg.sdhc_clk; + return fsl_esdhc_initialize(bis, &emmc_cfg); + } + + return -ENODEV; +} + +int board_mmc_init(bd_t *bis) +{ + if (IS_ENABLED(CONFIG_SPL_BUILD)) + return mmc_init_spl(bis); - return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); + return mmc_init_main(bis); } static iomux_v3_cfg_t const enet_pads[] = { From c4abe2863aae2a31ec7685d44de83122cf321d1e Mon Sep 17 00:00:00 2001 From: Baruch Siach Date: Mon, 11 Jun 2018 15:26:21 +0300 Subject: [PATCH 10/51] mx6cuboxi: drop CONFIG_SYS_FSL_USDHC_NUM This macro is not used. Signed-off-by: Baruch Siach --- include/configs/mx6cuboxi.h | 1 - 1 file changed, 1 deletion(-) diff --git a/include/configs/mx6cuboxi.h b/include/configs/mx6cuboxi.h index 803661c..1f7297d 100644 --- a/include/configs/mx6cuboxi.h +++ b/include/configs/mx6cuboxi.h @@ -67,7 +67,6 @@ #define CONFIG_MXC_UART_BASE UART1_BASE #define CONSOLE_DEV "ttymxc0" -#define CONFIG_SYS_FSL_USDHC_NUM 1 #define CONFIG_SYS_MMC_ENV_DEV 0 /* SDHC2 */ #ifndef CONFIG_SPL_BUILD From 19ed6063a567c6924dbfc358bf4ce9a60a31c567 Mon Sep 17 00:00:00 2001 From: Jon Nettleton Date: Mon, 11 Jun 2018 15:26:22 +0300 Subject: [PATCH 11/51] mx6cuboxi: Use mmc_get_op_cond() to check for an eMMC Previously we had just made broad assumptions with which of our boards had an eMMC or not even though this is a manufacturing time assembly option. This takes the guessing away and actually checks for the existence of an eMMC and sets up the has_emmc environment variable. Signed-off-by: Jon Nettleton Signed-off-by: Baruch Siach --- board/solidrun/mx6cuboxi/mx6cuboxi.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/board/solidrun/mx6cuboxi/mx6cuboxi.c b/board/solidrun/mx6cuboxi/mx6cuboxi.c index 9324650..cf63427 100644 --- a/board/solidrun/mx6cuboxi/mx6cuboxi.c +++ b/board/solidrun/mx6cuboxi/mx6cuboxi.c @@ -189,7 +189,7 @@ int board_mmc_getcd(struct mmc *mmc) ret = !gpio_get_value(USDHC2_CD_GPIO); break; case USDHC3_BASE_ADDR: - ret = 1; /* eMMC/uSDHC3 has no CD GPIO */ + ret = (mmc_get_op_cond(mmc) < 0) ? 0 : 1; /* eMMC/uSDHC3 has no CD GPIO */ break; } @@ -527,6 +527,15 @@ static bool is_rev_15_som(void) return false; } +static bool has_emmc(void) +{ + struct mmc *mmc; + mmc = find_mmc_device(1); + if (!mmc) + return 0; + return (mmc_get_op_cond(mmc) < 0) ? 0 : 1; +} + int checkboard(void) { switch (board_type()) { @@ -579,6 +588,10 @@ int board_late_init(void) if (is_rev_15_som()) env_set("som_rev", "V15"); + + if (has_emmc()) + env_set("has_emmc", "yes"); + #endif return 0; From 824705d53cdbdead205bf4b2267c54d456c6c7bc Mon Sep 17 00:00:00 2001 From: Jon Nettleton Date: Mon, 11 Jun 2018 15:26:23 +0300 Subject: [PATCH 12/51] mx6cuboxi: Add emmc device tree suffix Mainline and now the SolidRun 4.9 nxp based tree use the new reorganization of device-tree files that separate out the emmc into its own dtb. u-boot will now look for -emmc in the device tree name if one is detected. Signed-off-by: Jon Nettleton Signed-off-by: Baruch Siach --- include/configs/mx6cuboxi.h | 24 ++++++++++++++---------- 1 file changed, 14 insertions(+), 10 deletions(-) diff --git a/include/configs/mx6cuboxi.h b/include/configs/mx6cuboxi.h index 1f7297d..a647aab 100644 --- a/include/configs/mx6cuboxi.h +++ b/include/configs/mx6cuboxi.h @@ -71,6 +71,8 @@ #ifndef CONFIG_SPL_BUILD #define CONFIG_EXTRA_ENV_SETTINGS \ + "som_rev=undefined\0" \ + "has_emmc=undefined\0" \ "fdtfile=undefined\0" \ "fdt_addr_r=0x18000000\0" \ "fdt_addr=0x18000000\0" \ @@ -100,19 +102,21 @@ "fi; " \ "fi\0" \ "findfdt="\ - "if test $board_rev = MX6Q ; then " \ + "if test ${board_rev} = MX6Q; then " \ "setenv fdtprefix imx6q; fi; " \ - "if test $board_rev = MX6DL ; then " \ + "if test ${board_rev} = MX6DL; then " \ "setenv fdtprefix imx6dl; fi; " \ - "if test $som_rev = V15 ; then " \ + "if test ${som_rev} = V15; then " \ "setenv fdtsuffix -som-v15; fi; " \ - "if test $board_name = HUMMINGBOARD2 ; then " \ - "setenv fdtfile ${fdtprefix}-hummingboard2${fdtsuffix}.dtb; fi; " \ - "if test $board_name = HUMMINGBOARD ; then " \ - "setenv fdtfile ${fdtprefix}-hummingboard${fdtsuffix}.dtb; fi; " \ - "if test $board_name = CUBOXI ; then " \ - "setenv fdtfile ${fdtprefix}-cubox-i${fdtsuffix}.dtb; fi; " \ - "if test $fdtfile = undefined; then " \ + "if test ${has_emmc} = yes; then " \ + "setenv emmcsuffix -emmc; fi; " \ + "if test ${board_name} = HUMMINGBOARD2 ; then " \ + "setenv fdtfile ${fdtprefix}-hummingboard2${emmcsuffix}${fdtsuffix}.dtb; fi; " \ + "if test ${board_name} = HUMMINGBOARD ; then " \ + "setenv fdtfile ${fdtprefix}-hummingboard${emmcsuffix}${fdtsuffix}.dtb; fi; " \ + "if test ${board_name} = CUBOXI ; then " \ + "setenv fdtfile ${fdtprefix}-cubox-i${emmcsuffix}${fdtsuffix}.dtb; fi; " \ + "if test ${fdtfile} = undefined; then " \ "echo WARNING: Could not determine dtb to use; fi; \0" \ BOOTENV From efd0b791069af93e9d439a70d1fe2ae8994dbbfa Mon Sep 17 00:00:00 2001 From: Michael Trimarchi Date: Sun, 17 Jun 2018 15:22:39 +0200 Subject: [PATCH 13/51] eth: dm: fec: Add gpio phy reset binding Add the missing gpio phy reset binding to the gpio and reset time configuration Signed-off-by: Michael Trimarchi Acked-by: Joe Hershberger --- drivers/net/fec_mxc.c | 43 +++++++++++++++++++++++++++++++++++++------ drivers/net/fec_mxc.h | 5 ++++- 2 files changed, 41 insertions(+), 7 deletions(-) diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index 694a0b2..dac07b6 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -15,7 +15,6 @@ #include #include #include -#include "fec_mxc.h" #include #include @@ -24,6 +23,9 @@ #include #include #include +#include + +#include "fec_mxc.h" DECLARE_GLOBAL_DATA_PTR; @@ -1245,6 +1247,19 @@ static int fec_phy_init(struct fec_priv *priv, struct udevice *dev) return 0; } +#ifdef CONFIG_DM_GPIO +/* FEC GPIO reset */ +static void fec_gpio_reset(struct fec_priv *priv) +{ + debug("fec_gpio_reset: fec_gpio_reset(dev)\n"); + if (dm_gpio_is_valid(&priv->phy_reset_gpio)) { + dm_gpio_set_value(&priv->phy_reset_gpio, 1); + udelay(priv->reset_delay); + dm_gpio_set_value(&priv->phy_reset_gpio, 0); + } +} +#endif + static int fecmxc_probe(struct udevice *dev) { struct eth_pdata *pdata = dev_get_platdata(dev); @@ -1257,6 +1272,9 @@ static int fecmxc_probe(struct udevice *dev) if (ret) return ret; +#ifdef CONFIG_DM_GPIO + fec_gpio_reset(priv); +#endif /* Reset chip. */ writel(readl(&priv->eth->ecntrl) | FEC_ECNTRL_RESET, &priv->eth->ecntrl); @@ -1314,6 +1332,7 @@ static int fecmxc_remove(struct udevice *dev) static int fecmxc_ofdata_to_platdata(struct udevice *dev) { + int ret = 0; struct eth_pdata *pdata = dev_get_platdata(dev); struct fec_priv *priv = dev_get_priv(dev); const char *phy_mode; @@ -1331,12 +1350,24 @@ static int fecmxc_ofdata_to_platdata(struct udevice *dev) return -EINVAL; } - /* TODO - * Need to get the reset-gpio and related properties from DT - * and implemet the enet reset code on .probe call - */ +#ifdef CONFIG_DM_GPIO + ret = gpio_request_by_name(dev, "phy-reset-gpios", 0, + &priv->phy_reset_gpio, GPIOD_IS_OUT); + if (ret == 0) { + ret = dev_read_u32_array(dev, "phy-reset-duration", + &priv->reset_delay, 1); + } else if (ret == -ENOENT) { + priv->reset_delay = 1000; + ret = 0; + } - return 0; + if (priv->reset_delay > 1000) { + printf("FEX MXC: gpio reset timeout should be less the 1000\n"); + priv->reset_delay = 1000; + } +#endif + + return ret; } static const struct udevice_id fecmxc_ids[] = { diff --git a/drivers/net/fec_mxc.h b/drivers/net/fec_mxc.h index 3b935af..fd89443 100644 --- a/drivers/net/fec_mxc.h +++ b/drivers/net/fec_mxc.h @@ -250,7 +250,10 @@ struct fec_priv { int phy_id; int (*mii_postcall)(int); #endif - +#ifdef CONFIG_DM_GPIO + struct gpio_desc phy_reset_gpio; + uint32_t reset_delay; +#endif #ifdef CONFIG_DM_ETH u32 interface; #endif From 9236269de57dc1bd6574855a2d07721f49e80be8 Mon Sep 17 00:00:00 2001 From: Michael Trimarchi Date: Wed, 20 Jun 2018 23:27:54 +0200 Subject: [PATCH 14/51] imx: mx6: Fix implementantion reset_misc lcdif_power_down should not be included in spl build to avoid build failure introduced by commit eb111bb31d882877e75e6b8083808dcaf6493b92 Signed-off-by: Michael Trimarchi Reviewed-by: Peng Fan --- arch/arm/mach-imx/mx6/soc.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/mach-imx/mx6/soc.c b/arch/arm/mach-imx/mx6/soc.c index e8b6f77..ffc2951 100644 --- a/arch/arm/mach-imx/mx6/soc.c +++ b/arch/arm/mach-imx/mx6/soc.c @@ -548,9 +548,11 @@ const struct boot_mode soc_boot_modes[] = { void reset_misc(void) { +#ifndef CONFIG_SPL_BUILD #ifdef CONFIG_VIDEO_MXS lcdif_power_down(); #endif +#endif } void s_init(void) From 2756d31fae31da75f3ac8a10a61e6dd0ebea79c8 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Fri, 22 Jun 2018 13:54:55 -0300 Subject: [PATCH 15/51] mx7: Remove BMODE support i.MX7 does not support BMODE due to the erratum e10574 ("Watchdog: A watchdog timeout or software trigger will not reset the SOC"), so remove its support. Signed-off-by: Fabio Estevam --- arch/arm/mach-imx/Kconfig | 2 +- arch/arm/mach-imx/mx7/Kconfig | 1 - arch/arm/mach-imx/mx7/soc.c | 25 ------------------------- board/toradex/colibri_imx7/colibri_imx7.c | 19 ------------------- 4 files changed, 1 insertion(+), 46 deletions(-) diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 3aec89d..a1566cc 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -46,7 +46,7 @@ config SECURE_BOOT config CMD_BMODE bool "Support the 'bmode' command" default y - depends on ARCH_MX7 || ARCH_MX6 || ARCH_MX5 + depends on ARCH_MX6 || ARCH_MX5 help This enables the 'bmode' (bootmode) command for forcing a boot from specific media. diff --git a/arch/arm/mach-imx/mx7/Kconfig b/arch/arm/mach-imx/mx7/Kconfig index 2a3db86..3d12874 100644 --- a/arch/arm/mach-imx/mx7/Kconfig +++ b/arch/arm/mach-imx/mx7/Kconfig @@ -50,7 +50,6 @@ config TARGET_WARP7 config TARGET_COLIBRI_IMX7 bool "Support Colibri iMX7S/iMX7D modules" - select BOARD_LATE_INIT select DM select DM_SERIAL select DM_THERMAL diff --git a/arch/arm/mach-imx/mx7/soc.c b/arch/arm/mach-imx/mx7/soc.c index 2aca24b..7334ca9 100644 --- a/arch/arm/mach-imx/mx7/soc.c +++ b/arch/arm/mach-imx/mx7/soc.c @@ -8,7 +8,6 @@ #include #include #include -#include #include #include #include @@ -254,30 +253,6 @@ void set_wdog_reset(struct wdog_regs *wdog) writew(reg, &wdog->wcr); } -/* - * cfg_val will be used for - * Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0] - * After reset, if GPR10[28] is 1, ROM will copy GPR9[25:0] - * to SBMR1, which will determine the boot device. - */ -const struct boot_mode soc_boot_modes[] = { - {"ecspi1:0", MAKE_CFGVAL(0x00, 0x60, 0x00, 0x00)}, - {"ecspi1:1", MAKE_CFGVAL(0x40, 0x62, 0x00, 0x00)}, - {"ecspi1:2", MAKE_CFGVAL(0x80, 0x64, 0x00, 0x00)}, - {"ecspi1:3", MAKE_CFGVAL(0xc0, 0x66, 0x00, 0x00)}, - - {"weim", MAKE_CFGVAL(0x00, 0x50, 0x00, 0x00)}, - {"qspi1", MAKE_CFGVAL(0x10, 0x40, 0x00, 0x00)}, - /* 4 bit bus width */ - {"usdhc1", MAKE_CFGVAL(0x10, 0x10, 0x00, 0x00)}, - {"usdhc2", MAKE_CFGVAL(0x10, 0x14, 0x00, 0x00)}, - {"usdhc3", MAKE_CFGVAL(0x10, 0x18, 0x00, 0x00)}, - {"mmc1", MAKE_CFGVAL(0x10, 0x20, 0x00, 0x00)}, - {"mmc2", MAKE_CFGVAL(0x10, 0x24, 0x00, 0x00)}, - {"mmc3", MAKE_CFGVAL(0x10, 0x28, 0x00, 0x00)}, - {NULL, 0}, -}; - void s_init(void) { /* clock configuration. */ diff --git a/board/toradex/colibri_imx7/colibri_imx7.c b/board/toradex/colibri_imx7/colibri_imx7.c index cd98ec8..bf691a5 100644 --- a/board/toradex/colibri_imx7/colibri_imx7.c +++ b/board/toradex/colibri_imx7/colibri_imx7.c @@ -9,7 +9,6 @@ #include #include #include -#include #include #include #include @@ -322,24 +321,6 @@ int board_init(void) return 0; } -#ifdef CONFIG_CMD_BMODE -static const struct boot_mode board_boot_modes[] = { - /* 4 bit bus width */ - {"nand", MAKE_CFGVAL(0x40, 0x34, 0x00, 0x00)}, - {"sd1", MAKE_CFGVAL(0x10, 0x10, 0x00, 0x00)}, - {NULL, 0}, -}; -#endif - -int board_late_init(void) -{ -#ifdef CONFIG_CMD_BMODE - add_board_boot_modes(board_boot_modes); -#endif - - return 0; -} - #ifdef CONFIG_DM_PMIC int power_init_board(void) { From 4a72abcb71d9be773df438f237cc95c2ed399295 Mon Sep 17 00:00:00 2001 From: Michael Trimarchi Date: Sat, 23 Jun 2018 16:10:06 +0200 Subject: [PATCH 16/51] imx: imx6: Add comment to gpr_init function This function can be used only for some of the nxp SoC. Make it explicit in the comment. This adjust a bit commit 3aa4b703b483f165dd ("imx: imx6: Move gpr_init() function to soc.c") Signed-off-by: Michael Trimarchi Acked-by: Jagan Teki --- arch/arm/mach-imx/mx6/soc.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/mach-imx/mx6/soc.c b/arch/arm/mach-imx/mx6/soc.c index ffc2951..31c9a6e 100644 --- a/arch/arm/mach-imx/mx6/soc.c +++ b/arch/arm/mach-imx/mx6/soc.c @@ -651,6 +651,11 @@ void imx_setup_hdmi(void) } #endif + +/* + * gpr_init() function is common for boards using MX6S, MX6DL, MX6D, + * MX6Q and MX6QP processors + */ void gpr_init(void) { struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; From 3058879982ec2ad0a53222dd3a518fb609ca7ae7 Mon Sep 17 00:00:00 2001 From: Michael Trimarchi Date: Sat, 23 Jun 2018 16:10:07 +0200 Subject: [PATCH 17/51] i.MX6: engicam: gpr_init can be called only for some architecture Fix an invalid usage of the gpr_init function for the imx6ul architecture Signed-off-by: Michael Trimarchi Acked-by: Jagan Teki --- board/engicam/common/spl.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/board/engicam/common/spl.c b/board/engicam/common/spl.c index 1a1fe6c..4d293c8 100644 --- a/board/engicam/common/spl.c +++ b/board/engicam/common/spl.c @@ -414,7 +414,8 @@ void board_init_f(ulong dummy) /* setup AIPS and disable watchdog */ arch_cpu_init(); - gpr_init(); + if (!(is_mx6ul())) + gpr_init(); /* iomux */ SETUP_IOMUX_PADS(uart_pads); From 353432419de8f90e19f447b4e054ee28c7fa62d0 Mon Sep 17 00:00:00 2001 From: Uri Mashiach Date: Sun, 24 Jun 2018 12:13:10 +0300 Subject: [PATCH 18/51] arm: imx7d: cl-som-imx7: sf: support all SF types Enable the support for all SPI flash types. Signed-off-by: Uri Mashiach Signed-off-by: Yaniv Levinsky --- configs/cl-som-imx7_defconfig | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/configs/cl-som-imx7_defconfig b/configs/cl-som-imx7_defconfig index 38be7db..d47dd66 100644 --- a/configs/cl-som-imx7_defconfig +++ b/configs/cl-som-imx7_defconfig @@ -46,7 +46,14 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_FSL_ESDHC=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_WINBOND=y CONFIG_SPI=y CONFIG_MXC_SPI=y CONFIG_USB=y From 77fcc2cc901e1886996fda80de464a2372a69124 Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Sun, 24 Jun 2018 21:09:54 +0200 Subject: [PATCH 19/51] ARM: PSCI: initialize stack pointer on secondary CPUs A proper stack is required to safely use C code in psci_arch_cpu_entry. Fixes: 486daaa618e1 ("arm: psci: add a weak function psci_arch_cpu_entry") Cc: Patrick Delaunay Signed-off-by: Stefan Agner Acked-by: Patrick DELAUNAY Tested-by: Patrick DELAUNAY --- arch/arm/cpu/armv7/psci.S | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/cpu/armv7/psci.S b/arch/arm/cpu/armv7/psci.S index 08b5088..983cd90 100644 --- a/arch/arm/cpu/armv7/psci.S +++ b/arch/arm/cpu/armv7/psci.S @@ -331,6 +331,8 @@ ENTRY(psci_cpu_entry) bl _nonsec_init + bl psci_stack_setup + bl psci_arch_cpu_entry bl psci_get_cpu_id @ CPU ID => r0 From cff38c5504485af2aad3cdb5e0d654ae4d8e204d Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Sun, 24 Jun 2018 21:09:55 +0200 Subject: [PATCH 20/51] imx: mx7: psci: use C code exclusively There is no need for assembly in the platform specific part of the PSCI implementation. Note that this does not make it a complete PSCI 1.0 implementation yet but aids to do so in upcoming patches. Signed-off-by: Stefan Agner --- arch/arm/mach-imx/mx7/Makefile | 5 +--- arch/arm/mach-imx/mx7/psci-mx7.c | 29 +++++++++++++++---- arch/arm/mach-imx/mx7/psci.S | 60 ---------------------------------------- 3 files changed, 24 insertions(+), 70 deletions(-) delete mode 100644 arch/arm/mach-imx/mx7/psci.S diff --git a/arch/arm/mach-imx/mx7/Makefile b/arch/arm/mach-imx/mx7/Makefile index 7a1ee7a..94a0e64 100644 --- a/arch/arm/mach-imx/mx7/Makefile +++ b/arch/arm/mach-imx/mx7/Makefile @@ -4,7 +4,4 @@ # obj-y := soc.o clock.o clock_slice.o ddr.o snvs.o - -ifdef CONFIG_ARMV7_PSCI -obj-y += psci-mx7.o psci.o -endif +obj-$(CONFIG_ARMV7_PSCI) += psci-mx7.o diff --git a/arch/arm/mach-imx/mx7/psci-mx7.c b/arch/arm/mach-imx/mx7/psci-mx7.c index 7dc49bd..95f8cb4 100644 --- a/arch/arm/mach-imx/mx7/psci-mx7.c +++ b/arch/arm/mach-imx/mx7/psci-mx7.c @@ -67,23 +67,34 @@ __secure void imx_enable_cpu_ca7(int cpu, bool enable) writel(val, SRC_BASE_ADDR + SRC_A7RCR1); } -__secure int imx_cpu_on(int fn, int cpu, int pc) +__secure s32 psci_cpu_on(u32 __always_unused function_id, u32 mpidr, u32 ep, + u32 context_id) { - writel(pc, SRC_BASE_ADDR + cpu * 8 + SRC_GPR1_MX7D); + u32 cpu = (mpidr & 0x1); + + psci_save(cpu, ep, context_id); + + writel((u32)psci_cpu_entry, SRC_BASE_ADDR + cpu * 8 + SRC_GPR1_MX7D); imx_gpcv2_set_core1_power(true); imx_enable_cpu_ca7(cpu, true); return 0; } -__secure int imx_cpu_off(int cpu) +__secure s32 psci_cpu_off(void) { + int cpu; + + psci_cpu_off_common(); + cpu = psci_get_cpu_id(); imx_enable_cpu_ca7(cpu, false); imx_gpcv2_set_core1_power(false); writel(0, SRC_BASE_ADDR + cpu * 8 + SRC_GPR1_MX7D + 4); - return 0; + + while (1) + wfi(); } -__secure void imx_system_reset(void) +__secure void psci_system_reset(void) { struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; @@ -91,9 +102,12 @@ __secure void imx_system_reset(void) writel(0x1 << 28, CCM_BASE_ADDR + CCM_ROOT_WDOG); writel(0x3, CCM_BASE_ADDR + CCM_CCGR_WDOG1); writew(WCR_WDE, &wdog->wcr); + + while (1) + wfi(); } -__secure void imx_system_off(void) +__secure void psci_system_off(void) { u32 val; @@ -103,4 +117,7 @@ __secure void imx_system_off(void) val = readl(SNVS_BASE_ADDR + SNVS_LPCR); val |= BP_SNVS_LPCR_DP_EN | BP_SNVS_LPCR_TOP; writel(val, SNVS_BASE_ADDR + SNVS_LPCR); + + while (1) + wfi(); } diff --git a/arch/arm/mach-imx/mx7/psci.S b/arch/arm/mach-imx/mx7/psci.S deleted file mode 100644 index 89dcf88..0000000 --- a/arch/arm/mach-imx/mx7/psci.S +++ /dev/null @@ -1,60 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. - * Copyright 2017 NXP - */ - -#include -#include - -#include -#include -#include - - .pushsection ._secure.text, "ax" - - .arch_extension sec - -.globl psci_cpu_on -psci_cpu_on: - push {r4, r5, lr} - - mov r4, r0 - mov r5, r1 - mov r0, r1 - mov r1, r2 - mov r2, r3 - bl psci_save - - mov r0, r4 - mov r1, r5 - ldr r2, =psci_cpu_entry - bl imx_cpu_on - - pop {r4, r5, pc} - -.globl psci_cpu_off -psci_cpu_off: - - bl psci_cpu_off_common - bl psci_get_cpu_id - bl imx_cpu_off - -1: wfi - b 1b - -.globl psci_system_reset -psci_system_reset: - bl imx_system_reset - -2: wfi - b 2b - -.globl psci_system_off -psci_system_off: - bl imx_system_off - -3: wfi - b 3b - - .popsection From a89eb89b385908df511190cef7e360cb4c3f12f6 Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Sun, 24 Jun 2018 21:09:56 +0200 Subject: [PATCH 21/51] imx: mx7: psci: provide complete PSCI 1.0 implementation PSCI 1.0 require PSCI_VERSION, PSCI_FEATURES, AFFINITY_INFO and CPU_SUSPEND to be implemented. Commit 0ec3d98f7692 ("mx7_common: use psci 1.0 instead of 0.1") marked the i.MX 7 implementation to be PSCI 1.0 compliant but failed to implement those functions. Especially the missing PSCI version callback was noticeable when booting Linux: [ 0.000000] psci: probing for conduit method from DT. [ 0.000000] psci: PSCIv65535.65535 detected in firmware. [ 0.000000] psci: Using standard PSCI v0.2 function IDs [ 0.000000] psci: MIGRATE_INFO_TYPE not supported. [ 0.000000] psci: SMC Calling Convention v1.0 This patch provides a minimal implementation thereof. With this patch applied Linux detects PSCI 1.0: [ 0.000000] psci: probing for conduit method from DT. [ 0.000000] psci: PSCIv1.0 detected in firmware. [ 0.000000] psci: Using standard PSCI v0.2 function IDs [ 0.000000] psci: MIGRATE_INFO_TYPE not supported. [ 0.000000] psci: SMC Calling Convention v1.0 Fixes: 0ec3d98f7692 ("mx7_common: use psci 1.0 instead of 0.1") Suggested-by: Mark Rutland Signed-off-by: Stefan Agner --- arch/arm/mach-imx/mx7/psci-mx7.c | 96 ++++++++++++++++++++++++++++++++++++++-- 1 file changed, 93 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-imx/mx7/psci-mx7.c b/arch/arm/mach-imx/mx7/psci-mx7.c index 95f8cb4..8b839d3 100644 --- a/arch/arm/mach-imx/mx7/psci-mx7.c +++ b/arch/arm/mach-imx/mx7/psci-mx7.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include @@ -34,6 +35,24 @@ #define CCM_ROOT_WDOG 0xbb80 #define CCM_CCGR_WDOG1 0x49c0 +#define MPIDR_AFF0 GENMASK(7, 0) + +#define IMX7D_PSCI_NR_CPUS 2 +#if IMX7D_PSCI_NR_CPUS > CONFIG_ARMV7_PSCI_NR_CPUS +#error "invalid value for CONFIG_ARMV7_PSCI_NR_CPUS" +#endif + +u8 psci_state[IMX7D_PSCI_NR_CPUS] __secure_data = { + PSCI_AFFINITY_LEVEL_ON, + PSCI_AFFINITY_LEVEL_OFF}; + +static inline void psci_set_state(int cpu, u8 state) +{ + psci_state[cpu] = state; + dsb(); + isb(); +} + static inline void imx_gpcv2_set_m_core_pgc(bool enable, u32 offset) { writel(enable, GPC_IPS_BASE_ADDR + offset); @@ -67,25 +86,51 @@ __secure void imx_enable_cpu_ca7(int cpu, bool enable) writel(val, SRC_BASE_ADDR + SRC_A7RCR1); } +__secure void psci_arch_cpu_entry(void) +{ + u32 cpu = psci_get_cpu_id(); + + psci_set_state(cpu, PSCI_AFFINITY_LEVEL_ON); +} + __secure s32 psci_cpu_on(u32 __always_unused function_id, u32 mpidr, u32 ep, u32 context_id) { - u32 cpu = (mpidr & 0x1); + u32 cpu = mpidr & MPIDR_AFF0; + + if (mpidr & ~MPIDR_AFF0) + return ARM_PSCI_RET_INVAL; + + if (cpu >= IMX7D_PSCI_NR_CPUS) + return ARM_PSCI_RET_INVAL; + + if (psci_state[cpu] == PSCI_AFFINITY_LEVEL_ON) + return ARM_PSCI_RET_ALREADY_ON; + + if (psci_state[cpu] == PSCI_AFFINITY_LEVEL_ON_PENDING) + return ARM_PSCI_RET_ON_PENDING; psci_save(cpu, ep, context_id); writel((u32)psci_cpu_entry, SRC_BASE_ADDR + cpu * 8 + SRC_GPR1_MX7D); + + psci_set_state(cpu, PSCI_AFFINITY_LEVEL_ON_PENDING); + imx_gpcv2_set_core1_power(true); imx_enable_cpu_ca7(cpu, true); - return 0; + + return ARM_PSCI_RET_SUCCESS; } __secure s32 psci_cpu_off(void) { int cpu; - psci_cpu_off_common(); cpu = psci_get_cpu_id(); + + psci_cpu_off_common(); + psci_set_state(cpu, PSCI_AFFINITY_LEVEL_OFF); + imx_enable_cpu_ca7(cpu, false); imx_gpcv2_set_core1_power(false); writel(0, SRC_BASE_ADDR + cpu * 8 + SRC_GPR1_MX7D + 4); @@ -121,3 +166,48 @@ __secure void psci_system_off(void) while (1) wfi(); } + +__secure u32 psci_version(void) +{ + return ARM_PSCI_VER_1_0; +} + +__secure s32 psci_cpu_suspend(u32 __always_unused function_id, u32 power_state, + u32 entry_point_address, + u32 context_id) +{ + return ARM_PSCI_RET_INVAL; +} + +__secure s32 psci_affinity_info(u32 __always_unused function_id, + u32 target_affinity, + u32 lowest_affinity_level) +{ + u32 cpu = target_affinity & MPIDR_AFF0; + + if (lowest_affinity_level > 0) + return ARM_PSCI_RET_INVAL; + + if (target_affinity & ~MPIDR_AFF0) + return ARM_PSCI_RET_INVAL; + + if (cpu >= IMX7D_PSCI_NR_CPUS) + return ARM_PSCI_RET_INVAL; + + return psci_state[cpu]; +} + +__secure s32 psci_features(u32 __always_unused function_id, u32 psci_fid) +{ + switch (psci_fid) { + case ARM_PSCI_0_2_FN_PSCI_VERSION: + case ARM_PSCI_0_2_FN_CPU_OFF: + case ARM_PSCI_0_2_FN_CPU_ON: + case ARM_PSCI_0_2_FN_AFFINITY_INFO: + case ARM_PSCI_0_2_FN_SYSTEM_OFF: + case ARM_PSCI_0_2_FN_SYSTEM_RESET: + case ARM_PSCI_1_0_FN_PSCI_FEATURES: + return 0x0; + } + return ARM_PSCI_RET_NI; +} From 28a5af11f876a4fa6f1913281985e53b5ed4ba23 Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Sun, 24 Jun 2018 21:09:57 +0200 Subject: [PATCH 22/51] imx: mx7: psci: support CPU0 on/off So far psci_cpu_(on|off) only worked for CPU1. Allow to control CPU0 too. This allows to run the Linux PSCI checker successfully: [ 2.213447] psci_checker: PSCI checker started using 2 CPUs [ 2.219107] psci_checker: Starting hotplug tests [ 2.223859] psci_checker: Trying to turn off and on again all CPUs [ 2.267191] IRQ21 no longer affine to CPU0 [ 2.293266] Retrying again to check for CPU kill [ 2.302269] CPU0 killed. [ 2.311648] psci_checker: Trying to turn off and on again group 0 (CPUs 0-1) [ 2.354354] IRQ21 no longer affine to CPU0 [ 2.383222] Retrying again to check for CPU kill [ 2.392148] CPU0 killed. [ 2.398063] psci_checker: Hotplug tests passed OK [ 2.402910] psci_checker: Starting suspend tests (10 cycles per state) [ 2.410019] psci_checker: cpuidle not available on CPU 0, ignoring [ 2.416452] psci_checker: cpuidle not available on CPU 1, ignoring [ 2.422757] psci_checker: Could not start suspend tests on any CPU [ 2.429370] psci_checker: PSCI checker completed Signed-off-by: Stefan Agner --- arch/arm/mach-imx/mx7/psci-mx7.c | 20 ++++++++++++-------- 1 file changed, 12 insertions(+), 8 deletions(-) diff --git a/arch/arm/mach-imx/mx7/psci-mx7.c b/arch/arm/mach-imx/mx7/psci-mx7.c index 8b839d3..cd72449 100644 --- a/arch/arm/mach-imx/mx7/psci-mx7.c +++ b/arch/arm/mach-imx/mx7/psci-mx7.c @@ -14,8 +14,10 @@ #define GPC_CPU_PGC_SW_PDN_REQ 0xfc #define GPC_CPU_PGC_SW_PUP_REQ 0xf0 +#define GPC_PGC_C0 0x800 #define GPC_PGC_C1 0x840 +#define BM_CPU_PGC_SW_PDN_PUP_REQ_CORE0_A7 0x1 #define BM_CPU_PGC_SW_PDN_PUP_REQ_CORE1_A7 0x2 /* below is for i.MX7D */ @@ -58,22 +60,24 @@ static inline void imx_gpcv2_set_m_core_pgc(bool enable, u32 offset) writel(enable, GPC_IPS_BASE_ADDR + offset); } -__secure void imx_gpcv2_set_core1_power(bool pdn) +__secure void imx_gpcv2_set_core_power(int cpu, bool pdn) { u32 reg = pdn ? GPC_CPU_PGC_SW_PUP_REQ : GPC_CPU_PGC_SW_PDN_REQ; + u32 pgc = cpu ? GPC_PGC_C1 : GPC_PGC_C0; + u32 pdn_pup_req = cpu ? BM_CPU_PGC_SW_PDN_PUP_REQ_CORE1_A7 : + BM_CPU_PGC_SW_PDN_PUP_REQ_CORE0_A7; u32 val; - imx_gpcv2_set_m_core_pgc(true, GPC_PGC_C1); + imx_gpcv2_set_m_core_pgc(true, pgc); val = readl(GPC_IPS_BASE_ADDR + reg); - val |= BM_CPU_PGC_SW_PDN_PUP_REQ_CORE1_A7; + val |= pdn_pup_req; writel(val, GPC_IPS_BASE_ADDR + reg); - while ((readl(GPC_IPS_BASE_ADDR + reg) & - BM_CPU_PGC_SW_PDN_PUP_REQ_CORE1_A7) != 0) + while ((readl(GPC_IPS_BASE_ADDR + reg) & pdn_pup_req) != 0) ; - imx_gpcv2_set_m_core_pgc(false, GPC_PGC_C1); + imx_gpcv2_set_m_core_pgc(false, pgc); } __secure void imx_enable_cpu_ca7(int cpu, bool enable) @@ -116,7 +120,7 @@ __secure s32 psci_cpu_on(u32 __always_unused function_id, u32 mpidr, u32 ep, psci_set_state(cpu, PSCI_AFFINITY_LEVEL_ON_PENDING); - imx_gpcv2_set_core1_power(true); + imx_gpcv2_set_core_power(cpu, true); imx_enable_cpu_ca7(cpu, true); return ARM_PSCI_RET_SUCCESS; @@ -132,7 +136,7 @@ __secure s32 psci_cpu_off(void) psci_set_state(cpu, PSCI_AFFINITY_LEVEL_OFF); imx_enable_cpu_ca7(cpu, false); - imx_gpcv2_set_core1_power(false); + imx_gpcv2_set_core_power(cpu, false); writel(0, SRC_BASE_ADDR + cpu * 8 + SRC_GPR1_MX7D + 4); while (1) From f97df68898eb080ccf712ee5845cf19660b5111b Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Sun, 24 Jun 2018 21:09:58 +0200 Subject: [PATCH 23/51] imx: mx7: psci: implement MIGRATE_INFO_TYPE Implement MIGRATE_INFO_TYPE. This informs Linux that no migration for the trusted operating system is necessary: [ 0.000000] psci: Trusted OS migration not required Signed-off-by: Stefan Agner --- arch/arm/mach-imx/mx7/psci-mx7.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/mach-imx/mx7/psci-mx7.c b/arch/arm/mach-imx/mx7/psci-mx7.c index cd72449..aae96c5 100644 --- a/arch/arm/mach-imx/mx7/psci-mx7.c +++ b/arch/arm/mach-imx/mx7/psci-mx7.c @@ -201,6 +201,12 @@ __secure s32 psci_affinity_info(u32 __always_unused function_id, return psci_state[cpu]; } +__secure s32 psci_migrate_info_type(u32 function_id) +{ + /* Trusted OS is either not present or does not require migration */ + return 2; +} + __secure s32 psci_features(u32 __always_unused function_id, u32 psci_fid) { switch (psci_fid) { @@ -208,6 +214,7 @@ __secure s32 psci_features(u32 __always_unused function_id, u32 psci_fid) case ARM_PSCI_0_2_FN_CPU_OFF: case ARM_PSCI_0_2_FN_CPU_ON: case ARM_PSCI_0_2_FN_AFFINITY_INFO: + case ARM_PSCI_0_2_FN_MIGRATE_INFO_TYPE: case ARM_PSCI_0_2_FN_SYSTEM_OFF: case ARM_PSCI_0_2_FN_SYSTEM_RESET: case ARM_PSCI_1_0_FN_PSCI_FEATURES: From 55314608959e9f5977859362d70978a604d387a8 Mon Sep 17 00:00:00 2001 From: Jon Nettleton Date: Mon, 25 Jun 2018 13:39:03 +0300 Subject: [PATCH 24/51] mx6cuboxi: Move the default environment for all devices Previously we had stored the environment right after the u-boot.img on the disk. I never liked this because with dtbs being included and such the image could grow in size. Instead we move the environment to be negatively offset from the 1MB mark. Almost all our images start at 4MB's, and most standard images start at 1MB, and all our storage devices are a minimum 1MB. Therefore we can store env there for all classes of devices and have plenty of space in case u-boot.img needs to grow. Signed-off-by: Jon Nettleton Signed-off-by: Baruch Siach Reviewed-by: Fabio Estevam --- include/configs/mx6cuboxi.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/mx6cuboxi.h b/include/configs/mx6cuboxi.h index a647aab..7fa63fd 100644 --- a/include/configs/mx6cuboxi.h +++ b/include/configs/mx6cuboxi.h @@ -146,6 +146,6 @@ /* Environment organization */ #define CONFIG_ENV_SIZE (8 * 1024) -#define CONFIG_ENV_OFFSET (8 * 64 * 1024) +#define CONFIG_ENV_OFFSET (SZ_1M - CONFIG_ENV_SIZE) #endif /* __MX6CUBOXI_CONFIG_H */ From e38adcecca4731acaa51b37b00ee5feee55b6b85 Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Tue, 26 Jun 2018 11:10:51 +0200 Subject: [PATCH 25/51] colibri_imx7: add compatible string used in vanilla Linux Device trees from vanilla Linux do not specify a i.MX 7 specific compatible string. Make sure to set partitions also when booting upstream Linux. Signed-off-by: Stefan Agner --- board/toradex/colibri_imx7/colibri_imx7.c | 1 + 1 file changed, 1 insertion(+) diff --git a/board/toradex/colibri_imx7/colibri_imx7.c b/board/toradex/colibri_imx7/colibri_imx7.c index bf691a5..f9f488d 100644 --- a/board/toradex/colibri_imx7/colibri_imx7.c +++ b/board/toradex/colibri_imx7/colibri_imx7.c @@ -391,6 +391,7 @@ int ft_board_setup(void *blob, bd_t *bd) #if defined(CONFIG_FDT_FIXUP_PARTITIONS) static struct node_info nodes[] = { { "fsl,imx7d-gpmi-nand", MTD_DEV_TYPE_NAND, }, /* NAND flash */ + { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, }, }; /* Update partition nodes using info from mtdparts env var */ From a19797b22cbc955ade2ef59c78fbdeea866285a9 Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Tue, 26 Jun 2018 11:10:52 +0200 Subject: [PATCH 26/51] colibri_imx7: improve DDR3 timing This makes sure that all Colibri iMX7 modules work with the same timing. The changes are: - Disable ODT on read (JEDEC standard JESD79-3F says in chapter 5.2.3 ODT during Reads: "As the DDR3 SDRAM can not terminate and drive at the same time, RTT must be disabled at least half a clock cycle..." and also MX7D SABRESD is disabling it) This alone fixed memory issues for two Colibri iMX7 1GB modules which showed issues before - Make sure tRFC(min) is at least 260ns - Make sure tRC is >50.625ns - tRP needs to be >13.125ns, we can lower from 18.75ns to 15ns - tFAW is not relevant, leave at reset Signed-off-by: Stefan Agner Acked-by: Marcel Ziswiler --- board/toradex/colibri_imx7/imximage.cfg | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/board/toradex/colibri_imx7/imximage.cfg b/board/toradex/colibri_imx7/imximage.cfg index 1d66884..25cfd5c 100644 --- a/board/toradex/colibri_imx7/imximage.cfg +++ b/board/toradex/colibri_imx7/imximage.cfg @@ -57,7 +57,7 @@ DATA 4 0x307a01a4 0x00100020 /* DDRC_DFIUPD2 */ DATA 4 0x307a01a8 0x80100004 /* DDRC_RFSHTMG */ -DATA 4 0x307a0064 0x00400045 +DATA 4 0x307a0064 0x00400046 /* DDRC_MP_PCTRL_0 */ DATA 4 0x307a0490 0x00000001 /* DDRC_INIT0 */ @@ -73,15 +73,15 @@ DATA 4 0x307a00e4 0x00100004 /* DDRC_RANKCTL */ DATA 4 0x307a00f4 0x0000033f /* DDRC_DRAMTMG0 */ -DATA 4 0x307a0100 0x090b090a +DATA 4 0x307a0100 0x0910090a /* DDRC_DRAMTMG1 */ -DATA 4 0x307a0104 0x000d020d +DATA 4 0x307a0104 0x000d020e /* DDRC_DRAMTMG2 */ DATA 4 0x307a0108 0x03040307 /* DDRC_DRAMTMG3 */ DATA 4 0x307a010c 0x00002006 /* DDRC_DRAMTMG4 */ -DATA 4 0x307a0110 0x04020205 +DATA 4 0x307a0110 0x04020204 /* DDRC_DRAMTMG5 */ DATA 4 0x307a0114 0x03030202 /* DDRC_DRAMTMG8 */ @@ -105,7 +105,7 @@ DATA 4 0x307a0218 0x07070707 /* DDRC_ODTCFG */ DATA 4 0x307a0240 0x06000601 /* DDRC_ODTMAP */ -DATA 4 0x307a0244 0x00000011 +DATA 4 0x307a0244 0x00000001 /* SRC_DDRC_RCR */ DATA 4 0x30391000 0x00000000 /* DDR_PHY_PHY_CON0 */ From 9ea7519383089fadf411f20b6ea19ab82211cb3a Mon Sep 17 00:00:00 2001 From: Mark Jonas Date: Thu, 28 Jun 2018 15:56:18 +0200 Subject: [PATCH 27/51] arm, imx6: add alternative PAD_CTL_DSE constants Not all i.MX6 pads use the same drive strength table. So far only the 240 Ohm to 34 Ohm table was available. Because the constants used have speaking names it can be confusing to use e.g. PAD_CTL_DSE_48ohm when according to the reference manual 52 Ohm is the correct value. This patch adds the 260 Ohm to 37 Ohm table. For example, the IOMUXC_SW_PAD_CTL_PAD_SD2_CLK register (SD-card clock) uses the added table. Signed-off-by: Mark Jonas Reviewed-by: Stefano Babic --- arch/arm/include/asm/mach-imx/iomux-v3.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/include/asm/mach-imx/iomux-v3.h b/arch/arm/include/asm/mach-imx/iomux-v3.h index bb93058..63f4b33 100644 --- a/arch/arm/include/asm/mach-imx/iomux-v3.h +++ b/arch/arm/include/asm/mach-imx/iomux-v3.h @@ -163,6 +163,14 @@ typedef u64 iomux_v3_cfg_t; #define PAD_CTL_DSE_40ohm (6 << 3) #define PAD_CTL_DSE_34ohm (7 << 3) +#define PAD_CTL_DSE_260ohm (1 << 3) +#define PAD_CTL_DSE_130ohm (2 << 3) +#define PAD_CTL_DSE_88ohm (3 << 3) +#define PAD_CTL_DSE_65ohm (4 << 3) +#define PAD_CTL_DSE_52ohm (5 << 3) +#define PAD_CTL_DSE_43ohm (6 << 3) +#define PAD_CTL_DSE_37ohm (7 << 3) + /* i.MX6SL/SLL */ #define PAD_CTL_LVE (1 << 1) #define PAD_CTL_LVE_BIT (1 << 22) From 7bbce215d82da00b45d4799e6c8945a4788b71c3 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Fri, 29 Jun 2018 15:19:06 -0300 Subject: [PATCH 28/51] pico-imx7d: Convert to distro config Instead of keeping a custom environment, use a more generic approach by switching to disto config. Signed-off-by: Fabio Estevam Signed-off-by: Otavio Salvador --- include/configs/pico-imx7d.h | 55 +++++++++++--------------------------------- 1 file changed, 14 insertions(+), 41 deletions(-) diff --git a/include/configs/pico-imx7d.h b/include/configs/pico-imx7d.h index d2ffa70..243c12f 100644 --- a/include/configs/pico-imx7d.h +++ b/include/configs/pico-imx7d.h @@ -41,48 +41,21 @@ "console=ttymxc4\0" \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ - "fdt_file=imx7d-pico-pi.dtb\0" \ + "fdtfile=imx7d-pico-pi.dtb\0" \ "fdt_addr=0x83000000\0" \ - "ip_dyn=yes\0" \ - "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ - "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ - "finduuid=part uuid mmc 0:2 uuid\0" \ - "mmcargs=setenv bootargs console=${console},${baudrate} " \ - "root=PARTUUID=${uuid} rootwait rw\0" \ - "loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ - "loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run finduuid; " \ - "run mmcargs; " \ - "if run loadfdt; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi;\0" \ - "netargs=setenv bootargs console=${console},${baudrate} " \ - "root=/dev/nfs " \ - "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ - "netboot=echo Booting from net ...; " \ - "run netargs; " \ - "if test ${ip_dyn} = yes; then " \ - "setenv get_cmd dhcp; " \ - "else " \ - "setenv get_cmd tftp; " \ - "fi; " \ - "${get_cmd} ${image}; " \ - "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi;\0" - -#define CONFIG_BOOTCOMMAND \ - "if mmc rescan; then " \ - "if run loadimage; then " \ - "run mmcboot; " \ - "else run netboot; " \ - "fi; " \ - "else run netboot; fi" + "fdt_addr_r=0x83000000\0" \ + "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "ramdisk_addr_r=0x83000000\0" \ + "ramdiskaddr=0x83000000\0" \ + "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \ + BOOTENV + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(DHCP, dhcp, na) + +#include #define CONFIG_SYS_MEMTEST_START 0x80000000 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x20000000) From 7985987dc4990d2ecc75bb11b433735c5ce41911 Mon Sep 17 00:00:00 2001 From: Otavio Salvador Date: Fri, 29 Jun 2018 15:19:07 -0300 Subject: [PATCH 29/51] pico-imx7d: Fix common distro configuration behavior This sets DISTRO_CONFIG and BOOTCOMMAND, as well as add a `finduuid` environment helper to allow it to properly work with Yocto Project and other distributions using extlinux autogenerated configuration files. Signed-off-by: Otavio Salvador --- configs/pico-imx7d_defconfig | 13 +++++-------- include/configs/pico-imx7d.h | 1 + 2 files changed, 6 insertions(+), 8 deletions(-) diff --git a/configs/pico-imx7d_defconfig b/configs/pico-imx7d_defconfig index ef52dcb..7be695c 100644 --- a/configs/pico-imx7d_defconfig +++ b/configs/pico-imx7d_defconfig @@ -3,26 +3,23 @@ CONFIG_ARCH_MX7=y CONFIG_SYS_TEXT_BASE=0x87800000 CONFIG_TARGET_PICO_IMX7D=y CONFIG_IMX_RDC=y +CONFIG_DISTRO_DEFAULTS=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/technexion/pico-imx7d/imximage.cfg" -CONFIG_HUSH_PARSER=y +CONFIG_BOOTCOMMAND="run finduuid; run distro_bootcmd" # CONFIG_CMD_BOOTD is not set -CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMI is not set # CONFIG_CMD_XIMG is not set CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y -CONFIG_CMD_PART=y CONFIG_CMD_USB=y CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y +# CONFIG_CMD_MII is not set CONFIG_CMD_CACHE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y +# CONFIG_ISO_PARTITION is not set +# CONFIG_EFI_PARTITION is not set CONFIG_FSL_ESDHC=y CONFIG_PHYLIB=y CONFIG_USB=y diff --git a/include/configs/pico-imx7d.h b/include/configs/pico-imx7d.h index 243c12f..d27b925 100644 --- a/include/configs/pico-imx7d.h +++ b/include/configs/pico-imx7d.h @@ -49,6 +49,7 @@ "ramdisk_addr_r=0x83000000\0" \ "ramdiskaddr=0x83000000\0" \ "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \ + "finduuid=part uuid mmc 0:1 uuid\0" \ BOOTENV #define BOOT_TARGET_DEVICES(func) \ From 4242de43bb386199c705271dfbb19ccf4b3c281f Mon Sep 17 00:00:00 2001 From: Otavio Salvador Date: Fri, 29 Jun 2018 15:19:08 -0300 Subject: [PATCH 30/51] pico-imx7d: Add GPT partitioning support This allow the use of: > run setup_emmc inside of the U-Boot prompt to do the partitioning of the disk. Signed-off-by: Otavio Salvador --- configs/pico-imx7d_defconfig | 2 +- include/configs/pico-imx7d.h | 4 ++++ 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/configs/pico-imx7d_defconfig b/configs/pico-imx7d_defconfig index 7be695c..e456aed 100644 --- a/configs/pico-imx7d_defconfig +++ b/configs/pico-imx7d_defconfig @@ -10,6 +10,7 @@ CONFIG_BOOTCOMMAND="run finduuid; run distro_bootcmd" # CONFIG_CMD_IMI is not set # CONFIG_CMD_XIMG is not set CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y @@ -19,7 +20,6 @@ CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_CACHE=y CONFIG_CMD_EXT4_WRITE=y # CONFIG_ISO_PARTITION is not set -# CONFIG_EFI_PARTITION is not set CONFIG_FSL_ESDHC=y CONFIG_PHYLIB=y CONFIG_USB=y diff --git a/include/configs/pico-imx7d.h b/include/configs/pico-imx7d.h index d27b925..9746caa 100644 --- a/include/configs/pico-imx7d.h +++ b/include/configs/pico-imx7d.h @@ -50,6 +50,10 @@ "ramdiskaddr=0x83000000\0" \ "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \ "finduuid=part uuid mmc 0:1 uuid\0" \ + "partitions=" \ + "uuid_disk=${uuid_gpt_disk};" \ + "name=rootfs,size=0,uuid=${uuid_gpt_rootfs}\0" \ + "setup_emmc=mmc dev 0; gpt write mmc 0 $partitions; reset;\0" \ BOOTENV #define BOOT_TARGET_DEVICES(func) \ From 0676b6948d31607f208650cd9c1359f6210f55c3 Mon Sep 17 00:00:00 2001 From: Otavio Salvador Date: Fri, 29 Jun 2018 15:19:09 -0300 Subject: [PATCH 31/51] pico-imx7d: Add default DFU targets Signed-off-by: Otavio Salvador --- configs/pico-imx7d_defconfig | 3 ++- include/configs/pico-imx7d.h | 7 +++++++ 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/configs/pico-imx7d_defconfig b/configs/pico-imx7d_defconfig index e456aed..04823ca 100644 --- a/configs/pico-imx7d_defconfig +++ b/configs/pico-imx7d_defconfig @@ -9,6 +9,7 @@ CONFIG_BOOTCOMMAND="run finduuid; run distro_bootcmd" # CONFIG_CMD_BOOTD is not set # CONFIG_CMD_IMI is not set # CONFIG_CMD_XIMG is not set +CONFIG_CMD_DFU=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y @@ -19,7 +20,7 @@ CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_CMD_MII is not set CONFIG_CMD_CACHE=y CONFIG_CMD_EXT4_WRITE=y -# CONFIG_ISO_PARTITION is not set +CONFIG_DFU_MMC=y CONFIG_FSL_ESDHC=y CONFIG_PHYLIB=y CONFIG_USB=y diff --git a/include/configs/pico-imx7d.h b/include/configs/pico-imx7d.h index 9746caa..23ac103 100644 --- a/include/configs/pico-imx7d.h +++ b/include/configs/pico-imx7d.h @@ -32,6 +32,12 @@ /* MMC Config */ #define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CONFIG_DFU_ENV_SETTINGS \ + "dfu_alt_info=u-boot raw 0x2 0x400 mmcpart 1;" \ + "/boot/zImage ext4 0 1;" \ + "/boot/imx7d-pico-pi.dtb ext4 0 1;" \ + "rootfs part 0 1\0" \ + #define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ #define CONFIG_SYS_MMC_IMG_LOAD_PART 1 @@ -49,6 +55,7 @@ "ramdisk_addr_r=0x83000000\0" \ "ramdiskaddr=0x83000000\0" \ "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \ + CONFIG_DFU_ENV_SETTINGS \ "finduuid=part uuid mmc 0:1 uuid\0" \ "partitions=" \ "uuid_disk=${uuid_gpt_disk};" \ From 3fbbfed7a86354a51590647bcaf7c65665e81357 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Fri, 29 Jun 2018 15:19:10 -0300 Subject: [PATCH 32/51] pico-imx7d: Add fastboot support fastboot tool is a convenient way to flash the eMMC, so add support for it. Examples of usages: On the pico-imx7d U-Boot prompt: => fastboot 0 On the Linux PC connected via USB: 1. Retrieving the U-Boot version $ sudo fastboot getvar bootloader-version -i 0x0525 bootloader-version: U-Boot 2018.07-rc1-03888-gde846f9 finished. total time: 0.000s 2. Resetting the board $ sudo fastboot reboot -i 0x0525 (this causes the pico-imx7d to reboot) Signed-off-by: Fabio Estevam Signed-off-by: Otavio Salvador --- configs/pico-imx7d_defconfig | 7 ++++++- include/configs/pico-imx7d.h | 1 + 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/configs/pico-imx7d_defconfig b/configs/pico-imx7d_defconfig index 04823ca..bff6b9c 100644 --- a/configs/pico-imx7d_defconfig +++ b/configs/pico-imx7d_defconfig @@ -21,6 +21,12 @@ CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_CACHE=y CONFIG_CMD_EXT4_WRITE=y CONFIG_DFU_MMC=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x82000000 +CONFIG_FASTBOOT_BUF_SIZE=0x10000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_FSL_ESDHC=y CONFIG_PHYLIB=y CONFIG_USB=y @@ -32,5 +38,4 @@ CONFIG_USB_GADGET_MANUFACTURER="FSL" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_CI_UDC=y -CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_OF_LIBFDT=y diff --git a/include/configs/pico-imx7d.h b/include/configs/pico-imx7d.h index 23ac103..a6ebb04 100644 --- a/include/configs/pico-imx7d.h +++ b/include/configs/pico-imx7d.h @@ -60,6 +60,7 @@ "partitions=" \ "uuid_disk=${uuid_gpt_disk};" \ "name=rootfs,size=0,uuid=${uuid_gpt_rootfs}\0" \ + "fastboot_partition_alias_system=rootfs\0" \ "setup_emmc=mmc dev 0; gpt write mmc 0 $partitions; reset;\0" \ BOOTENV From d5b7177f9130d8b66e7f20f71ff358fb5619a13a Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Fri, 29 Jun 2018 15:19:11 -0300 Subject: [PATCH 33/51] pico-imx7d: Add SPL support Convert pico-imx7d to SPL support. There are two variants of pico-imx7d SOMs: - One with 512MB of RAM - One with 1GB of RAM The 512MB module contains two Hynix H5TC2G63GFR-PBA. The 1GB module contains two Hynix H5TC4G63GFR-PBA. The RAM size is determined in runtime by reading GPIO1_12. While at it, also add USB Serial Download mode support as it is very helpful for loading SPL and u-boot.img via imx_usb_loader. Signed-off-by: Fabio Estevam Signed-off-by: Otavio Salvador --- arch/arm/mach-imx/mx7/Kconfig | 1 + board/technexion/pico-imx7d/Makefile | 2 +- board/technexion/pico-imx7d/imximage.cfg | 97 -------------------------- board/technexion/pico-imx7d/pico-imx7d.c | 2 +- board/technexion/pico-imx7d/spl.c | 116 +++++++++++++++++++++++++++++++ configs/pico-imx7d_defconfig | 14 +++- include/configs/pico-imx7d.h | 2 +- 7 files changed, 133 insertions(+), 101 deletions(-) delete mode 100644 board/technexion/pico-imx7d/imximage.cfg create mode 100644 board/technexion/pico-imx7d/spl.c diff --git a/arch/arm/mach-imx/mx7/Kconfig b/arch/arm/mach-imx/mx7/Kconfig index 3d12874..944585b 100644 --- a/arch/arm/mach-imx/mx7/Kconfig +++ b/arch/arm/mach-imx/mx7/Kconfig @@ -40,6 +40,7 @@ config TARGET_PICO_IMX7D select MX7D select DM select DM_THERMAL + select SUPPORT_SPL config TARGET_WARP7 bool "warp7" diff --git a/board/technexion/pico-imx7d/Makefile b/board/technexion/pico-imx7d/Makefile index 6cfa803..4ae3d60 100644 --- a/board/technexion/pico-imx7d/Makefile +++ b/board/technexion/pico-imx7d/Makefile @@ -1,4 +1,4 @@ # SPDX-License-Identifier: GPL-2.0+ # (C) Copyright 2017 NXP Semiconductors -obj-y := pico-imx7d.o +obj-y := pico-imx7d.o spl.o diff --git a/board/technexion/pico-imx7d/imximage.cfg b/board/technexion/pico-imx7d/imximage.cfg deleted file mode 100644 index c5caff4..0000000 --- a/board/technexion/pico-imx7d/imximage.cfg +++ /dev/null @@ -1,97 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2017 Freescale Semiconductor, Inc. - * - * Refer docs/README.imxmage for more details about how-to configure - * and create imximage boot image - * - * The syntax is taken as close as possible with the kwbimage - */ - -#define __ASSEMBLY__ -#include - -/* image version */ - -IMAGE_VERSION 2 - -BOOT_FROM sd - -/* Secure boot support */ -#ifdef CONFIG_SECURE_BOOT -CSF CONFIG_CSF_SIZE -#endif - -/* - * Device Configuration Data (DCD) - * - * Each entry must have the format: - * Addr-type Address Value - * - * where: - * Addr-type register length (1,2 or 4 bytes) - * Address absolute address of the register - * value value to be stored in the register - */ - -DATA 4 0x30340004 0x4F400005 -/* Clear then set bit30 to ensure exit from DDR retention */ -DATA 4 0x30360388 0x40000000 -DATA 4 0x30360384 0x40000000 - -DATA 4 0x30391000 0x00000002 -DATA 4 0x307a0000 0x01040001 -DATA 4 0x307a01a0 0x80400003 -DATA 4 0x307a01a4 0x00100020 -DATA 4 0x307a01a8 0x80100004 -DATA 4 0x307a0064 0x00400046 -DATA 4 0x307a0490 0x00000001 -DATA 4 0x307a00d0 0x00020083 -DATA 4 0x307a00d4 0x00690000 -DATA 4 0x307a00dc 0x09300004 -DATA 4 0x307a00e0 0x04080000 -DATA 4 0x307a00e4 0x00100004 -DATA 4 0x307a00f4 0x0000033f -DATA 4 0x307a0100 0x09081109 -DATA 4 0x307a0104 0x0007020d -DATA 4 0x307a0108 0x03040407 -DATA 4 0x307a010c 0x00002006 -DATA 4 0x307a0110 0x04020205 -DATA 4 0x307a0114 0x03030202 -DATA 4 0x307a0120 0x00000803 -DATA 4 0x307a0180 0x00800020 -DATA 4 0x307a0184 0x02000100 -DATA 4 0x307a0190 0x02098204 -DATA 4 0x307a0194 0x00030303 -DATA 4 0x307a0200 0x00000016 -DATA 4 0x307a0204 0x00080808 -DATA 4 0x307a0210 0x00000f0f -DATA 4 0x307a0214 0x07070707 -DATA 4 0x307a0218 0x0f070707 -DATA 4 0x307a0240 0x06000604 -DATA 4 0x307a0244 0x00000001 -DATA 4 0x30391000 0x00000000 -DATA 4 0x30790000 0x17420f40 -DATA 4 0x30790004 0x10210100 -DATA 4 0x30790010 0x00060807 -DATA 4 0x307900b0 0x1010007e -DATA 4 0x3079009c 0x00000b24 -DATA 4 0x30790020 0x08080808 -DATA 4 0x30790030 0x08080808 -DATA 4 0x30790050 0x01000010 -DATA 4 0x30790050 0x00000010 - -DATA 4 0x307900c0 0x0e407304 -DATA 4 0x307900c0 0x0e447304 -DATA 4 0x307900c0 0x0e447306 - -CHECK_BITS_SET 4 0x307900c4 0x1 - -DATA 4 0x307900c0 0x0e407304 - -DATA 4 0x30384130 0x00000000 -DATA 4 0x30340020 0x00000178 -DATA 4 0x30384130 0x00000002 -DATA 4 0x30790018 0x0000000f - -CHECK_BITS_SET 4 0x307a0004 0x1 diff --git a/board/technexion/pico-imx7d/pico-imx7d.c b/board/technexion/pico-imx7d/pico-imx7d.c index 44c81ec..0767d04 100644 --- a/board/technexion/pico-imx7d/pico-imx7d.c +++ b/board/technexion/pico-imx7d/pico-imx7d.c @@ -58,7 +58,7 @@ static struct i2c_pads_info i2c_pad_info4 = { int dram_init(void) { - gd->ram_size = PHYS_SDRAM_SIZE; + gd->ram_size = imx_ddr_size(); return 0; } diff --git a/board/technexion/pico-imx7d/spl.c b/board/technexion/pico-imx7d/spl.c new file mode 100644 index 0000000..14d96cb --- /dev/null +++ b/board/technexion/pico-imx7d/spl.c @@ -0,0 +1,116 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Technexion Ltd. + * + * Author: Richard Hu + */ + +#include +#include +#include +#include +#include +#include + +#if defined(CONFIG_SPL_BUILD) +static struct ddrc ddrc_regs_val = { + .mstr = 0x01040001, + .rfshtmg = 0x00400046, + .init1 = 0x00690000, + .init0 = 0x00020083, + .init3 = 0x09300004, + .init4 = 0x04080000, + .init5 = 0x00100004, + .rankctl = 0x0000033F, + .dramtmg0 = 0x09081109, + .dramtmg1 = 0x0007020d, + .dramtmg2 = 0x03040407, + .dramtmg3 = 0x00002006, + .dramtmg4 = 0x04020205, + .dramtmg5 = 0x03030202, + .dramtmg8 = 0x00000803, + .zqctl0 = 0x00800020, + .dfitmg0 = 0x02098204, + .dfitmg1 = 0x00030303, + .dfiupd0 = 0x80400003, + .dfiupd1 = 0x00100020, + .dfiupd2 = 0x80100004, + .addrmap4 = 0x00000F0F, + .odtcfg = 0x06000604, + .odtmap = 0x00000001, + .rfshtmg = 0x00400046, + .dramtmg0 = 0x09081109, + .addrmap0 = 0x0000001f, + .addrmap1 = 0x00080808, + .addrmap4 = 0x00000f0f, + .addrmap5 = 0x07070707, + .addrmap6 = 0x0f0f0707, +}; + +static struct ddrc_mp ddrc_mp_val = { + .pctrl_0 = 0x00000001, +}; + +static struct ddr_phy ddr_phy_regs_val = { + .phy_con0 = 0x17420f40, + .phy_con1 = 0x10210100, + .phy_con4 = 0x00060807, + .mdll_con0 = 0x1010007e, + .drvds_con0 = 0x00000d6e, + .cmd_sdll_con0 = 0x00000010, + .offset_lp_con0 = 0x0000000f, + .offset_rd_con0 = 0x08080808, + .offset_wr_con0 = 0x08080808, +}; + +static struct mx7_calibration calib_param = { + .num_val = 5, + .values = { + 0x0E407304, + 0x0E447304, + 0x0E447306, + 0x0E447304, + 0x0E447304, + }, +}; + +static void gpr_init(void) +{ + struct iomuxc_gpr_base_regs *gpr_regs = + (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; + writel(0x4F400005, &gpr_regs->gpr[1]); +} + +static bool is_1g(void) +{ + gpio_direction_input(IMX_GPIO_NR(1, 12)); + return !gpio_get_value(IMX_GPIO_NR(1, 12)); +} + +static void ddr_init(void) +{ + if (is_1g()) { + ddrc_regs_val.addrmap5 = 0x07070707; + ddrc_regs_val.addrmap6 = 0x0f070707; + } + + mx7_dram_cfg(&ddrc_regs_val, &ddrc_mp_val, &ddr_phy_regs_val, + &calib_param); +} + +void board_init_f(ulong dummy) +{ + arch_cpu_init(); + gpr_init(); + board_early_init_f(); + timer_init(); + preloader_console_init(); + ddr_init(); + memset(__bss_start, 0, __bss_end - __bss_start); + board_init_r(NULL, 0); +} + +void reset_cpu(ulong addr) +{ +} +#endif diff --git a/configs/pico-imx7d_defconfig b/configs/pico-imx7d_defconfig index bff6b9c..27e5ca9 100644 --- a/configs/pico-imx7d_defconfig +++ b/configs/pico-imx7d_defconfig @@ -1,11 +1,22 @@ CONFIG_ARM=y CONFIG_ARCH_MX7=y CONFIG_SYS_TEXT_BASE=0x87800000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_TARGET_PICO_IMX7D=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL=y +CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_IMX_RDC=y CONFIG_DISTRO_DEFAULTS=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/technexion/pico-imx7d/imximage.cfg" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" CONFIG_BOOTCOMMAND="run finduuid; run distro_bootcmd" +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_USB_HOST_SUPPORT=y +CONFIG_SPL_USB_GADGET_SUPPORT=y +CONFIG_SPL_USB_SDP_SUPPORT=y # CONFIG_CMD_BOOTD is not set # CONFIG_CMD_IMI is not set # CONFIG_CMD_XIMG is not set @@ -15,6 +26,7 @@ CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y +CONFIG_CMD_USB_SDP=y CONFIG_CMD_USB_MASS_STORAGE=y # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_MII is not set diff --git a/include/configs/pico-imx7d.h b/include/configs/pico-imx7d.h index a6ebb04..80abcb4 100644 --- a/include/configs/pico-imx7d.h +++ b/include/configs/pico-imx7d.h @@ -10,7 +10,7 @@ #include "mx7_common.h" -#define PHYS_SDRAM_SIZE SZ_1G +#include "imx7_spl.h" /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M) From 1e646426949a4205ae973c4a7ff7f2aea9f6d9bd Mon Sep 17 00:00:00 2001 From: Fabio Berton Date: Fri, 29 Jun 2018 15:19:12 -0300 Subject: [PATCH 34/51] pico-imx7d: Add support for update SPL using DFU Add spl entry on dfu_alt_info to be able to update U-Boot with SPL for pico imx7d board. Signed-off-by: Fabio Berton Signed-off-by: Otavio Salvador --- include/configs/pico-imx7d.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/include/configs/pico-imx7d.h b/include/configs/pico-imx7d.h index 80abcb4..f974b79 100644 --- a/include/configs/pico-imx7d.h +++ b/include/configs/pico-imx7d.h @@ -33,7 +33,9 @@ #define CONFIG_SYS_FSL_ESDHC_ADDR 0 #define CONFIG_DFU_ENV_SETTINGS \ - "dfu_alt_info=u-boot raw 0x2 0x400 mmcpart 1;" \ + "dfu_alt_info=" \ + "spl raw 0x2 0x400 mmcpart 1;" \ + "u-boot raw 0x8a 0x400 mmcpart 1;" \ "/boot/zImage ext4 0 1;" \ "/boot/imx7d-pico-pi.dtb ext4 0 1;" \ "rootfs part 0 1\0" \ From 22dda6bd8b2b495a71d3776cf0b4379fe14fd8bc Mon Sep 17 00:00:00 2001 From: Otavio Salvador Date: Fri, 29 Jun 2018 15:19:13 -0300 Subject: [PATCH 35/51] pico-imx7d: Add bootmenu to choose the baseboard Currently the baseboards do not offer a way to autodetect which one is in use, so we ask the user if no value has been set. Signed-off-by: Otavio Salvador --- configs/pico-imx7d_defconfig | 3 ++- include/configs/pico-imx7d.h | 12 +++++++++++- 2 files changed, 13 insertions(+), 2 deletions(-) diff --git a/configs/pico-imx7d_defconfig b/configs/pico-imx7d_defconfig index 27e5ca9..3eb26c7 100644 --- a/configs/pico-imx7d_defconfig +++ b/configs/pico-imx7d_defconfig @@ -12,12 +12,13 @@ CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_IMX_RDC=y CONFIG_DISTRO_DEFAULTS=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" -CONFIG_BOOTCOMMAND="run finduuid; run distro_bootcmd" +CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd" CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_USB_HOST_SUPPORT=y CONFIG_SPL_USB_GADGET_SUPPORT=y CONFIG_SPL_USB_SDP_SUPPORT=y # CONFIG_CMD_BOOTD is not set +CONFIG_CMD_BOOTMENU=y # CONFIG_CMD_IMI is not set # CONFIG_CMD_XIMG is not set CONFIG_CMD_DFU=y diff --git a/include/configs/pico-imx7d.h b/include/configs/pico-imx7d.h index f974b79..94c846a 100644 --- a/include/configs/pico-imx7d.h +++ b/include/configs/pico-imx7d.h @@ -40,6 +40,10 @@ "/boot/imx7d-pico-pi.dtb ext4 0 1;" \ "rootfs part 0 1\0" \ +#define BOOTMENU_ENV \ + "bootmenu_0=Boot using PICO-PI baseboard=" \ + "setenv fdtfile imx7d-pico-pi.dtb\0" \ + #define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ #define CONFIG_SYS_MMC_IMG_LOAD_PART 1 @@ -49,7 +53,8 @@ "console=ttymxc4\0" \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ - "fdtfile=imx7d-pico-pi.dtb\0" \ + "fdtfile=ask\0" \ + BOOTMENU_ENV \ "fdt_addr=0x83000000\0" \ "fdt_addr_r=0x83000000\0" \ "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ @@ -58,6 +63,11 @@ "ramdiskaddr=0x83000000\0" \ "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \ CONFIG_DFU_ENV_SETTINGS \ + "findfdt=" \ + "if test $fdtfile = ask ; then " \ + "bootmenu -1; fi;" \ + "if test $fdtfile != ask ; then " \ + "saveenv; fi;\0" \ "finduuid=part uuid mmc 0:1 uuid\0" \ "partitions=" \ "uuid_disk=${uuid_gpt_disk};" \ From 78d30a1bc039bc4c0a63cca4c03238adb5cf02bb Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Fri, 29 Jun 2018 15:19:14 -0300 Subject: [PATCH 36/51] pico-imx7d: Add Falcon mode support Falcon mode boots the kernel directly from SPL, without loading the full U-Boot. As pico-imx7d does not have a GPIO for selecting Falcon versus normal mode, enter in Falcon mode when the customer selects the CONFIG_SPL_OS_BOOT option in menuconfig. Signed-off-by: Fabio Estevam Signed-off-by: Otavio Salvador --- board/technexion/pico-imx7d/spl.c | 8 ++++++++ configs/pico-imx7d_defconfig | 2 ++ include/configs/pico-imx7d.h | 12 ++++++++++++ 3 files changed, 22 insertions(+) diff --git a/board/technexion/pico-imx7d/spl.c b/board/technexion/pico-imx7d/spl.c index 14d96cb..a5463ee 100644 --- a/board/technexion/pico-imx7d/spl.c +++ b/board/technexion/pico-imx7d/spl.c @@ -13,6 +13,14 @@ #include #if defined(CONFIG_SPL_BUILD) + +#ifdef CONFIG_SPL_OS_BOOT +int spl_start_uboot(void) +{ + return 0; +} +#endif + static struct ddrc ddrc_regs_val = { .mstr = 0x01040001, .rfshtmg = 0x00400046, diff --git a/configs/pico-imx7d_defconfig b/configs/pico-imx7d_defconfig index 3eb26c7..6ea49fd 100644 --- a/configs/pico-imx7d_defconfig +++ b/configs/pico-imx7d_defconfig @@ -21,6 +21,8 @@ CONFIG_SPL_USB_SDP_SUPPORT=y CONFIG_CMD_BOOTMENU=y # CONFIG_CMD_IMI is not set # CONFIG_CMD_XIMG is not set +CONFIG_CMD_SPL=y +CONFIG_CMD_SPL_WRITE_SIZE=0x20000 CONFIG_CMD_DFU=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y diff --git a/include/configs/pico-imx7d.h b/include/configs/pico-imx7d.h index 94c846a..8f1876c 100644 --- a/include/configs/pico-imx7d.h +++ b/include/configs/pico-imx7d.h @@ -12,6 +12,18 @@ #include "imx7_spl.h" +#ifdef CONFIG_SPL_OS_BOOT +/* Falcon Mode */ +#define CONFIG_SPL_FS_LOAD_ARGS_NAME "args" +#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage" +#define CONFIG_SYS_SPL_ARGS_ADDR 0x88000000 + +/* Falcon Mode - MMC support: args@1MB kernel@2MB */ +#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x800 /* 1MB */ +#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (CONFIG_CMD_SPL_WRITE_SIZE / 512) +#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x1000 /* 2MB */ +#endif + /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M) From c6f69fe712c88795319a05ecd282cc545f9aff3d Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Fri, 29 Jun 2018 15:19:15 -0300 Subject: [PATCH 37/51] pico-imx7d: Enable CONFIG_ARMV7_BOOT_SEC_DEFAULT Currently the CAAM driver fails to be probed: caam 30900000.caam: Entropy delay = 3200 caam 30900000.caam: failed to acquire DECO 0 caam 30900000.caam: failed to instantiate RNG CAAM needs to be initialized in secure world, so enable CONFIG_ARMV7_BOOT_SEC_DEFAULT to allow the driver to probe successfully. Tested with kernel mainline version 4.17.2. Signed-off-by: Fabio Estevam Signed-off-by: Otavio Salvador --- configs/pico-imx7d_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/pico-imx7d_defconfig b/configs/pico-imx7d_defconfig index 6ea49fd..17fe13b 100644 --- a/configs/pico-imx7d_defconfig +++ b/configs/pico-imx7d_defconfig @@ -9,6 +9,7 @@ CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL=y CONFIG_SPL_LIBDISK_SUPPORT=y +CONFIG_ARMV7_BOOT_SEC_DEFAULT=y CONFIG_IMX_RDC=y CONFIG_DISTRO_DEFAULTS=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" From e5ccad5d004129a453aeadabecc5158d67261039 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Fri, 29 Jun 2018 15:19:16 -0300 Subject: [PATCH 38/51] pico-imx7d: Do not override addrmap5 The addrmap5 value is the same for the 512MB and 1GB variants, so there is no need to override it. Signed-off-by: Fabio Estevam Signed-off-by: Otavio Salvador --- board/technexion/pico-imx7d/spl.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/board/technexion/pico-imx7d/spl.c b/board/technexion/pico-imx7d/spl.c index a5463ee..8c34438 100644 --- a/board/technexion/pico-imx7d/spl.c +++ b/board/technexion/pico-imx7d/spl.c @@ -97,10 +97,8 @@ static bool is_1g(void) static void ddr_init(void) { - if (is_1g()) { - ddrc_regs_val.addrmap5 = 0x07070707; + if (is_1g()) ddrc_regs_val.addrmap6 = 0x0f070707; - } mx7_dram_cfg(&ddrc_regs_val, &ddrc_mp_val, &ddr_phy_regs_val, &calib_param); From 4f96670104f67229e7d335065bee4c48034a26d9 Mon Sep 17 00:00:00 2001 From: Otavio Salvador Date: Fri, 29 Jun 2018 15:19:17 -0300 Subject: [PATCH 39/51] pico-imx7d: Allow default fdtfile to be overridden by defconfig This allow the addition of extra default configurations for each baseboard, removing the boot menu when user boots for the first time. Signed-off-by: Otavio Salvador --- configs/pico-imx7d_defconfig | 1 + include/configs/pico-imx7d.h | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/configs/pico-imx7d_defconfig b/configs/pico-imx7d_defconfig index 17fe13b..af2a776 100644 --- a/configs/pico-imx7d_defconfig +++ b/configs/pico-imx7d_defconfig @@ -14,6 +14,7 @@ CONFIG_IMX_RDC=y CONFIG_DISTRO_DEFAULTS=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd" +CONFIG_DEFAULT_FDT_FILE="ask" CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_USB_HOST_SUPPORT=y CONFIG_SPL_USB_GADGET_SUPPORT=y diff --git a/include/configs/pico-imx7d.h b/include/configs/pico-imx7d.h index 8f1876c..13e7353 100644 --- a/include/configs/pico-imx7d.h +++ b/include/configs/pico-imx7d.h @@ -65,7 +65,7 @@ "console=ttymxc4\0" \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ - "fdtfile=ask\0" \ + "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ BOOTMENU_ENV \ "fdt_addr=0x83000000\0" \ "fdt_addr_r=0x83000000\0" \ From 190702af514df2cd121417bcf3c316d1c7eb93b8 Mon Sep 17 00:00:00 2001 From: Otavio Salvador Date: Fri, 29 Jun 2018 15:19:18 -0300 Subject: [PATCH 40/51] pico-imx7d: Enable auxiliary code support This enables the "bootaux" command so a firmware can be loaded inside the M4 MCU. Signed-off-by: Otavio Salvador --- configs/pico-imx7d_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/pico-imx7d_defconfig b/configs/pico-imx7d_defconfig index af2a776..57312b1 100644 --- a/configs/pico-imx7d_defconfig +++ b/configs/pico-imx7d_defconfig @@ -11,6 +11,7 @@ CONFIG_SPL=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_ARMV7_BOOT_SEC_DEFAULT=y CONFIG_IMX_RDC=y +CONFIG_IMX_BOOTAUX=y CONFIG_DISTRO_DEFAULTS=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd" From 619fc167b65ea07601e0ce1cd969718c7092a40c Mon Sep 17 00:00:00 2001 From: Otavio Salvador Date: Fri, 29 Jun 2018 15:19:19 -0300 Subject: [PATCH 41/51] pico-imx7d: README: Use dfu-util to flash U-Boot The DFU allows a more user friendly use as the details where the bootloader is installed are abstracted. Signed-off-by: Otavio Salvador --- board/technexion/pico-imx7d/README | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/board/technexion/pico-imx7d/README b/board/technexion/pico-imx7d/README index 8af4eff..9e88bc2 100644 --- a/board/technexion/pico-imx7d/README +++ b/board/technexion/pico-imx7d/README @@ -35,12 +35,17 @@ Use the default environment variables: => env default -f -a => saveenv -Run the UMS command: -=> ums 0 mmc 0 +Run the DFU agent so we can flash the new images using dfu-util tool: -Transfer u-boot.imx to be flashed into the eMMC: +=> dfu 0 mmc 0 -$ sudo dd if=u-boot.imx of=/dev/sdX bs=1K seek=1; sync +Flash SPL into the eMMC: + +$ sudo dfu-util -D SPL -a spl + +Flash u-boot.img into the eMMC: + +$ sudo dfu-util -D u-boot.img -a u-boot Remove power from the pico board. From 0a7b54f58779ddbc3383e75789e6e45bb1b93b7f Mon Sep 17 00:00:00 2001 From: Otavio Salvador Date: Fri, 29 Jun 2018 15:19:20 -0300 Subject: [PATCH 42/51] pico-imx7d: README: Drop old instructions about secure mode Our default config already has the secure mode supported, so the manual step is not required anymore. Signed-off-by: Otavio Salvador --- board/technexion/pico-imx7d/README | 17 ----------------- 1 file changed, 17 deletions(-) diff --git a/board/technexion/pico-imx7d/README b/board/technexion/pico-imx7d/README index 9e88bc2..aa9d72c 100644 --- a/board/technexion/pico-imx7d/README +++ b/board/technexion/pico-imx7d/README @@ -52,20 +52,3 @@ Remove power from the pico board. Put pico board into normal boot mode. Power up the board and the new updated U-Boot should boot from eMMC. - -Building U-Boot to boot with NXP 4.1 kernel: - -The NXP 4.1 kernel boots only in secure boot mode on mx7. - -Follow the next steps to enable secure boot: - -$ make mrproper -$ make pico-imx7d_defconfig -$ make menuconfig - -> ARM architecture - -> [*] Enable support for booting in non-secure mode - -> [*] Boot in secure mode by default - -> Exit -$ make - -Flash u-boot.imx using the imx_usb_loader tool. From 3a68ad49352ba1d33820e5ece4decd3ddb7c0287 Mon Sep 17 00:00:00 2001 From: Otavio Salvador Date: Fri, 29 Jun 2018 15:19:21 -0300 Subject: [PATCH 43/51] pico-imx7d: Add new pico-pi config The new config skips the boot menu which asks which board is in use. This is useful to allow direct booting of image without user iteration. Signed-off-by: Otavio Salvador --- configs/pico-pi-imx7d_defconfig | 59 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 59 insertions(+) create mode 100644 configs/pico-pi-imx7d_defconfig diff --git a/configs/pico-pi-imx7d_defconfig b/configs/pico-pi-imx7d_defconfig new file mode 100644 index 0000000..2e72572 --- /dev/null +++ b/configs/pico-pi-imx7d_defconfig @@ -0,0 +1,59 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX7=y +CONFIG_SYS_TEXT_BASE=0x87800000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_TARGET_PICO_IMX7D=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL=y +CONFIG_SPL_LIBDISK_SUPPORT=y +CONFIG_ARMV7_BOOT_SEC_DEFAULT=y +CONFIG_IMX_RDC=y +CONFIG_IMX_BOOTAUX=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" +CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd" +CONFIG_DEFAULT_FDT_FILE="imx7d-pico-pi.dtb" +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_USB_HOST_SUPPORT=y +CONFIG_SPL_USB_GADGET_SUPPORT=y +CONFIG_SPL_USB_SDP_SUPPORT=y +# CONFIG_CMD_BOOTD is not set +CONFIG_CMD_BOOTMENU=y +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_XIMG is not set +CONFIG_CMD_SPL=y +CONFIG_CMD_SPL_WRITE_SIZE=0x20000 +CONFIG_CMD_DFU=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_SDP=y +CONFIG_CMD_USB_MASS_STORAGE=y +# CONFIG_CMD_SETEXPR is not set +# CONFIG_CMD_MII is not set +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_DFU_MMC=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x82000000 +CONFIG_FASTBOOT_BUF_SIZE=0x10000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_FASTBOOT_CMD_OEM_FORMAT=y +CONFIG_FSL_ESDHC=y +CONFIG_PHYLIB=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_MXC_USB_OTG_HACTIVE=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y +CONFIG_OF_LIBFDT=y From 3d81584d40877f95a381355438e5694253f5fa9b Mon Sep 17 00:00:00 2001 From: Ludwig Zenz Date: Thu, 5 Jul 2018 09:23:46 +0200 Subject: [PATCH 44/51] Revert "ARM: imx6: Disable DDR DRAM calibration DHCOM i.MX6 PDK" This reverts commit a637fe6f27fd4c19ef9f43a5f871c244581422ac. The DDR DRAM calibration was enhanced by write leveling correction code. It can be used with T-topology now. Signed-off-by: Ludwig Zenz --- board/dhelectronics/dh_imx6/dh_imx6_spl.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/board/dhelectronics/dh_imx6/dh_imx6_spl.c b/board/dhelectronics/dh_imx6/dh_imx6_spl.c index dffe4eb..beda389 100644 --- a/board/dhelectronics/dh_imx6/dh_imx6_spl.c +++ b/board/dhelectronics/dh_imx6/dh_imx6_spl.c @@ -384,6 +384,10 @@ void board_init_f(ulong dummy) &dhcom6sdl_grp_ioregs); mx6_dram_cfg(&dhcom_ddr_info, &dhcom_mmdc_calib, &dhcom_mem_ddr); + /* Perform DDR DRAM calibration */ + udelay(100); + mmdc_do_dqs_calibration(&dhcom_ddr_info); + /* Clear the BSS. */ memset(__bss_start, 0, __bss_end - __bss_start); From 659ca2dd08cc669a259c8205c8b4ac63b06911e6 Mon Sep 17 00:00:00 2001 From: Ludwig Zenz Date: Thu, 5 Jul 2018 09:23:47 +0200 Subject: [PATCH 45/51] ARM: imx6: configure ddrcode pins in spl DHCOM i.MX6 PDK Preperation for conditional DDR3 initialization based on GPIO codes. Signed-off-by: Ludwig Zenz --- board/dhelectronics/dh_imx6/dh_imx6_spl.c | 40 +++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/board/dhelectronics/dh_imx6/dh_imx6_spl.c b/board/dhelectronics/dh_imx6/dh_imx6_spl.c index beda389..eafb86d 100644 --- a/board/dhelectronics/dh_imx6/dh_imx6_spl.c +++ b/board/dhelectronics/dh_imx6/dh_imx6_spl.c @@ -208,6 +208,45 @@ static void setup_iomux_boardid(void) SETUP_IOMUX_PADS(hwcode_pads); } +/* DDR Code */ +static iomux_v3_cfg_t const ddrcode_pads[] = { + IOMUX_PADS(PAD_EIM_A16__GPIO2_IO22 | MUX_PAD_CTRL(GPIO_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_A17__GPIO2_IO21 | MUX_PAD_CTRL(GPIO_PAD_CTRL)), +}; + +static void setup_iomux_ddrcode(void) +{ + /* ddr code pins */ + SETUP_IOMUX_PADS(ddrcode_pads); +} + +enum dhcom_ddr3_code { + DH_DDR3_SIZE_256MIB = 0x00, + DH_DDR3_SIZE_512MIB = 0x01, + DH_DDR3_SIZE_1GIB = 0x02, + DH_DDR3_SIZE_2GIB = 0x03 +}; + +#define DDR3_CODE_BIT_0 IMX_GPIO_NR(2, 22) +#define DDR3_CODE_BIT_1 IMX_GPIO_NR(2, 21) + +enum dhcom_ddr3_code dhcom_get_ddr3_code(void) +{ + enum dhcom_ddr3_code ddr3_code; + + gpio_request(DDR3_CODE_BIT_0, "DDR3_CODE_BIT_0"); + gpio_request(DDR3_CODE_BIT_1, "DDR3_CODE_BIT_1"); + + gpio_direction_input(DDR3_CODE_BIT_0); + gpio_direction_input(DDR3_CODE_BIT_1); + + /* 256MB = 0b00; 512MB = 0b01; 1GB = 0b10; 2GB = 0b11 */ + ddr3_code = (!!gpio_get_value(DDR3_CODE_BIT_1) << 1) + | (!!gpio_get_value(DDR3_CODE_BIT_0)); + + return ddr3_code; +} + /* GPIO */ static iomux_v3_cfg_t const gpio_pads[] = { IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(GPIO_PAD_CTRL)), @@ -365,6 +404,7 @@ void board_init_f(ulong dummy) timer_init(); setup_iomux_boardid(); + setup_iomux_ddrcode(); setup_iomux_gpio(); setup_iomux_enet(); setup_iomux_sd(); From 0481bef035f5281d075549eb18cc6949dfbc42ff Mon Sep 17 00:00:00 2001 From: Ludwig Zenz Date: Thu, 5 Jul 2018 09:23:48 +0200 Subject: [PATCH 46/51] ARM: imx6: DHCOM i.MX6 PDK: ddr init for 32bit bus and 4GBit chips Support 1GIB + 2GIB DDR3 with 64bit bus width and 512MIB + 1GIB with 32bit bus width Signed-off-by: Ludwig Zenz --- board/dhelectronics/dh_imx6/dh_imx6_spl.c | 191 +++++++++++++++++++++++++++--- 1 file changed, 173 insertions(+), 18 deletions(-) diff --git a/board/dhelectronics/dh_imx6/dh_imx6_spl.c b/board/dhelectronics/dh_imx6/dh_imx6_spl.c index eafb86d..04e9eab 100644 --- a/board/dhelectronics/dh_imx6/dh_imx6_spl.c +++ b/board/dhelectronics/dh_imx6/dh_imx6_spl.c @@ -136,7 +136,31 @@ static const struct mx6sdl_iomux_grp_regs dhcom6sdl_grp_ioregs = { .grp_b7ds = 0x00000030, }; -static const struct mx6_mmdc_calibration dhcom_mmdc_calib = { +static const struct mx6_mmdc_calibration dhcom_mmdc_calib_4x4g_1066 = { + .p0_mpwldectrl0 = 0x00150019, + .p0_mpwldectrl1 = 0x001C000B, + .p1_mpwldectrl0 = 0x00020018, + .p1_mpwldectrl1 = 0x0002000C, + .p0_mpdgctrl0 = 0x43140320, + .p0_mpdgctrl1 = 0x03080304, + .p1_mpdgctrl0 = 0x43180320, + .p1_mpdgctrl1 = 0x03100254, + .p0_mprddlctl = 0x4830383C, + .p1_mprddlctl = 0x3836323E, + .p0_mpwrdlctl = 0x3E444642, + .p1_mpwrdlctl = 0x42344442, +}; + +static const struct mx6_mmdc_calibration dhcom_mmdc_calib_2x4g_800 = { + .p0_mpwldectrl0 = 0x0040003C, + .p0_mpwldectrl1 = 0x0032003E, + .p0_mpdgctrl0 = 0x42350231, + .p0_mpdgctrl1 = 0x021A0218, + .p0_mprddlctl = 0x4B4B4E49, + .p0_mpwrdlctl = 0x3F3F3035, +}; + +static const struct mx6_mmdc_calibration dhcom_mmdc_calib_4x2g_1066 = { .p0_mpwldectrl0 = 0x0011000E, .p0_mpwldectrl1 = 0x000E001B, .p1_mpwldectrl0 = 0x00190015, @@ -151,23 +175,89 @@ static const struct mx6_mmdc_calibration dhcom_mmdc_calib = { .p1_mpwrdlctl = 0x473E4A3B, }; -static const struct mx6_ddr3_cfg dhcom_mem_ddr = { +static const struct mx6_mmdc_calibration dhcom_mmdc_calib_4x2g_800 = { + .p0_mpwldectrl0 = 0x003A003A, + .p0_mpwldectrl1 = 0x0030002F, + .p1_mpwldectrl0 = 0x002F0038, + .p1_mpwldectrl1 = 0x00270039, + .p0_mpdgctrl0 = 0x420F020F, + .p0_mpdgctrl1 = 0x01760175, + .p1_mpdgctrl0 = 0x41640171, + .p1_mpdgctrl1 = 0x015E0160, + .p0_mprddlctl = 0x45464B4A, + .p1_mprddlctl = 0x49484A46, + .p0_mpwrdlctl = 0x40402E32, + .p1_mpwrdlctl = 0x3A3A3231, +}; + +static const struct mx6_mmdc_calibration dhcom_mmdc_calib_2x2g_800 = { + .p0_mpwldectrl0 = 0x0040003C, + .p0_mpwldectrl1 = 0x0032003E, + .p0_mpdgctrl0 = 0x42350231, + .p0_mpdgctrl1 = 0x021A0218, + .p0_mprddlctl = 0x4B4B4E49, + .p0_mpwrdlctl = 0x3F3F3035, +}; + +/* + * 2 Gbit DDR3 memory + * - NANYA #NT5CC128M16IP-DII + * - NANYA #NT5CB128M16FP-DII + */ +static const struct mx6_ddr3_cfg dhcom_mem_ddr_2g = { .mem_speed = 1600, .density = 2, - .width = 64, + .width = 16, .banks = 8, .rowaddr = 14, .coladdr = 10, .pagesz = 2, - .trcd = 1312, + .trcd = 1375, .trcmin = 5863, .trasmin = 3750, }; -static const struct mx6_ddr_sysinfo dhcom_ddr_info = { +/* + * 4 Gbit DDR3 memory + * - Intelligent Memory #IM4G16D3EABG-125I + */ +static const struct mx6_ddr3_cfg dhcom_mem_ddr_4g = { + .mem_speed = 1600, + .density = 4, + .width = 16, + .banks = 8, + .rowaddr = 15, + .coladdr = 10, + .pagesz = 2, + .trcd = 1375, + .trcmin = 4875, + .trasmin = 3500, +}; + +/* DDR3 64bit */ +static const struct mx6_ddr_sysinfo dhcom_ddr_64bit = { /* width of data bus:0=16,1=32,2=64 */ .dsize = 2, - .cs_density = 16, + .cs_density = 32, + .ncs = 1, /* single chip select */ + .cs1_mirror = 1, + .rtt_wr = 1, /* DDR3_RTT_60_OHM, RTT_Wr = RZQ/4 */ + .rtt_nom = 1, /* DDR3_RTT_60_OHM, RTT_Nom = RZQ/4 */ + .walat = 1, /* Write additional latency */ + .ralat = 5, /* Read additional latency */ + .mif3_mode = 3, /* Command prediction working mode */ + .bi_on = 1, /* Bank interleaving enabled */ + .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ + .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ + .refsel = 1, /* Refresh cycles at 32KHz */ + .refr = 3, /* 4 refresh commands per refresh cycle */ +}; + +/* DDR3 32bit */ +static const struct mx6_ddr_sysinfo dhcom_ddr_32bit = { + /* width of data bus:0=16,1=32,2=64 */ + .dsize = 1, + .cs_density = 32, .ncs = 1, /* single chip select */ .cs1_mirror = 1, .rtt_wr = 1, /* DDR3_RTT_60_OHM, RTT_Wr = RZQ/4 */ @@ -392,6 +482,81 @@ static void setup_iomux_usb(void) SETUP_IOMUX_PADS(usb_pads); } + +/* DRAM */ +static void dhcom_spl_dram_init(void) +{ + enum dhcom_ddr3_code ddr3_code = dhcom_get_ddr3_code(); + + if (is_mx6dq()) { + mx6dq_dram_iocfg(64, &dhcom6dq_ddr_ioregs, + &dhcom6dq_grp_ioregs); + switch (ddr3_code) { + default: + printf("imx6qd: unsupported ddr3 code %d\n", ddr3_code); + printf(" choosing 1024 MB\n"); + /* fall through */ + case DH_DDR3_SIZE_1GIB: + mx6_dram_cfg(&dhcom_ddr_64bit, + &dhcom_mmdc_calib_4x2g_1066, + &dhcom_mem_ddr_2g); + break; + case DH_DDR3_SIZE_2GIB: + mx6_dram_cfg(&dhcom_ddr_64bit, + &dhcom_mmdc_calib_4x4g_1066, + &dhcom_mem_ddr_4g); + break; + } + + /* Perform DDR DRAM calibration */ + udelay(100); + mmdc_do_dqs_calibration(&dhcom_ddr_64bit); + + } else if (is_cpu_type(MXC_CPU_MX6DL)) { + mx6sdl_dram_iocfg(64, &dhcom6sdl_ddr_ioregs, + &dhcom6sdl_grp_ioregs); + switch (ddr3_code) { + default: + printf("imx6dl: unsupported ddr3 code %d\n", ddr3_code); + printf(" choosing 1024 MB\n"); + /* fall through */ + case DH_DDR3_SIZE_1GIB: + mx6_dram_cfg(&dhcom_ddr_64bit, + &dhcom_mmdc_calib_4x2g_800, + &dhcom_mem_ddr_2g); + break; + } + + /* Perform DDR DRAM calibration */ + udelay(100); + mmdc_do_dqs_calibration(&dhcom_ddr_64bit); + + } else if (is_cpu_type(MXC_CPU_MX6SOLO)) { + mx6sdl_dram_iocfg(32, &dhcom6sdl_ddr_ioregs, + &dhcom6sdl_grp_ioregs); + switch (ddr3_code) { + default: + printf("imx6s: unsupported ddr3 code %d\n", ddr3_code); + printf(" choosing 512 MB\n"); + /* fall through */ + case DH_DDR3_SIZE_512MIB: + mx6_dram_cfg(&dhcom_ddr_32bit, + &dhcom_mmdc_calib_2x2g_800, + &dhcom_mem_ddr_2g); + break; + case DH_DDR3_SIZE_1GIB: + mx6_dram_cfg(&dhcom_ddr_32bit, + &dhcom_mmdc_calib_2x4g_800, + &dhcom_mem_ddr_4g); + break; + } + + /* Perform DDR DRAM calibration */ + udelay(100); + mmdc_do_dqs_calibration(&dhcom_ddr_32bit); + } +} + void board_init_f(ulong dummy) { /* setup AIPS and disable watchdog */ @@ -415,18 +580,8 @@ void board_init_f(ulong dummy) /* UART clocks enabled and gd valid - init serial console */ preloader_console_init(); - /* Start the DDR DRAM */ - if (is_mx6dq()) - mx6dq_dram_iocfg(dhcom_mem_ddr.width, &dhcom6dq_ddr_ioregs, - &dhcom6dq_grp_ioregs); - else - mx6sdl_dram_iocfg(dhcom_mem_ddr.width, &dhcom6sdl_ddr_ioregs, - &dhcom6sdl_grp_ioregs); - mx6_dram_cfg(&dhcom_ddr_info, &dhcom_mmdc_calib, &dhcom_mem_ddr); - - /* Perform DDR DRAM calibration */ - udelay(100); - mmdc_do_dqs_calibration(&dhcom_ddr_info); + /* DDR3 initialization */ + dhcom_spl_dram_init(); /* Clear the BSS. */ memset(__bss_start, 0, __bss_end - __bss_start); From bbbb50f9fdec4bee5a0ae0238100a57b09a4b719 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Thu, 5 Jul 2018 20:58:24 -0500 Subject: [PATCH 47/51] imx: i.mx6q: imx6q_logic: Migrate to SPL and enable SDP Since the vast majority of i.MX6 boards are migrating to SPL, this patch converts im6q_logic to SPL and enables the SDP for loading SPL and u-boot.img over USB. The Falcon mode only supports NAND flash as of now due to limited space/RAM, but all i.MX6D/Q SOM's from Logic PD have internal NAND from which to boot. Signed-off-by: Adam Ford --- arch/arm/mach-imx/mx6/Kconfig | 3 +- board/logicpd/imx6/imx6logic.c | 141 +++++++++++++++++++++++++++ board/logicpd/imx6/mx6q_2x_MT41K512M16HA.cfg | 111 --------------------- configs/imx6q_logic_defconfig | 47 +++++++-- include/configs/imx6_logic.h | 26 ++++- 5 files changed, 208 insertions(+), 120 deletions(-) delete mode 100644 board/logicpd/imx6/mx6q_2x_MT41K512M16HA.cfg diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index 3c87ece..d4bc60a 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -205,6 +205,8 @@ config TARGET_MX6CUBOXI config TARGET_MX6LOGICPD bool "Logic PD i.MX6 SOM" + select MX6Q + select SUPPORT_SPL select BOARD_EARLY_INIT_F select BOARD_LATE_INIT select DM @@ -213,7 +215,6 @@ config TARGET_MX6LOGICPD select DM_I2C select DM_MMC select DM_PMIC - select DM_REGULATOR select OF_CONTROL config TARGET_MX6MEMCAL diff --git a/board/logicpd/imx6/imx6logic.c b/board/logicpd/imx6/imx6logic.c index 8440563..ce1c8a5 100644 --- a/board/logicpd/imx6/imx6logic.c +++ b/board/logicpd/imx6/imx6logic.c @@ -182,3 +182,144 @@ int board_late_init(void) return 0; } + +#ifdef CONFIG_SPL_BUILD +#include +#include +#include +#include + +#ifdef CONFIG_SPL_OS_BOOT +int spl_start_uboot(void) +{ + /* break into full u-boot on 'c' */ + if (serial_tstc() && serial_getc() == 'c') + return 1; + + return 0; +} +#endif + +static void ccgr_init(void) +{ + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + writel(0x00C03F3F, &ccm->CCGR0); + writel(0x0030FC03, &ccm->CCGR1); + writel(0x0FFFC000, &ccm->CCGR2); + writel(0x3FF00000, &ccm->CCGR3); + writel(0xFFFFF300, &ccm->CCGR4); + writel(0x0F0000F3, &ccm->CCGR5); + writel(0x00000FFF, &ccm->CCGR6); +} + +static int mx6q_dcd_table[] = { + MX6_IOM_GRP_DDR_TYPE, 0x000C0000, + MX6_IOM_GRP_DDRPKE, 0x00000000, + MX6_IOM_DRAM_SDCLK_0, 0x00000030, + MX6_IOM_DRAM_SDCLK_1, 0x00000030, + MX6_IOM_DRAM_CAS, 0x00000030, + MX6_IOM_DRAM_RAS, 0x00000030, + MX6_IOM_GRP_ADDDS, 0x00000030, + MX6_IOM_DRAM_RESET, 0x00000030, + MX6_IOM_DRAM_SDBA2, 0x00000000, + MX6_IOM_DRAM_SDODT0, 0x00000030, + MX6_IOM_DRAM_SDODT1, 0x00000030, + MX6_IOM_GRP_CTLDS, 0x00000030, + MX6_IOM_DDRMODE_CTL, 0x00020000, + MX6_IOM_DRAM_SDQS0, 0x00000030, + MX6_IOM_DRAM_SDQS1, 0x00000030, + MX6_IOM_DRAM_SDQS2, 0x00000030, + MX6_IOM_DRAM_SDQS3, 0x00000030, + MX6_IOM_GRP_DDRMODE, 0x00020000, + MX6_IOM_GRP_B0DS, 0x00000030, + MX6_IOM_GRP_B1DS, 0x00000030, + MX6_IOM_GRP_B2DS, 0x00000030, + MX6_IOM_GRP_B3DS, 0x00000030, + MX6_IOM_DRAM_DQM0, 0x00000030, + MX6_IOM_DRAM_DQM1, 0x00000030, + MX6_IOM_DRAM_DQM2, 0x00000030, + MX6_IOM_DRAM_DQM3, 0x00000030, + MX6_MMDC_P0_MDSCR, 0x00008000, + MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003, + MX6_MMDC_P0_MPWLDECTRL0, 0x002D003A, + MX6_MMDC_P0_MPWLDECTRL1, 0x0038002B, + MX6_MMDC_P0_MPDGCTRL0, 0x03340338, + MX6_MMDC_P0_MPDGCTRL1, 0x0334032C, + MX6_MMDC_P0_MPRDDLCTL, 0x4036383C, + MX6_MMDC_P0_MPWRDLCTL, 0x2E384038, + MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333, + MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333, + MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333, + MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333, + MX6_MMDC_P0_MPMUR0, 0x00000800, + MX6_MMDC_P0_MDPDC, 0x00020036, + MX6_MMDC_P0_MDOTC, 0x09444040, + MX6_MMDC_P0_MDCFG0, 0xB8BE7955, + MX6_MMDC_P0_MDCFG1, 0xFF328F64, + MX6_MMDC_P0_MDCFG2, 0x01FF00DB, + MX6_MMDC_P0_MDMISC, 0x00011740, + MX6_MMDC_P0_MDSCR, 0x00008000, + MX6_MMDC_P0_MDRWD, 0x000026D2, + MX6_MMDC_P0_MDOR, 0x00BE1023, + MX6_MMDC_P0_MDASP, 0x00000047, + MX6_MMDC_P0_MDCTL, 0x85190000, + MX6_MMDC_P0_MDSCR, 0x00888032, + MX6_MMDC_P0_MDSCR, 0x00008033, + MX6_MMDC_P0_MDSCR, 0x00008031, + MX6_MMDC_P0_MDSCR, 0x19408030, + MX6_MMDC_P0_MDSCR, 0x04008040, + MX6_MMDC_P0_MDREF, 0x00007800, + MX6_MMDC_P0_MPODTCTRL, 0x00000007, + MX6_MMDC_P0_MDPDC, 0x00025576, + MX6_MMDC_P0_MAPSR, 0x00011006, + MX6_MMDC_P0_MDSCR, 0x00000000, + /* enable AXI cache for VDOA/VPU/IPU */ + + MX6_IOMUXC_GPR4, 0xF00000CF, + /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ + MX6_IOMUXC_GPR6, 0x007F007F, + MX6_IOMUXC_GPR7, 0x007F007F, +}; + +static void ddr_init(int *table, int size) +{ + int i; + + for (i = 0; i < size / 2 ; i++) + writel(table[2 * i + 1], table[2 * i]); +} + +static void spl_dram_init(void) +{ + if (is_mx6dq()) + ddr_init(mx6q_dcd_table, ARRAY_SIZE(mx6q_dcd_table)); +} + +void board_init_f(ulong dummy) +{ + /* DDR initialization */ + spl_dram_init(); + + /* setup AIPS and disable watchdog */ + arch_cpu_init(); + + ccgr_init(); + gpr_init(); + + /* iomux and setup of uart and NAND pins */ + board_early_init_f(); + + /* setup GP timer */ + timer_init(); + + /* UART clocks enabled and gd valid - init serial console */ + preloader_console_init(); + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + /* load/boot image from boot device */ + board_init_r(NULL, 0); +} +#endif diff --git a/board/logicpd/imx6/mx6q_2x_MT41K512M16HA.cfg b/board/logicpd/imx6/mx6q_2x_MT41K512M16HA.cfg deleted file mode 100644 index 6d7e29d..0000000 --- a/board/logicpd/imx6/mx6q_2x_MT41K512M16HA.cfg +++ /dev/null @@ -1,111 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2017 Logic PD, Inc. - * Adam Ford - * - * Refer doc/README.imximage for more details about how-to configure - * and create imximage boot image - * - * The syntax is taken as close as possible with the kwbimage - */ - -#include - -/* image version */ -IMAGE_VERSION 2 - -BOOT_OFFSET FLASH_OFFSET_STANDARD - -/* - * Device Configuration Data (DCD) - * - * Each entry must have the format: - * Addr-type Address Value - * - * where: - * Addr-type register length (1,2 or 4 bytes) - * Address absolute address of the register - * value value to be stored in the register - */ - -#define __ASSEMBLY__ -#include -#include "asm/arch-mx6/mx6-ddr.h" -#include "asm/arch-mx6/iomux.h" -#include "asm/arch-mx6/crm_regs.h" - -DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000 -DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000 -DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00000030 -DATA 4, MX6_IOM_DRAM_CAS, 0x00000030 -DATA 4, MX6_IOM_DRAM_RAS, 0x00000030 -DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030 -DATA 4, MX6_IOM_DRAM_RESET, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000 -DATA 4, MX6_IOM_DRAM_SDODT0, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDODT1, 0x00000030 -DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030 -DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000 -DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030 -DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000 -DATA 4, MX6_IOM_GRP_B0DS, 0x00000030 -DATA 4, MX6_IOM_GRP_B1DS, 0x00000030 -DATA 4, MX6_IOM_GRP_B2DS, 0x00000030 -DATA 4, MX6_IOM_GRP_B3DS, 0x00000030 -DATA 4, MX6_IOM_DRAM_DQM0, 0x00000030 -DATA 4, MX6_IOM_DRAM_DQM1, 0x00000030 -DATA 4, MX6_IOM_DRAM_DQM2, 0x00000030 -DATA 4, MX6_IOM_DRAM_DQM3, 0x00000030 -DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000 -DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003 -DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x002D003A -DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x0038002B -DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x03340338 -DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x0334032C -DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x4036383C -DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x2E384038 -DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333 -DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333 -DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333 -DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333 -DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 -DATA 4, MX6_MMDC_P0_MDPDC, 0x00020036 -DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040 -DATA 4, MX6_MMDC_P0_MDCFG0, 0xB8BE7955 -DATA 4, MX6_MMDC_P0_MDCFG1, 0xFF328F64 -DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB -DATA 4, MX6_MMDC_P0_MDMISC, 0x00011740 -DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000 -DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2 -DATA 4, MX6_MMDC_P0_MDOR, 0x00BE1023 -DATA 4, MX6_MMDC_P0_MDASP, 0x00000047 -DATA 4, MX6_MMDC_P0_MDCTL, 0x85190000 -DATA 4, MX6_MMDC_P0_MDSCR, 0x00888032 -DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 -DATA 4, MX6_MMDC_P0_MDSCR, 0x00008031 -DATA 4, MX6_MMDC_P0_MDSCR, 0x19408030 -DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 -DATA 4, MX6_MMDC_P0_MDREF, 0x00007800 -DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00000007 -DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576 -DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006 -DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 - -/* set the default clock gate to save power */ -DATA 4, CCM_CCGR0, 0x00C03F3F -DATA 4, CCM_CCGR1, 0x0030FC03 -DATA 4, CCM_CCGR2, 0x0FFFC000 -DATA 4, CCM_CCGR3, 0x3FF00000 -DATA 4, CCM_CCGR4, 0xFFFFF300 -DATA 4, CCM_CCGR5, 0x0F0000F3 -DATA 4, CCM_CCGR6, 0x00000FFF - -/* enable AXI cache for VDOA/VPU/IPU */ -DATA 4 MX6_IOMUXC_GPR4 0xF00000CF -/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ -DATA 4 MX6_IOMUXC_GPR6 0x007F007F -DATA 4 MX6_IOMUXC_GPR7 0x007F007F diff --git a/configs/imx6q_logic_defconfig b/configs/imx6q_logic_defconfig index f0974bf..7d921cd 100644 --- a/configs/imx6q_logic_defconfig +++ b/configs/imx6q_logic_defconfig @@ -1,39 +1,74 @@ CONFIG_ARM=y CONFIG_ARCH_MX6=y CONFIG_SYS_TEXT_BASE=0x17800000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_TARGET_MX6LOGICPD=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SYS_MALLOC_F_LEN=0x400 +CONFIG_SPL=y CONFIG_DEFAULT_DEVICE_TREE="imx6q-logicpd" CONFIG_DISTRO_DEFAULTS=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/logicpd/imx6/mx6q_2x_MT41K512M16HA.cfg,MX6Q" +CONFIG_TPL_SYS_MALLOC_F_LEN=0x400 +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" CONFIG_BOOTDELAY=3 # CONFIG_USE_BOOTCOMMAND is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_DMA_SUPPORT=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_NAND_SUPPORT=y +CONFIG_SPL_OS_BOOT=y +CONFIG_SPL_USB_HOST_SUPPORT=y +CONFIG_SPL_USB_GADGET_SUPPORT=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_SPL_WATCHDOG_SUPPORT=y CONFIG_SYS_PROMPT="i.MX6 Logic # " +CONFIG_CMD_SPL=y +CONFIG_CMD_SPL_WRITE_SIZE=0x20000 CONFIG_CMD_MEMTEST=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND_TRIMFFS=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_SDP=y +CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_CACHE=y +# CONFIG_CMD_LED is not set CONFIG_CMD_PMIC=y -CONFIG_CMD_REGULATOR=y CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand" -CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:4m(uboot),1m(env),16m(kernel),1m(dtb),-(fs)" +CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:2m(spl),2m(uboot),1m(env),16m(kernel),1m(dtb),-(fs)" +CONFIG_CMD_UBI=y +CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_IS_IN_NAND=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_SPL_DM=y +CONFIG_PCF8575_GPIO=y CONFIG_SYS_I2C_MXC=y +CONFIG_LED=y +CONFIG_LED_GPIO=y CONFIG_FSL_ESDHC=y CONFIG_NAND=y CONFIG_NAND_MXS=y CONFIG_PHYLIB=y -CONFIG_PHY_SMSC=y +CONFIG_PHY_ATHEROS=y CONFIG_FEC_MXC=y CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y CONFIG_PINCTRL_IMX6=y CONFIG_DM_PMIC_PFUZE100=y -CONFIG_DM_REGULATOR_PFUZE100=y CONFIG_MXC_UART=y +CONFIG_USB=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y diff --git a/include/configs/imx6_logic.h b/include/configs/imx6_logic.h index 0226510..40eb84c 100644 --- a/include/configs/imx6_logic.h +++ b/include/configs/imx6_logic.h @@ -11,6 +11,10 @@ #define CONFIG_MXC_UART_BASE UART1_BASE #define CONSOLE_DEV "ttymxc0" +#ifdef CONFIG_SPL +#include "imx6_spl.h" +#endif + #include "mx6_common.h" /* Size of malloc() pool */ @@ -132,7 +136,7 @@ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) /* Environment organization */ -#define CONFIG_ENV_SIZE (8 * 1024) +#define CONFIG_ENV_SIZE (1024 * 1024) #define CONFIG_ENV_OFFSET 0x400000 #define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE @@ -143,7 +147,7 @@ #define CONFIG_SYS_NAND_ONFI_DETECTION #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x200000 - +#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00500000 /* MTD device */ # define CONFIG_MTD_DEVICE # define CONFIG_MTD_PARTITIONS @@ -153,4 +157,22 @@ /* EEPROM contains serial no, MAC addr and other Logic PD info */ #define CONFIG_I2C_EEPROM +/* USB Configs */ +#ifdef CONFIG_CMD_USB +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 /* Enabled USB controller number */ +#endif + +/* Falcon Mode */ +#define CONFIG_SPL_FS_LOAD_ARGS_NAME "args" +#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage" +#define CONFIG_SYS_SPL_ARGS_ADDR 0x15000000 + +/* Falcon Mode - MMC support: args@1MB kernel@2MB */ +#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x800 /* 1MB */ +#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (CONFIG_CMD_SPL_WRITE_SIZE / 512) +#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x1000 /* 2MB */ + #endif /* __IMX6LOGIC_CONFIG_H */ From e16f2de0c48fdaab461ecd4d6f1890fbdaf5ef63 Mon Sep 17 00:00:00 2001 From: Ludwig Zenz Date: Fri, 6 Jul 2018 11:26:03 +0200 Subject: [PATCH 48/51] ARM: dh_imx6: enable GigaDevice, Macronix, and Winbond SPI Flash support in Kconfig In preparation for delivery bottlenecks, enable support for GigaDevice, Macronix, and Winbond nor flash chips. Signed-off-by: Ludwig Zenz --- configs/dh_imx6_defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/configs/dh_imx6_defconfig b/configs/dh_imx6_defconfig index db1460b..8f45531 100644 --- a/configs/dh_imx6_defconfig +++ b/configs/dh_imx6_defconfig @@ -39,7 +39,10 @@ CONFIG_BOOTCOUNT_LIMIT=y CONFIG_SYS_BOOTCOUNT_ADDR=0x00900000 CONFIG_FSL_ESDHC=y CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_WINBOND=y CONFIG_PHYLIB=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y From 7e1a0483c36a8a53c207123262a1d108588517ad Mon Sep 17 00:00:00 2001 From: Holger Dengler Date: Fri, 6 Jul 2018 16:10:00 +0200 Subject: [PATCH 49/51] tools/imximage: get HAB information from header Signing parts of a u-boot imximage for image verification in High Assurance Boot (HAB) in a post-build process, requires some information from the imximage header. Currently, this information is only provided during the image build, which makes the transfer of this information to the post-build process harder than necessary. The i.MX HAB information (start and length) can be calculated either by using information from the image-configuration file, or from the information in the flash header of the imximage. The advantage of using information from flash header is, that they are not only available during image creation, but also available if existing images are processed. Example: $ tools/mkimage -l u-boot.imx Image Type: Freescale IMX Boot Image Image Ver: 2 (i.MX53/6/7 compatible) Mode: DCD Data Size: 483328 Bytes = 472.00 KiB = 0.46 MiB Load Address: 877ff420 Entry Point: 87800000 HAB Blocks: 0x877ff400 0x00000000 0x00071c00 DCD Blocks: 0x00910000 0x0000002c 0x00000208 Signed-off-by: Holger Dengler Tested-by: Bryan O'Donoghue --- tools/imximage.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/tools/imximage.c b/tools/imximage.c index 5f63bf8..d7c0b6e 100644 --- a/tools/imximage.c +++ b/tools/imximage.c @@ -506,8 +506,7 @@ static void print_hdr_v2(struct imx_header *imx_hdr) genimg_print_size(hdr_v2->boot_data.size); printf("Load Address: %08x\n", (uint32_t)fhdr_v2->boot_data_ptr); printf("Entry Point: %08x\n", (uint32_t)fhdr_v2->entry); - if (fhdr_v2->csf && (imximage_ivt_offset != UNDEFINED) && - (imximage_csf_size != UNDEFINED)) { + if (fhdr_v2->csf) { uint16_t dcdlen; int offs; @@ -515,10 +514,16 @@ static void print_hdr_v2(struct imx_header *imx_hdr) offs = (char *)&hdr_v2->data.dcd_table - (char *)hdr_v2; + /* + * The HAB block is the first part of the image, from + * start of IVT header (fhdr_v2->self) to the start of + * the CSF block (fhdr_v2->csf). So HAB size is + * calculated as: + * HAB_size = fhdr_v2->csf - fhdr_v2->self + */ printf("HAB Blocks: 0x%08x 0x%08x 0x%08x\n", (uint32_t)fhdr_v2->self, 0, - hdr_v2->boot_data.size - imximage_ivt_offset - - imximage_csf_size); + (uint32_t)(fhdr_v2->csf - fhdr_v2->self)); printf("DCD Blocks: 0x00910000 0x%08x 0x%08x\n", offs, be16_to_cpu(dcdlen)); } From 0d38a5fd44b773c718ee4e834d34cf8c7912e200 Mon Sep 17 00:00:00 2001 From: Martin Kaiser Date: Mon, 16 Jul 2018 22:11:57 +0200 Subject: [PATCH 50/51] mx25: fix the offset between the USB ports' registers The USBOH module on imx25 chips contains two USB controllers which are called USB OTG Controller and USB Host Controller. Each one has its EHCI root hub. The OTG Controller's EHCI registers start at offset 0, the Host Controller's registers start at offset 0x400. We set CONFIG_MXC_USB_PORT=0 to select the OTG Controller and 1 for the Host Controller. Therefore, IMX_USB_PORT_OFFSET must be 0x400. Using this setting, the Host Controller starts working on my imx25 board. Please note that the imx25 reference manual claims that the Host Controller's registers start at 0x200. This is not correct. The Linux Kernel uses the correct offset 0x400 in imx25.dtsi. Signed-off-by: Martin Kaiser Reviewed-by: Fabio Estevam --- arch/arm/include/asm/arch-mx25/imx-regs.h | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/arm/include/asm/arch-mx25/imx-regs.h b/arch/arm/include/asm/arch-mx25/imx-regs.h index f4abbde..cee42e5 100644 --- a/arch/arm/include/asm/arch-mx25/imx-regs.h +++ b/arch/arm/include/asm/arch-mx25/imx-regs.h @@ -359,7 +359,12 @@ struct cspi_regs { #define IMX_IIM_BASE (0x53FF0000) #define IIM_BASE_ADDR IMX_IIM_BASE #define IMX_USB_BASE (0x53FF4000) -#define IMX_USB_PORT_OFFSET 0x200 +/* + * This is in contradiction to the imx25 reference manual, which says that + * port 1's registers start at 0x53FF4200. The correct base address for + * port 1 is 0x53FF4400. The kernel uses 0x53FF4400 as well. + */ +#define IMX_USB_PORT_OFFSET 0x400 #define IMX_CSI_BASE (0x53FF8000) #define IMX_DRYICE_BASE (0x53FFC000) From f97f167107b33fc6596561dae1309571ade39055 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Fri, 20 Jul 2018 08:25:53 -0500 Subject: [PATCH 51/51] configs: imx6q_logic: Cleanup ramdiskaddr and fdtaddr There are already definitions for ramdisk_addr_r and fdt_addr_r, so having a duplicate copy called ramdiskaddr and fdtaddr is confusing. This patch converts any references to ramdisk_addr_r and fdt_addr_r and removes the duplicates. Signed-off-by: Adam Ford --- include/configs/imx6_logic.h | 20 +++++++++----------- 1 file changed, 9 insertions(+), 11 deletions(-) diff --git a/include/configs/imx6_logic.h b/include/configs/imx6_logic.h index 40eb84c..a8f02d3 100644 --- a/include/configs/imx6_logic.h +++ b/include/configs/imx6_logic.h @@ -35,10 +35,8 @@ "script=boot.scr\0" \ "image=zImage\0" \ "bootm_size=0x10000000\0" \ - "fdt_addr_r=0x18000000\0" \ - "fdt_addr=0x18000000\0" \ - "ramdisk_addr_r=0x13000000\0" \ - "ramdiskaddr=0x13000000\0" \ + "fdt_addr_r=0x13000000\0" \ + "ramdisk_addr_r=0x14000000\0" \ "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ "ramdisk_file=rootfs.cpio.uboot\0" \ "boot_fdt=try\0" \ @@ -60,25 +58,25 @@ " source\0" \ "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image};" \ " setenv kernelsize ${filesize}\0" \ - "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ - "loadramdisk=fatload mmc ${mmcdev}:${mmcpart} ${ramdiskaddr}" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdt_file}\0" \ + "loadramdisk=fatload mmc ${mmcdev}:${mmcpart} ${ramdisk_addr_r}" \ " ${ramdisk_file}; setenv ramdisksize ${filesize}\0" \ "mmcboot=echo Booting from mmc...; run mmcargs; run loadimage;" \ - " run loadfdt; bootz ${loadaddr} - ${fdt_addr}\0" \ + " run loadfdt; bootz ${loadaddr} - ${fdt_addr_r}\0" \ "mmcramboot=run ramargs; run loadimage;" \ " run loadfdt; run loadramdisk;" \ - " bootz ${loadaddr} ${ramdiskaddr} ${fdt_addr}\0" \ + " bootz ${loadaddr} ${ramdisk_addr_r} ${fdt_addr_r}\0" \ "nandboot=echo Booting from nand ...; " \ " run nandargs;" \ " nand read ${loadaddr} kernel ${kernelsize};" \ " nand read ${fdt_addr} dtb;" \ " bootz ${loadaddr} - ${fdt_addr}\0" \ "nandramboot=echo Booting RAMdisk from nand ...; " \ - " nand read ${ramdiskaddr} fs ${ramdisksize};" \ + " nand read ${ramdisk_addr_r} fs ${ramdisksize};" \ " nand read ${loadaddr} kernel ${kernelsize};" \ - " nand read ${fdt_addr} dtb;" \ + " nand read ${fdt_addr_r} dtb;" \ " run ramargs;" \ - " bootz ${loadaddr} ${ramdiskaddr} ${fdt_addr}\0" \ + " bootz ${loadaddr} ${ramdisk_addr_r} ${fdt_addr_r}\0" \ "netargs=setenv bootargs console=${console},${baudrate} " \ "root=/dev/nfs" \ " ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \