Eran Liberty
20 years ago
committed by
Jon Loeliger
parent
63be111e72
commit
f046ccd15c
@ -0,0 +1,45 @@ |
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#
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# Copyright 2004 Freescale Semiconductor, Inc.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk |
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LIB = lib$(BOARD).a
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OBJS := $(BOARD).o
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$(LIB): $(OBJS) $(SOBJS) |
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$(AR) crv $@ $(OBJS)
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clean: |
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rm -f $(SOBJS) $(OBJS)
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distclean: clean |
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rm -f $(LIB) core *.bak .depend
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#########################################################################
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.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) |
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$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
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-include .depend |
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#########################################################################
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@ -0,0 +1,27 @@ |
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#
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# Copyright 2004 Freescale Semiconductor, Inc.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
|
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# modify it under the terms of the GNU General Public License as
|
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# published by the Free Software Foundation; either version 2 of
|
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
|
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
|
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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#
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# MPC83xxADS
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#
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TEXT_BASE = 0xFE700000
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@ -0,0 +1,278 @@ |
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/*
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* Copyright Freescale Semiconductor, Inc. |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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* |
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* Change log: |
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* 20050101: Eran Liberty (liberty@freescale.com) |
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* Initial file creating (porting from 85XX & 8260) |
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*/ |
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#include <common.h> |
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#include <ioports.h> |
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#include <mpc83xx.h> |
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#include <asm/mpc8349_pci.h> |
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#include <i2c.h> |
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#include <spd.h> |
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#include <miiphy.h> |
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#if defined(CONFIG_PCI) |
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#include <pci.h> |
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#endif |
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#if defined(CONFIG_SPD_EEPROM) |
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#include <spd_sdram.h> |
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#endif |
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int fixed_sdram(void); |
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void sdram_init(void); |
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int board_early_init_f (void) |
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{ |
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volatile u8* bcsr = (volatile u8*)CFG_BCSR; |
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/* Enable flash write */ |
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bcsr[1] &= ~0x01; |
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return 0; |
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} |
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#define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1) |
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long int initdram (int board_type) |
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{ |
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volatile immap_t *im = (immap_t *)CFG_IMMRBAR; |
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u32 msize = 0; |
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if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) |
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return -1; |
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/* DDR SDRAM - Main SODIMM */ |
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im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR; |
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#if defined(CONFIG_SPD_EEPROM) |
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msize = spd_sdram(NULL); |
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#else |
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msize = fixed_sdram(); |
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#endif |
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/*
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* Initialize SDRAM if it is on local bus. |
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*/ |
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sdram_init(); |
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puts(" DDR RAM: "); |
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/* return total bus SDRAM size(bytes) -- DDR */ |
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return (msize * 1024 * 1024); |
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} |
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#if !defined(CONFIG_SPD_EEPROM) |
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/*************************************************************************
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* fixed sdram init -- doesn't use serial presence detect. |
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************************************************************************/ |
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int fixed_sdram(void) |
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{ |
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volatile immap_t *im = (immap_t *)CFG_IMMRBAR; |
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u32 msize = 0; |
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u32 ddr_size; |
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u32 ddr_size_log2; |
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msize = CFG_DDR_SIZE; |
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for (ddr_size = msize << 20, ddr_size_log2 = 0; |
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(ddr_size > 1); |
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ddr_size = ddr_size>>1, ddr_size_log2++) { |
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if (ddr_size & 1) { |
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return -1; |
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} |
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} |
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im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); |
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#if (CFG_DDR_SIZE != 256) |
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#warning Currenly any ddr size other than 256 is not supported |
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#endif |
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im->ddr.csbnds[0].csbnds = 0x00100017; |
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im->ddr.csbnds[1].csbnds = 0x0018001f; |
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im->ddr.csbnds[2].csbnds = 0x00000007; |
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im->ddr.csbnds[3].csbnds = 0x0008000f; |
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im->ddr.cs_config[0] = CFG_DDR_CONFIG; |
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im->ddr.cs_config[1] = CFG_DDR_CONFIG; |
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im->ddr.cs_config[2] = CFG_DDR_CONFIG; |
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im->ddr.cs_config[3] = CFG_DDR_CONFIG; |
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im->ddr.timing_cfg_1 = |
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3 << TIMING_CFG1_PRETOACT_SHIFT | |
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7 << TIMING_CFG1_ACTTOPRE_SHIFT | |
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3 << TIMING_CFG1_ACTTORW_SHIFT | |
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4 << TIMING_CFG1_CASLAT_SHIFT | |
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3 << TIMING_CFG1_REFREC_SHIFT | |
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3 << TIMING_CFG1_WRREC_SHIFT | |
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2 << TIMING_CFG1_ACTTOACT_SHIFT | |
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1 << TIMING_CFG1_WRTORD_SHIFT; |
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im->ddr.timing_cfg_2 = 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT; |
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im->ddr.sdram_cfg = |
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SDRAM_CFG_SREN |
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#if defined(CONFIG_DDR_2T_TIMING) |
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| SDRAM_CFG_2T_EN |
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#endif |
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| 2 << SDRAM_CFG_SDRAM_TYPE_SHIFT; |
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im->ddr.sdram_mode = |
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0x2000 << SDRAM_MODE_ESD_SHIFT | |
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0x0162 << SDRAM_MODE_SD_SHIFT; |
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im->ddr.sdram_interval = 0x045B << SDRAM_INTERVAL_REFINT_SHIFT | |
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0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT; |
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udelay(200); |
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im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; |
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return msize; |
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} |
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#endif/*!CFG_SPD_EEPROM*/ |
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int checkboard (void) |
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{ |
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puts("Board: Freescale MPC8349ADS\n"); |
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return 0; |
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} |
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#if defined(CONFIG_PCI) //copy from mpc85xx
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/*
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* Initialize PCI Devices, report devices found |
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*/ |
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#ifndef CONFIG_PCI_PNP |
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static struct pci_config_table pci_mpc83xxads_config_table[] = { |
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{PCI_ANY_ID,PCI_ANY_ID,PCI_ANY_ID,PCI_ANY_ID, |
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pci_cfgfunc_config_device, {PCI_ENET0_IOADDR, |
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PCI_ENET0_MEMADDR, |
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PCI_COMMON_MEMORY | PCI_COMMAND_MASTER |
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} }, |
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{} |
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} |
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#endif |
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volatile static struct pci_controller hose[] = { |
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{ |
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#ifndef CONFIG_PCI_PNP |
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config_table:pci_mpc83xxads_config_table, |
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#endif |
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}, |
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{ |
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#ifndef CONFIG_PCI_PNP |
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config_table:pci_mpc83xxads_config_table, |
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#endif |
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} |
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}; |
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#endif /* CONFIG_PCI */ |
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void |
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pci_init_board(void) |
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{ |
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#ifdef CONFIG_PCI |
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extern void pci_mpc83xx_init(volatile struct pci_controller *hose); |
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pci_mpc83xx_init(hose); |
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#endif /* CONFIG_PCI */ |
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} |
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/*
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if MPC8349ADS is soldered with SDRAM |
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*/ |
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#if defined(CFG_BR2_PRELIM) \ |
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&& defined(CFG_OR2_PRELIM) \
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&& defined(CFG_LBLAWBAR2_PRELIM) \
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&& defined(CFG_LBLAWAR2_PRELIM) |
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/*
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* Initialize SDRAM memory on the Local Bus. |
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*/ |
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void |
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sdram_init(void) |
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{ |
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volatile immap_t *immap = (immap_t *)CFG_IMMRBAR; |
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volatile lbus8349_t *lbc= &immap->lbus; |
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uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE; |
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puts("\n SDRAM on Local Bus: "); |
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print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); |
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/*
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* Setup SDRAM Base and Option Registers, already done in cpu_init.c |
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*/ |
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/*setup mtrpt, lsrt and lbcr for LB bus*/ |
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lbc->lbcr = CFG_LBC_LBCR; |
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lbc->mrtpr = CFG_LBC_MRTPR; |
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lbc->lsrt = CFG_LBC_LSRT; |
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asm("sync"); |
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/*
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* Configure the SDRAM controller Machine Mode Register. |
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*/ |
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lbc->lsdmr = CFG_LBC_LSDMR_5; /* 0x40636733; normal operation*/ |
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lbc->lsdmr = CFG_LBC_LSDMR_1; /*0x68636733;precharge all the banks*/ |
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asm("sync"); |
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*sdram_addr = 0xff; |
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udelay(100); |
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lbc->lsdmr = CFG_LBC_LSDMR_2;/*0x48636733;auto refresh*/ |
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asm("sync"); |
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/*1 times*/ |
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*sdram_addr = 0xff; |
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udelay(100); |
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/*2 times*/ |
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*sdram_addr = 0xff; |
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udelay(100); |
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/*3 times*/ |
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*sdram_addr = 0xff; |
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udelay(100); |
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/*4 times*/ |
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*sdram_addr = 0xff; |
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udelay(100); |
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/*5 times*/ |
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*sdram_addr = 0xff; |
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udelay(100); |
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/*6 times*/ |
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*sdram_addr = 0xff; |
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udelay(100); |
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/*7 times*/ |
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*sdram_addr = 0xff; |
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udelay(100); |
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/*8 times*/ |
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*sdram_addr = 0xff; |
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udelay(100); |
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lbc->lsdmr = CFG_LBC_LSDMR_4; /*0x58636733;mode register write operation*/ |
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asm("sync"); |
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*sdram_addr = 0xff; |
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udelay(100); |
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lbc->lsdmr = CFG_LBC_LSDMR_5; /*0x40636733;normal operation*/ |
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asm("sync"); |
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*sdram_addr = 0xff; |
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udelay(100); |
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} |
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#else |
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void |
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sdram_init(void) |
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{ |
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put("SDRAM on Local Bus is NOT available!\n"); |
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} |
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#endif |
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@ -0,0 +1,119 @@ |
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/* |
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* Copyright 2004 Freescale Semiconductor, Inc. |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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OUTPUT_ARCH(powerpc) |
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SECTIONS |
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{ |
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/* Read-only sections, merged into text segment: */ |
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. = + SIZEOF_HEADERS; |
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.interp : { *(.interp) } |
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.hash : { *(.hash) } |
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.dynsym : { *(.dynsym) } |
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.dynstr : { *(.dynstr) } |
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.rel.text : { *(.rel.text) } |
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.rela.text : { *(.rela.text) } |
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.rel.data : { *(.rel.data) } |
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.rela.data : { *(.rela.data) } |
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.rel.rodata : { *(.rel.rodata) } |
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.rela.rodata : { *(.rela.rodata) } |
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.rel.got : { *(.rel.got) } |
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.rela.got : { *(.rela.got) } |
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.rel.ctors : { *(.rel.ctors) } |
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.rela.ctors : { *(.rela.ctors) } |
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.rel.dtors : { *(.rel.dtors) } |
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.rela.dtors : { *(.rela.dtors) } |
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.rel.bss : { *(.rel.bss) } |
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.rela.bss : { *(.rela.bss) } |
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.rel.plt : { *(.rel.plt) } |
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.rela.plt : { *(.rela.plt) } |
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.init : { *(.init) } |
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.plt : { *(.plt) } |
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.text : |
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{ |
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cpu/mpc83xx/start.o (.text) |
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*(.text) |
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*(.fixup) |
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*(.got1) |
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. = ALIGN(16); |
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*(.rodata) |
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*(.rodata1) |
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*(.rodata.str1.4) |
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} |
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.fini : { *(.fini) } =0 |
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.ctors : { *(.ctors) } |
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.dtors : { *(.dtors) } |
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|
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/* Read-write section, merged into data segment: */ |
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. = (. + 0x0FFF) & 0xFFFFF000; |
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_erotext = .; |
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PROVIDE (erotext = .); |
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.reloc : |
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{ |
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*(.got) |
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_GOT2_TABLE_ = .; |
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*(.got2) |
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_FIXUP_TABLE_ = .; |
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*(.fixup) |
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} |
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__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; |
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__fixup_entries = (. - _FIXUP_TABLE_) >> 2; |
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|
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.data : |
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{ |
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*(.data) |
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*(.data1) |
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*(.sdata) |
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*(.sdata2) |
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*(.dynamic) |
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CONSTRUCTORS |
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} |
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_edata = .; |
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PROVIDE (edata = .); |
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|
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__u_boot_cmd_start = .; |
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.u_boot_cmd : { *(.u_boot_cmd) } |
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__u_boot_cmd_end = .; |
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|
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|
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__start___ex_table = .; |
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__ex_table : { *(__ex_table) } |
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__stop___ex_table = .; |
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|
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. = ALIGN(4096); |
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__init_begin = .; |
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.text.init : { *(.text.init) } |
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.data.init : { *(.data.init) } |
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. = ALIGN(4096); |
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__init_end = .; |
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|
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__bss_start = .; |
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.bss : |
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{ |
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*(.sbss) *(.scommon) |
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*(.dynbss) |
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*(.bss) |
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*(COMMON) |
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} |
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_end = . ; |
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PROVIDE (end = .); |
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} |
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ENTRY(_start) |
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@ -0,0 +1,53 @@ |
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#
|
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# Copyright 2004 Freescale Semiconductor, Inc.
|
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#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk |
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|
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LIB = lib$(CPU).a
|
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|
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START = start.o \
|
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resetvec.o
|
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|
||||
COBJS = traps.o \
|
||||
cpu.o \
|
||||
cpu_init.o \
|
||||
speed.o \
|
||||
interrupts.o \
|
||||
pci.o \
|
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i2c.o \
|
||||
spd_sdram.o
|
||||
|
||||
OBJS = $(COBJS)
|
||||
|
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all: .depend $(START) $(LIB) |
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|
||||
$(LIB): $(OBJS) |
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$(AR) crv $@ $(OBJS)
|
||||
|
||||
#########################################################################
|
||||
|
||||
.depend: Makefile $(START:.o=.S) $(AOBJS:.o=.S) $(COBJS:.o=.c) |
||||
$(CC) -M $(CFLAGS) $(START:.o=.S) $(COBJS:.o=.c) > $@
|
||||
|
||||
sinclude .depend |
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|
||||
#########################################################################
|
||||
@ -0,0 +1,26 @@ |
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#
|
||||
# Copyright 2004 Freescale Semiconductor, Inc.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi
|
||||
|
||||
PLATFORM_CPPFLAGS += -DCONFIG_MPC83XX -DCONFIG_E300 \
|
||||
-ffixed-r2 -ffixed-r29 -msoft-float
|
||||
@ -0,0 +1,145 @@ |
||||
/*
|
||||
* Copyright 2004 Freescale Semiconductor, Inc. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
* |
||||
* Change log: |
||||
* |
||||
* 20050101: Eran Liberty (liberty@freescale.com) |
||||
* Initial file creating (porting from 85XX & 8260) |
||||
*/ |
||||
|
||||
/*
|
||||
* CPU specific code for the MPC83xx family. |
||||
* |
||||
* Derived from the MPC8260 and MPC85xx. |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <watchdog.h> |
||||
#include <command.h> |
||||
#include <mpc83xx.h> |
||||
#include <asm/processor.h> |
||||
|
||||
|
||||
int checkcpu(void) |
||||
{ |
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
ulong clock = gd->cpu_clk; |
||||
u32 pvr = get_pvr(); |
||||
char buf[32]; |
||||
|
||||
if ((pvr & 0xFFFF0000) != PVR_83xx) { |
||||
puts("Not MPC83xx Family!!!\n"); |
||||
return -1; |
||||
} |
||||
|
||||
puts("CPU: MPC83xx, "); |
||||
switch(pvr) { |
||||
case PVR_8349_REV10: |
||||
break; |
||||
case PVR_8349_REV11: |
||||
break; |
||||
default: |
||||
puts("Rev: Unknown\n"); |
||||
return -1; /* Not sure what this is */ |
||||
} |
||||
printf("Rev: %02x at %s MHz\n",pvr & 0x0000FFFF, strmhz(buf, clock)); |
||||
return 0; |
||||
} |
||||
|
||||
|
||||
void upmconfig (uint upm, uint *table, uint size) |
||||
{ |
||||
hang(); /* FIXME: upconfig() needed? */ |
||||
} |
||||
|
||||
|
||||
int |
||||
do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) |
||||
{ |
||||
ulong msr, addr; |
||||
|
||||
volatile immap_t *immap = (immap_t *) CFG_IMMRBAR; |
||||
|
||||
#ifdef MPC83xx_RESET |
||||
/* Interrupts and MMU off */ |
||||
__asm__ __volatile__ ("mfmsr %0":"=r" (msr):); |
||||
|
||||
msr &= ~( MSR_EE | MSR_IR | MSR_DR); |
||||
__asm__ __volatile__ ("mtmsr %0"::"r" (msr)); |
||||
|
||||
/* enable Reset Control Reg */ |
||||
immap->reset.rpr = 0x52535445; |
||||
|
||||
/* confirm Reset Control Reg is enabled */ |
||||
while(!((immap->reset.rcer) & RCER_CRE)); |
||||
|
||||
printf("Resetting the board."); |
||||
printf("\n"); |
||||
|
||||
udelay(200); |
||||
|
||||
/* perform reset, only one bit */ |
||||
immap->reset.rcr = RCR_SWHR; |
||||
#else |
||||
immap->reset.rmr = RMR_CSRE; /* Checkstop Reset enable */ |
||||
|
||||
/* Interrupts and MMU off */ |
||||
__asm__ __volatile__ ("mfmsr %0":"=r" (msr):); |
||||
|
||||
msr &= ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR); |
||||
__asm__ __volatile__ ("mtmsr %0"::"r" (msr)); |
||||
|
||||
/*
|
||||
* Trying to execute the next instruction at a non-existing address |
||||
* should cause a machine check, resulting in reset |
||||
*/ |
||||
addr = CFG_RESET_ADDRESS; |
||||
|
||||
printf("resetting the board."); |
||||
printf("\n"); |
||||
((void (*)(void)) addr) (); |
||||
#endif |
||||
return 1; |
||||
} |
||||
|
||||
|
||||
/*
|
||||
* Get timebase clock frequency (like cpu_clk in Hz) |
||||
*/ |
||||
|
||||
unsigned long get_tbclk(void) |
||||
{ |
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
ulong tbclk; |
||||
|
||||
tbclk = (gd->bus_clk + 3L) / 4L; |
||||
|
||||
return tbclk; |
||||
} |
||||
|
||||
|
||||
#if defined(CONFIG_WATCHDOG) |
||||
void watchdog_reset (void) |
||||
{ |
||||
hang(); /* FIXME: implement watchdog_reset()? */ |
||||
} |
||||
#endif /* CONFIG_WATCHDOG */ |
||||
@ -0,0 +1,164 @@ |
||||
/*
|
||||
* Copyright 2004 Freescale Semiconductor, Inc. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
* |
||||
* Change log: |
||||
* |
||||
* 20050101: Eran Liberty (liberty@freescale.com) |
||||
* Initial file creating (porting from 85XX & 8260) |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <mpc83xx.h> |
||||
#include <ioports.h> |
||||
|
||||
/*
|
||||
* Breathe some life into the CPU... |
||||
* |
||||
* Set up the memory map, |
||||
* initialize a bunch of registers, |
||||
* initialize the UPM's |
||||
*/ |
||||
void cpu_init_f (volatile immap_t * im) |
||||
{ |
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
/* Pointer is writable since we allocated a register for it */ |
||||
gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET); |
||||
|
||||
/* Clear initial global data */ |
||||
memset ((void *) gd, 0, sizeof (gd_t)); |
||||
|
||||
/* RSR - Reset Status Register - clear all status (4.6.1.3) */ |
||||
gd->reset_status = im->reset.rsr; |
||||
im->reset.rsr = ~(RSR_RES); |
||||
|
||||
/*
|
||||
* RMR - Reset Mode Register |
||||
* contains checkstop reset enable (4.6.1.4) |
||||
*/ |
||||
im->reset.rmr = (RMR_CSRE & (1<<RMR_CSRE_SHIFT)); |
||||
|
||||
/* LCRR - Clock Ratio Register (10.3.1.16) */ |
||||
im->lbus.lcrr = CFG_LCRR; |
||||
|
||||
/* Enable Time Base & Decrimenter ( so we will have udelay() )*/ |
||||
im->sysconf.spcr |= SPCR_TBEN; |
||||
|
||||
/* System General Purpose Register */ |
||||
im->sysconf.sicrh = SICRH_TSOBI1; |
||||
im->sysconf.sicrl = SICRL_LDP_A; |
||||
|
||||
/*
|
||||
* Memory Controller: |
||||
*/ |
||||
|
||||
/* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary
|
||||
* addresses - these have to be modified later when FLASH size |
||||
* has been determined |
||||
*/ |
||||
|
||||
#if defined(CFG_BR0_PRELIM) \ |
||||
&& defined(CFG_OR0_PRELIM) \
|
||||
&& defined(CFG_LBLAWBAR0_PRELIM) \
|
||||
&& defined(CFG_LBLAWAR0_PRELIM) |
||||
im->lbus.bank[0].br = CFG_BR0_PRELIM; |
||||
im->lbus.bank[0].or = CFG_OR0_PRELIM; |
||||
im->sysconf.lblaw[0].bar = CFG_LBLAWBAR0_PRELIM; |
||||
im->sysconf.lblaw[0].ar = CFG_LBLAWAR0_PRELIM; |
||||
#else |
||||
#error CFG_BR0_PRELIM, CFG_OR0_PRELIM, CFG_LBLAWBAR0_PRELIM & CFG_LBLAWAR0_PRELIM must be defined |
||||
#endif |
||||
|
||||
#if defined(CFG_BR1_PRELIM) \ |
||||
&& defined(CFG_OR1_PRELIM) \
|
||||
&& defined(CFG_LBLAWBAR1_PRELIM) \
|
||||
&& defined(CFG_LBLAWAR1_PRELIM) |
||||
im->lbus.bank[1].br = CFG_BR1_PRELIM; |
||||
im->lbus.bank[1].or = CFG_OR1_PRELIM; |
||||
im->sysconf.lblaw[1].bar = CFG_LBLAWBAR1_PRELIM; |
||||
im->sysconf.lblaw[1].ar = CFG_LBLAWAR1_PRELIM; |
||||
#endif |
||||
#if defined(CFG_BR2_PRELIM) \ |
||||
&& defined(CFG_OR2_PRELIM) \
|
||||
&& defined(CFG_LBLAWBAR2_PRELIM) \
|
||||
&& defined(CFG_LBLAWAR2_PRELIM) |
||||
im->lbus.bank[2].br = CFG_BR2_PRELIM; |
||||
im->lbus.bank[2].or = CFG_OR2_PRELIM; |
||||
im->sysconf.lblaw[2].bar = CFG_LBLAWBAR2_PRELIM; |
||||
im->sysconf.lblaw[2].ar = CFG_LBLAWAR2_PRELIM; |
||||
#endif |
||||
#if defined(CFG_BR3_PRELIM) \ |
||||
&& defined(CFG_OR3_PRELIM) \
|
||||
&& defined(CFG_LBLAWBAR3_PRELIM) \
|
||||
&& defined(CFG_LBLAWAR3_PRELIM) |
||||
im->lbus.bank[3].br = CFG_BR3_PRELIM; |
||||
im->lbus.bank[3].or = CFG_OR3_PRELIM; |
||||
im->sysconf.lblaw[3].bar = CFG_LBLAWBAR3_PRELIM; |
||||
im->sysconf.lblaw[3].ar = CFG_LBLAWAR3_PRELIM; |
||||
#endif |
||||
#if defined(CFG_BR4_PRELIM) \ |
||||
&& defined(CFG_OR4_PRELIM) \
|
||||
&& defined(CFG_LBLAWBAR4_PRELIM) \
|
||||
&& defined(CFG_LBLAWAR4_PRELIM) |
||||
im->lbus.bank[4].br = CFG_BR4_PRELIM; |
||||
im->lbus.bank[4].or = CFG_OR4_PRELIM; |
||||
im->sysconf.lblaw[4].bar = CFG_LBLAWBAR4_PRELIM; |
||||
im->sysconf.lblaw[4].ar = CFG_LBLAWAR4_PRELIM; |
||||
#endif |
||||
#if defined(CFG_BR5_PRELIM) \ |
||||
&& defined(CFG_OR5_PRELIM) \
|
||||
&& defined(CFG_LBLAWBAR5_PRELIM) \
|
||||
&& defined(CFG_LBLAWAR5_PRELIM) |
||||
im->lbus.bank[5].br = CFG_BR5_PRELIM; |
||||
im->lbus.bank[5].or = CFG_OR5_PRELIM; |
||||
im->sysconf.lblaw[5].bar = CFG_LBLAWBAR5_PRELIM; |
||||
im->sysconf.lblaw[5].ar = CFG_LBLAWAR5_PRELIM; |
||||
#endif |
||||
#if defined(CFG_BR6_PRELIM) \ |
||||
&& defined(CFG_OR6_PRELIM) \
|
||||
&& defined(CFG_LBLAWBAR6_PRELIM) \
|
||||
&& defined(CFG_LBLAWAR6_PRELIM) |
||||
im->lbus.bank[6].br = CFG_BR6_PRELIM; |
||||
im->lbus.bank[6].or = CFG_OR6_PRELIM; |
||||
im->sysconf.lblaw[6].bar = CFG_LBLAWBAR6_PRELIM; |
||||
im->sysconf.lblaw[6].ar = CFG_LBLAWAR6_PRELIM; |
||||
#endif |
||||
#if defined(CFG_BR7_PRELIM) \ |
||||
&& defined(CFG_OR7_PRELIM) \
|
||||
&& defined(CFG_LBLAWBAR7_PRELIM) \
|
||||
&& defined(CFG_LBLAWAR7_PRELIM) |
||||
im->lbus.bank[7].br = CFG_BR7_PRELIM; |
||||
im->lbus.bank[7].or = CFG_OR7_PRELIM; |
||||
im->sysconf.lblaw[7].bar = CFG_LBLAWBAR7_PRELIM; |
||||
im->sysconf.lblaw[7].ar = CFG_LBLAWAR7_PRELIM; |
||||
#endif |
||||
} |
||||
|
||||
|
||||
/*
|
||||
* Initialize higher level parts of CPU like time base and timers. |
||||
*/ |
||||
|
||||
int cpu_init_r (void) |
||||
{ |
||||
return 0; |
||||
} |
||||
|
||||
@ -0,0 +1,251 @@ |
||||
/*
|
||||
* (C) Copyright 2003,Motorola Inc. |
||||
* Xianghua Xiao <x.xiao@motorola.com> |
||||
* Adapted for Motorola 85xx chip. |
||||
* |
||||
* (C) Copyright 2003 |
||||
* Gleb Natapov <gnatapov@mrv.com> |
||||
* Some bits are taken from linux driver writen by adrian@humboldt.co.uk |
||||
* |
||||
* Hardware I2C driver for MPC107 PCI bridge. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
* |
||||
* Change log: |
||||
* |
||||
* 20050101: Eran Liberty (liberty@freescale.com) |
||||
* Initial file creating (porting from 85XX & 8260) |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <command.h> |
||||
#include <asm/io.h> |
||||
|
||||
#ifdef CONFIG_HARD_I2C |
||||
#include <i2c.h> |
||||
#include <asm/i2c.h> |
||||
|
||||
#ifdef CONFIG_MPC8349ADS |
||||
i2c_t * mpc8349_i2c = (i2c_t*)(CFG_IMMRBAR + CFG_I2C_OFFSET); |
||||
#endif |
||||
|
||||
void |
||||
i2c_init(int speed, int slaveadd) |
||||
{ |
||||
/* stop I2C controller */ |
||||
writeb(0x00 , &I2C->cr); |
||||
|
||||
/* set clock */ |
||||
writeb(0x3f, &I2C->fdr); |
||||
|
||||
/* set default filter */ |
||||
writeb(0x10,&I2C->dfsrr); |
||||
|
||||
/* write slave address */ |
||||
writeb(slaveadd, &I2C->adr); |
||||
|
||||
/* clear status register */ |
||||
writeb(0x00, &I2C->sr); |
||||
|
||||
/* start I2C controller */ |
||||
writeb(I2C_CR_MEN, &I2C->cr); |
||||
} |
||||
|
||||
static __inline__ int |
||||
i2c_wait4bus (void) |
||||
{ |
||||
ulong timeval = get_timer (0); |
||||
while (readb(&I2C->sr) & I2C_SR_MBB) { |
||||
if (get_timer (timeval) > I2C_TIMEOUT) { |
||||
return -1; |
||||
} |
||||
} |
||||
return 0; |
||||
} |
||||
|
||||
static __inline__ int |
||||
i2c_wait (int write) |
||||
{ |
||||
u32 csr; |
||||
ulong timeval = get_timer(0); |
||||
do { |
||||
csr = readb(&I2C->sr); |
||||
|
||||
if (!(csr & I2C_SR_MIF)) |
||||
continue; |
||||
|
||||
writeb(0x0, &I2C->sr); |
||||
|
||||
if (csr & I2C_SR_MAL) { |
||||
debug("i2c_wait: MAL\n"); |
||||
return -1; |
||||
} |
||||
|
||||
if (!(csr & I2C_SR_MCF)) { |
||||
debug("i2c_wait: unfinished\n"); |
||||
return -1; |
||||
} |
||||
|
||||
if (write == I2C_WRITE && (csr & I2C_SR_RXAK)) { |
||||
debug("i2c_wait: No RXACK\n"); |
||||
return -1; |
||||
} |
||||
|
||||
return 0; |
||||
} while (get_timer (timeval) < I2C_TIMEOUT); |
||||
debug("i2c_wait: timed out\n"); |
||||
} |
||||
|
||||
static __inline__ int |
||||
i2c_write_addr (u8 dev, u8 dir, int rsta) |
||||
{ |
||||
writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX | |
||||
(rsta?I2C_CR_RSTA:0), |
||||
&I2C->cr); |
||||
|
||||
writeb((dev << 1) | dir, &I2C->dr); |
||||
|
||||
if (i2c_wait (I2C_WRITE) < 0) |
||||
return 0; |
||||
return 1; |
||||
} |
||||
|
||||
static __inline__ int |
||||
__i2c_write (u8 *data, int length) |
||||
{ |
||||
int i; |
||||
|
||||
writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX, |
||||
&I2C->cr); |
||||
|
||||
for (i=0; i < length; i++) { |
||||
writeb(data[i], &I2C->dr); |
||||
|
||||
if (i2c_wait (I2C_WRITE) < 0) |
||||
break; |
||||
} |
||||
return i; |
||||
} |
||||
|
||||
static __inline__ int |
||||
__i2c_read (u8 *data, int length) |
||||
{ |
||||
int i; |
||||
|
||||
writeb(I2C_CR_MEN | I2C_CR_MSTA | |
||||
((length == 1) ? I2C_CR_TXAK : 0), |
||||
&I2C->cr); |
||||
|
||||
/* dummy read */ |
||||
readb(&I2C->dr); |
||||
|
||||
for (i=0; i < length; i++) { |
||||
if (i2c_wait (I2C_READ) < 0) |
||||
break; |
||||
|
||||
/* Generate ack on last next to last byte */ |
||||
if (i == length - 2) |
||||
writeb(I2C_CR_MEN | I2C_CR_MSTA | |
||||
I2C_CR_TXAK, |
||||
&I2C->cr); |
||||
|
||||
/* Generate stop on last byte */ |
||||
if (i == length - 1) |
||||
writeb(I2C_CR_MEN | I2C_CR_TXAK, &I2C->cr); |
||||
|
||||
data[i] = readb(&I2C->dr); |
||||
} |
||||
return i; |
||||
} |
||||
|
||||
int |
||||
i2c_read (u8 dev, uint addr, int alen, u8 *data, int length) |
||||
{ |
||||
int i = 0; |
||||
u8 *a = (u8*)&addr; |
||||
|
||||
if (i2c_wait4bus () < 0) |
||||
goto exit; |
||||
|
||||
if (i2c_write_addr (dev, I2C_WRITE, 0) == 0) |
||||
goto exit; |
||||
|
||||
if (__i2c_write (&a[4 - alen], alen) != alen) |
||||
goto exit; |
||||
|
||||
if (i2c_write_addr (dev, I2C_READ, 1) == 0) |
||||
goto exit; |
||||
|
||||
i = __i2c_read (data, length); |
||||
|
||||
exit: |
||||
writeb(I2C_CR_MEN, &I2C->cr); |
||||
return !(i == length); |
||||
} |
||||
|
||||
int |
||||
i2c_write (u8 dev, uint addr, int alen, u8 *data, int length) |
||||
{ |
||||
int i = 0; |
||||
u8 *a = (u8*)&addr; |
||||
|
||||
if (i2c_wait4bus () < 0) |
||||
goto exit; |
||||
|
||||
if (i2c_write_addr (dev, I2C_WRITE, 0) == 0) |
||||
goto exit; |
||||
|
||||
if (__i2c_write (&a[4 - alen], alen) != alen) |
||||
goto exit; |
||||
|
||||
i = __i2c_write (data, length); |
||||
|
||||
exit: |
||||
writeb(I2C_CR_MEN, &I2C->cr); |
||||
return !(i == length); |
||||
} |
||||
|
||||
int i2c_probe (uchar chip) |
||||
{ |
||||
int tmp; |
||||
|
||||
/*
|
||||
* Try to read the first location of the chip. The underlying |
||||
* driver doesn't appear to support sending just the chip address |
||||
* and looking for an <ACK> back. |
||||
*/ |
||||
udelay(10000); |
||||
return i2c_read (chip, 0, 1, (char *)&tmp, 1); |
||||
} |
||||
|
||||
uchar i2c_reg_read (uchar i2c_addr, uchar reg) |
||||
{ |
||||
char buf[1]; |
||||
|
||||
i2c_read (i2c_addr, reg, 1, buf, 1); |
||||
|
||||
return (buf[0]); |
||||
} |
||||
|
||||
void i2c_reg_write (uchar i2c_addr, uchar reg, uchar val) |
||||
{ |
||||
i2c_write (i2c_addr, reg, 1, &val, 1); |
||||
} |
||||
|
||||
#endif /* CONFIG_HARD_I2C */ |
||||
@ -0,0 +1,94 @@ |
||||
/*
|
||||
* (C) Copyright 2000-2002 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* Copyright 2004 Freescale Semiconductor, Inc. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
* |
||||
* Change log: |
||||
* |
||||
* Hacked for MPC8260 by Murray.Jensen@cmst.csiro.au, 22-Oct-00 |
||||
* |
||||
* 20050101: Eran Liberty (liberty@freescale.com) |
||||
* Initial file creating (porting from 85XX & 8260) |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <command.h> |
||||
#include <mpc83xx.h> |
||||
#include <asm/processor.h> |
||||
|
||||
struct irq_action { |
||||
interrupt_handler_t *handler; |
||||
void *arg; |
||||
ulong count; |
||||
}; |
||||
|
||||
int interrupt_init_cpu (unsigned *decrementer_count) |
||||
{ |
||||
return 0; |
||||
} |
||||
|
||||
|
||||
/*
|
||||
* Handle external interrupts |
||||
*/ |
||||
|
||||
void external_interrupt (struct pt_regs *regs) |
||||
{ |
||||
} |
||||
|
||||
|
||||
/*
|
||||
* Install and free an interrupt handler. |
||||
*/ |
||||
|
||||
void |
||||
irq_install_handler (int irq, interrupt_handler_t * handler, void *arg) |
||||
{ |
||||
} |
||||
|
||||
|
||||
void irq_free_handler (int irq) |
||||
{ |
||||
} |
||||
|
||||
|
||||
void timer_interrupt_cpu (struct pt_regs *regs) |
||||
{ |
||||
/* nothing to do here */ |
||||
return; |
||||
} |
||||
|
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_IRQ) |
||||
|
||||
/* ripped this out of ppc4xx/interrupts.c */ |
||||
|
||||
/*
|
||||
* irqinfo - print information about PCI devices |
||||
*/ |
||||
|
||||
void |
||||
do_irqinfo(cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) |
||||
{ |
||||
} |
||||
|
||||
#endif /* CONFIG_COMMANDS & CFG_CMD_IRQ */ |
||||
@ -0,0 +1,253 @@ |
||||
/*
|
||||
* Copyright 2004 Freescale Semiconductor. |
||||
* Copyright (C) 2003 Motorola Inc. |
||||
* Xianghua Xiao (x.xiao@motorola.com) |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
* |
||||
* Change log: |
||||
* |
||||
* 20050101: Eran Liberty (liberty@freescale.com) |
||||
* Initial file creating (porting from 85XX & 8260) |
||||
*/ |
||||
|
||||
/*
|
||||
* PCI Configuration space access support for MPC85xx PCI Bridge |
||||
*/ |
||||
#include <asm/mmu.h> |
||||
#include <asm/io.h> |
||||
#include <common.h> |
||||
#include <pci.h> |
||||
|
||||
#ifdef CONFIG_MPC8349ADS |
||||
#include <asm/i2c.h> |
||||
#endif |
||||
|
||||
#if defined(CONFIG_PCI) |
||||
|
||||
void |
||||
pci_mpc83xx_init(volatile struct pci_controller *hose) |
||||
{ |
||||
volatile immap_t * immr; |
||||
volatile clk8349_t * clk;
|
||||
volatile law8349_t * pci_law; |
||||
volatile pot8349_t * pci_pot; |
||||
volatile pcictrl8349_t * pci_ctrl; |
||||
volatile pciconf8349_t * pci_conf; |
||||
|
||||
u8 val8,tmp8,ret; |
||||
u16 reg16,tmp16; |
||||
u32 val32,tmp32; |
||||
|
||||
immr = (immap_t *)CFG_IMMRBAR; |
||||
clk = (clk8349_t *)&immr->clk; |
||||
pci_law = immr->sysconf.pcilaw; |
||||
pci_pot = immr->ios.pot; |
||||
pci_ctrl = immr->pci_ctrl; |
||||
pci_conf = immr->pci_conf; |
||||
|
||||
/*
|
||||
* Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode |
||||
*/ |
||||
val32 = clk->occr; |
||||
udelay(2000); |
||||
clk->occr = 0xff000000; |
||||
udelay(2000); |
||||
|
||||
/*
|
||||
* Configure PCI Local Access Windows |
||||
*/ |
||||
pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR; |
||||
pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G; |
||||
pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR; |
||||
pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_32M; |
||||
|
||||
/*
|
||||
* Configure PCI Outbound Translation Windows |
||||
*/ |
||||
pci_pot[0].potar = (CFG_PCI1_MEM_BASE >> 12) & POTAR_TA_MASK; |
||||
pci_pot[0].pobar = (CFG_PCI1_MEM_PHYS >> 12) & POBAR_BA_MASK; |
||||
pci_pot[0].pocmr = POCMR_EN | (POCMR_CM_512M & POCMR_CM_MASK); |
||||
|
||||
/* mapped to PCI1 IO space 0x0 to local 0xe2000000 */ |
||||
pci_pot[1].potar = (CFG_PCI1_IO_BASE >> 12) & POTAR_TA_MASK; |
||||
pci_pot[1].pobar = (CFG_PCI1_IO_PHYS >> 12) & POBAR_BA_MASK; |
||||
pci_pot[1].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_16M & POCMR_CM_MASK); |
||||
//#if defined(CONFIG_PCI_2)
|
||||
pci_pot[3].potar = (CFG_PCI2_MEM_BASE >> 12) & POTAR_TA_MASK; |
||||
pci_pot[3].pobar = (CFG_PCI2_MEM_PHYS >> 12) & POBAR_BA_MASK; |
||||
pci_pot[3].pocmr = POCMR_EN | POCMR_DST | (POCMR_CM_512M & POCMR_CM_MASK); |
||||
|
||||
/* mapped to PCI2 IO space 0x0 to local 0xe3000000 */ |
||||
pci_pot[4].potar = (CFG_PCI2_IO_BASE >> 12) & POTAR_TA_MASK; |
||||
pci_pot[4].pobar = (CFG_PCI2_IO_PHYS >> 12) & POBAR_BA_MASK; |
||||
pci_pot[4].pocmr = POCMR_EN | POCMR_DST | POCMR_IO | (POCMR_CM_16M & POCMR_CM_MASK); |
||||
//#endif
|
||||
|
||||
/*
|
||||
* Configure PCI Inbound Translation Windows |
||||
*/ |
||||
pci_ctrl[0].pitar1 = 0x0; |
||||
pci_ctrl[0].pibar1 = 0x0; |
||||
pci_ctrl[0].piebar1 = 0x0; |
||||
pci_ctrl[0].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | PIWAR_IWS_2G; |
||||
|
||||
pci_ctrl[1].pitar1 = 0x0; |
||||
pci_ctrl[1].pibar1 = 0x0; |
||||
pci_ctrl[1].piebar1 = 0x0; |
||||
pci_ctrl[1].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | PIWAR_IWS_2G; |
||||
/*
|
||||
* Assign PIB PMC slot to desired PCI bus |
||||
*/ |
||||
#ifdef CONFIG_MPC8349ADS |
||||
mpc8349_i2c = (i2c_t*)(CFG_IMMRBAR + CFG_I2C2_OFFSET); |
||||
i2c_init(CFG_I2C_SPEED,CFG_I2C_SLAVE); |
||||
#endif |
||||
val8 = 0; |
||||
ret = i2c_write(0x23,0x6,1,&val8,1); |
||||
ret = i2c_write(0x23,0x7,1,&val8,1); |
||||
val8 = 0xff; |
||||
ret = i2c_write(0x23,0x2,1,&val8,1); |
||||
ret = i2c_write(0x23,0x3,1,&val8,1); |
||||
|
||||
val8 = 0; |
||||
ret = i2c_write(0x26,0x6,1,&val8,1); |
||||
val8 = 0x34; |
||||
ret = i2c_write(0x26,0x7,1,&val8,1); |
||||
#if defined(PCI_64BIT) |
||||
val8 = 0xf4; // PMC2<->PCI1 64bit
|
||||
#elif defined(PCI_ALL_PCI1) |
||||
val8 = 0xf3; // PMC1<->PCI1,PMC2<->PCI1,PMC3<->PCI1 32bit
|
||||
#elif defined(PCI_ONE_PCI1) |
||||
val8 = 0xf9; // PMC1<->PCI1,PMC2<->PCI2,PMC3<->PCI2 32bit
|
||||
#elif defined(PCI_TWO_PCI1) |
||||
val8 = 0xf5; // PMC1<->PCI1,PMC2<->PCI1,PMC3<->PCI2 32bit
|
||||
#else |
||||
val8 = 0xf5; |
||||
#endif |
||||
ret = i2c_write(0x26,0x2,1,&val8,1); |
||||
val8 = 0xff; |
||||
ret = i2c_write(0x26,0x3,1,&val8,1); |
||||
val8 = 0; |
||||
ret = i2c_write(0x27,0x6,1,&val8,1); |
||||
ret = i2c_write(0x27,0x7,1,&val8,1); |
||||
val8 = 0xff; |
||||
ret = i2c_write(0x27,0x2,1,&val8,1); |
||||
val8 = 0xef; |
||||
ret = i2c_write(0x27,0x3,1,&val8,1); |
||||
asm("eieio"); |
||||
|
||||
/*
|
||||
* Release PCI RST Output signal |
||||
*/ |
||||
udelay(2000); |
||||
pci_ctrl[0].gcr = 1; |
||||
#ifndef PCI_64BIT |
||||
pci_ctrl[1].gcr = 1; |
||||
#endif |
||||
udelay(2000); |
||||
|
||||
hose[0].first_busno = 0; |
||||
hose[0].last_busno = 0xff; |
||||
|
||||
pci_set_region(hose[0].regions + 0, |
||||
CFG_PCI1_MEM_BASE, |
||||
CFG_PCI1_MEM_PHYS, |
||||
CFG_PCI1_MEM_SIZE, |
||||
PCI_REGION_MEM); |
||||
|
||||
pci_set_region(hose[0].regions + 1, |
||||
CFG_PCI1_IO_BASE, |
||||
CFG_PCI1_IO_PHYS, |
||||
CFG_PCI1_IO_SIZE, |
||||
PCI_REGION_IO); |
||||
|
||||
hose[0].region_count = 2; |
||||
|
||||
pci_setup_indirect(&hose[0], |
||||
(CFG_IMMRBAR+0x8300), |
||||
(CFG_IMMRBAR+0x8304)); |
||||
#define PCI_CLASS_BRIDGE 0x06 |
||||
reg16 = 0xff; |
||||
tmp32 = 0xffff; |
||||
pci_hose_write_config_byte(&hose[0],PCI_BDF(0,0,0),PCI_CLASS_CODE,PCI_CLASS_BRIDGE);
|
||||
|
||||
pci_hose_read_config_word (&hose[0],PCI_BDF(0,0,0),PCI_COMMAND, ®16); |
||||
reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; |
||||
pci_hose_write_config_word(&hose[0],PCI_BDF(0,0,0), PCI_COMMAND, reg16); |
||||
|
||||
/*
|
||||
* Clear non-reserved bits in status register. |
||||
*/ |
||||
pci_hose_write_config_word(&hose[0],PCI_BDF(0,0,0), PCI_STATUS, 0xffff); |
||||
pci_hose_write_config_byte(&hose[0],PCI_BDF(0,0,0), PCI_LATENCY_TIMER,0x80); |
||||
#ifndef PCI_64BIT |
||||
hose[1].first_busno = 0; |
||||
hose[1].last_busno = 0xff; |
||||
|
||||
pci_set_region(hose[1].regions + 0, |
||||
CFG_PCI2_MEM_BASE, |
||||
CFG_PCI2_MEM_PHYS, |
||||
CFG_PCI2_MEM_SIZE, |
||||
PCI_REGION_MEM); |
||||
|
||||
pci_set_region(hose[1].regions + 1, |
||||
CFG_PCI2_IO_BASE, |
||||
CFG_PCI2_IO_PHYS, |
||||
CFG_PCI2_IO_SIZE, |
||||
PCI_REGION_IO); |
||||
|
||||
hose[1].region_count = 2; |
||||
|
||||
pci_setup_indirect(&hose[1], |
||||
(CFG_IMMRBAR+0x8380), |
||||
(CFG_IMMRBAR+0x8384)); |
||||
|
||||
pci_hose_write_config_byte(&hose[1],PCI_BDF(0,0,0),PCI_CLASS_CODE,PCI_CLASS_BRIDGE);
|
||||
pci_hose_read_config_word (&hose[1],PCI_BDF(0,0,0), PCI_COMMAND, ®16); |
||||
reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; |
||||
pci_hose_write_config_word(&hose[1],PCI_BDF(0,0,0), PCI_COMMAND, reg16); |
||||
|
||||
/*
|
||||
* Clear non-reserved bits in status register. |
||||
*/ |
||||
pci_hose_write_config_word(&hose[1],PCI_BDF(0,0,0), PCI_STATUS, 0xffff); |
||||
pci_hose_write_config_byte(&hose[1],PCI_BDF(0,0,0), PCI_LATENCY_TIMER,0x80); |
||||
#endif |
||||
|
||||
#if defined(PCI_64BIT) |
||||
printf("PCI1 64bit on PMC2\n"); |
||||
#elif defined(PCI_ALL_PCI1) |
||||
printf("PCI1 32bit on PMC1 & PMC2 & PMC3\n"); |
||||
#elif defined(PCI_ONE_PCI1) |
||||
printf("PCI1 32bit on PMC1,PCI2 32bit on PMC2 & PMC3\n"); |
||||
#else |
||||
printf("PCI1 32bit on PMC1 & PMC2 & PMC3 in default\n"); |
||||
#endif |
||||
|
||||
#if 1 |
||||
/*
|
||||
* Hose scan. |
||||
*/ |
||||
pci_register_hose(hose); |
||||
hose->last_busno = pci_hose_scan(hose); |
||||
#endif |
||||
} |
||||
|
||||
#endif /* CONFIG_PCI */ |
||||
@ -0,0 +1,6 @@ |
||||
.section .resetvec,"ax" |
||||
#ifndef FIXME |
||||
#if 0 |
||||
b _start_e500 |
||||
#endif
|
||||
#endif |
||||
@ -0,0 +1,413 @@ |
||||
/*
|
||||
* Copyright 2004 Freescale Semiconductor. |
||||
* (C) Copyright 2003 Motorola Inc. |
||||
* Xianghua Xiao (X.Xiao@motorola.com) |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
* |
||||
* Change log: |
||||
* |
||||
* 20050101: Eran Liberty (liberty@freescale.com) |
||||
* Initial file creating (porting from 85XX & 8260) |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <asm/processor.h> |
||||
#include <i2c.h> |
||||
#include <spd.h> |
||||
#include <asm/mmu.h> |
||||
#include <spd_sdram.h> |
||||
|
||||
#ifdef CONFIG_SPD_EEPROM |
||||
|
||||
|
||||
#if defined(CONFIG_DDR_ECC) |
||||
extern void dma_init(void); |
||||
extern uint dma_check(void); |
||||
extern int dma_xfer(void *dest, uint count, void *src); |
||||
#endif |
||||
|
||||
|
||||
#ifndef CFG_READ_SPD |
||||
#define CFG_READ_SPD i2c_read |
||||
#endif |
||||
|
||||
|
||||
|
||||
/*
|
||||
* Convert picoseconds into clock cycles (rounding up if needed). |
||||
*/ |
||||
|
||||
int |
||||
picos_to_clk(int picos) |
||||
{ |
||||
int clks; |
||||
|
||||
clks = picos / (2000000000 / (get_bus_freq(0) / 1000)); |
||||
if (picos % (2000000000 / (get_bus_freq(0) / 1000)) != 0) { |
||||
clks++; |
||||
} |
||||
|
||||
return clks; |
||||
} |
||||
|
||||
|
||||
unsigned int |
||||
banksize(unsigned char row_dens) |
||||
{ |
||||
return ((row_dens >> 2) | ((row_dens & 3) << 6)) << 24; |
||||
} |
||||
|
||||
|
||||
long int spd_sdram(int(read_spd)(uint addr)) |
||||
{ |
||||
volatile immap_t *immap = (immap_t *)CFG_IMMRBAR; |
||||
volatile ddr8349_t *ddr = &immap->ddr; |
||||
volatile law8349_t *ecm = &immap->sysconf.ddrlaw[0]; |
||||
spd_eeprom_t spd; |
||||
unsigned tmp, tmp1; |
||||
unsigned int memsize; |
||||
unsigned int law_size; |
||||
unsigned char caslat; |
||||
unsigned int trfc, trfc_clk, trfc_low; |
||||
|
||||
#warning Current spd_sdram does not fit its usage... adjust implementation or API... |
||||
|
||||
CFG_READ_SPD(SPD_EEPROM_ADDRESS, 0, 1, (uchar *) & spd, sizeof (spd)); |
||||
|
||||
if (spd.nrows > 2) { |
||||
puts("DDR:Only two chip selects are supported on ADS.\n"); |
||||
return 0; |
||||
} |
||||
|
||||
if (spd.nrow_addr < 12 |
||||
|| spd.nrow_addr > 14 |
||||
|| spd.ncol_addr < 8 |
||||
|| spd.ncol_addr > 11) { |
||||
puts("DDR:Row or Col number unsupported.\n"); |
||||
return 0; |
||||
} |
||||
|
||||
ddr->csbnds[2].csbnds = (banksize(spd.row_dens) >> 24) - 1; |
||||
ddr->cs_config[2] = ( 1 << 31 |
||||
| (spd.nrow_addr - 12) << 8 |
||||
| (spd.ncol_addr - 8) ); |
||||
debug("\n"); |
||||
debug("cs2_bnds = 0x%08x\n",ddr->csbnds[2].csbnds); |
||||
debug("cs2_config = 0x%08x\n",ddr->cs_config[2]); |
||||
|
||||
if (spd.nrows == 2) { |
||||
ddr->csbnds[3].csbnds = ( (banksize(spd.row_dens) >> 8) |
||||
| ((banksize(spd.row_dens) >> 23) - 1) ); |
||||
ddr->cs_config[3] = ( 1<<31 |
||||
| (spd.nrow_addr-12) << 8 |
||||
| (spd.ncol_addr-8) ); |
||||
debug("cs3_bnds = 0x%08x\n",ddr->csbnds[3].csbnds); |
||||
debug("cs3_config = 0x%08x\n",ddr->cs_config[3]); |
||||
} |
||||
|
||||
if (spd.mem_type != 0x07) { |
||||
puts("No DDR module found!\n"); |
||||
return 0; |
||||
} |
||||
|
||||
/*
|
||||
* Figure out memory size in Megabytes. |
||||
*/ |
||||
memsize = spd.nrows * banksize(spd.row_dens) / 0x100000; |
||||
|
||||
/*
|
||||
* First supported LAW size is 16M, at LAWAR_SIZE_16M == 23. |
||||
*/ |
||||
law_size = 19 + __ilog2(memsize); |
||||
|
||||
/*
|
||||
* Set up LAWBAR for all of DDR. |
||||
*/ |
||||
ecm->bar = ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff); |
||||
ecm->ar = (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & law_size)); |
||||
debug("DDR:bar=0x%08x\n", ecm->bar); |
||||
debug("DDR:ar=0x%08x\n", ecm->ar); |
||||
|
||||
/*
|
||||
* find the largest CAS |
||||
*/ |
||||
if(spd.cas_lat & 0x40) { |
||||
caslat = 7; |
||||
} else if (spd.cas_lat & 0x20) { |
||||
caslat = 6; |
||||
} else if (spd.cas_lat & 0x10) { |
||||
caslat = 5; |
||||
} else if (spd.cas_lat & 0x08) { |
||||
caslat = 4; |
||||
} else if (spd.cas_lat & 0x04) { |
||||
caslat = 3; |
||||
} else if (spd.cas_lat & 0x02) { |
||||
caslat = 2; |
||||
} else if (spd.cas_lat & 0x01) { |
||||
caslat = 1; |
||||
} else { |
||||
puts("DDR:no valid CAS Latency information.\n"); |
||||
return 0; |
||||
} |
||||
|
||||
tmp = 20000 / (((spd.clk_cycle & 0xF0) >> 4) * 10 |
||||
+ (spd.clk_cycle & 0x0f)); |
||||
debug("DDR:Module maximum data rate is: %dMhz\n", tmp); |
||||
|
||||
tmp1 = get_bus_freq(0) / 1000000; |
||||
if (tmp1 < 230 && tmp1 >= 90 && tmp >= 230) { |
||||
/* 90~230 range, treated as DDR 200 */ |
||||
if (spd.clk_cycle3 == 0xa0) |
||||
caslat -= 2; |
||||
else if(spd.clk_cycle2 == 0xa0) |
||||
caslat--; |
||||
} else if (tmp1 < 280 && tmp1 >= 230 && tmp >= 280) { |
||||
/* 230-280 range, treated as DDR 266 */ |
||||
if (spd.clk_cycle3 == 0x75) |
||||
caslat -= 2; |
||||
else if (spd.clk_cycle2 == 0x75) |
||||
caslat--; |
||||
} else if (tmp1 < 350 && tmp1 >= 280 && tmp >= 350) { |
||||
/* 280~350 range, treated as DDR 333 */ |
||||
if (spd.clk_cycle3 == 0x60) |
||||
caslat -= 2; |
||||
else if (spd.clk_cycle2 == 0x60) |
||||
caslat--; |
||||
} else if (tmp1 < 90 || tmp1 >= 350) { |
||||
/* DDR rate out-of-range */ |
||||
puts("DDR:platform frequency is not fit for DDR rate\n"); |
||||
return 0; |
||||
} |
||||
|
||||
/*
|
||||
* note: caslat must also be programmed into ddr->sdram_mode |
||||
* register. |
||||
* |
||||
* note: WRREC(Twr) and WRTORD(Twtr) are not in SPD, |
||||
* use conservative value here. |
||||
*/ |
||||
trfc = spd.trfc * 1000; /* up to ps */ |
||||
trfc_clk = picos_to_clk(trfc); |
||||
trfc_low = (trfc_clk - 8) & 0xf; |
||||
|
||||
ddr->timing_cfg_1 = |
||||
(((picos_to_clk(spd.trp * 250) & 0x07) << 28 ) | |
||||
((picos_to_clk(spd.tras * 1000) & 0x0f ) << 24 ) | |
||||
((picos_to_clk(spd.trcd * 250) & 0x07) << 20 ) | |
||||
((caslat & 0x07) << 16 ) | |
||||
(trfc_low << 12 ) | |
||||
( 0x300 ) | |
||||
((picos_to_clk(spd.trrd * 250) & 0x07) << 4) | 1); |
||||
|
||||
ddr->timing_cfg_2 = 0x00000800; |
||||
|
||||
debug("DDR:timing_cfg_1=0x%08x\n", ddr->timing_cfg_1); |
||||
debug("DDR:timing_cfg_2=0x%08x\n", ddr->timing_cfg_2); |
||||
|
||||
/*
|
||||
* Only DDR I is supported |
||||
* DDR I and II have different mode-register-set definition |
||||
*/ |
||||
|
||||
/* burst length is always 4 */ |
||||
switch(caslat) { |
||||
case 2: |
||||
ddr->sdram_mode = 0x52; /* 1.5 */ |
||||
break; |
||||
case 3: |
||||
ddr->sdram_mode = 0x22; /* 2.0 */ |
||||
break; |
||||
case 4: |
||||
ddr->sdram_mode = 0x62; /* 2.5 */ |
||||
break; |
||||
case 5: |
||||
ddr->sdram_mode = 0x32; /* 3.0 */ |
||||
break; |
||||
default: |
||||
puts("DDR:only CAS Latency 1.5, 2.0, 2.5, 3.0 is supported.\n"); |
||||
return 0; |
||||
} |
||||
debug("DDR:sdram_mode=0x%08x\n", ddr->sdram_mode); |
||||
|
||||
switch(spd.refresh) { |
||||
case 0x00: |
||||
case 0x80: |
||||
tmp = picos_to_clk(15625000); |
||||
break; |
||||
case 0x01: |
||||
case 0x81: |
||||
tmp = picos_to_clk(3900000); |
||||
break; |
||||
case 0x02: |
||||
case 0x82: |
||||
tmp = picos_to_clk(7800000); |
||||
break; |
||||
case 0x03: |
||||
case 0x83: |
||||
tmp = picos_to_clk(31300000); |
||||
break; |
||||
case 0x04: |
||||
case 0x84: |
||||
tmp = picos_to_clk(62500000); |
||||
break; |
||||
case 0x05: |
||||
case 0x85: |
||||
tmp = picos_to_clk(125000000); |
||||
break; |
||||
default: |
||||
tmp = 0x512; |
||||
break; |
||||
} |
||||
|
||||
/*
|
||||
* Set BSTOPRE to 0x100 for page mode |
||||
* If auto-charge is used, set BSTOPRE = 0 |
||||
*/ |
||||
ddr->sdram_interval = ((tmp & 0x3fff) << 16) | 0x100; |
||||
debug("DDR:sdram_interval=0x%08x\n", ddr->sdram_interval); |
||||
|
||||
/*
|
||||
* Is this an ECC DDR chip? |
||||
*/ |
||||
#if defined(CONFIG_DDR_ECC) |
||||
if (spd.config == 0x02) { |
||||
ddr->err_disable = 0x0000000d; |
||||
ddr->err_sbe = 0x00ff0000; |
||||
} |
||||
debug("DDR:err_disable=0x%08x\n", ddr->err_disable); |
||||
debug("DDR:err_sbe=0x%08x\n", ddr->err_sbe); |
||||
#endif |
||||
asm("sync;isync"); |
||||
|
||||
udelay(500); |
||||
|
||||
|
||||
ddr->sdram_clk_cntl = 0x82000000;/*SS_EN=1, CLK_ADJST = 2-MCK/MCK_B, is lauched 1/2 of one SDRAM clock cycle after address/command*/ |
||||
|
||||
|
||||
/*
|
||||
* Figure out the settings for the sdram_cfg register. Build up |
||||
* the entire register in 'tmp' before writing since the write into |
||||
* the register will actually enable the memory controller, and all |
||||
* settings must be done before enabling. |
||||
* |
||||
* sdram_cfg[0] = 1 (ddr sdram logic enable) |
||||
* sdram_cfg[1] = 1 (self-refresh-enable) |
||||
* sdram_cfg[6:7] = 2 (SDRAM type = DDR SDRAM) |
||||
*/ |
||||
tmp = 0xc2000000; |
||||
|
||||
/*
|
||||
* sdram_cfg[3] = RD_EN - registered DIMM enable |
||||
* A value of 0x26 indicates micron registered DIMMS (micron.com) |
||||
*/ |
||||
if (spd.mod_attr == 0x26) { |
||||
tmp |= 0x10000000; |
||||
} |
||||
|
||||
#if defined(CONFIG_DDR_ECC) |
||||
/*
|
||||
* If the user wanted ECC (enabled via sdram_cfg[2]) |
||||
*/ |
||||
if (spd.config == 0x02) { |
||||
tmp |= 0x20000000; |
||||
} |
||||
#endif |
||||
|
||||
#if defined(CONFIG_DDR_2T_TIMING) |
||||
/*
|
||||
* Enable 2T timing by setting sdram_cfg[16]. |
||||
*/ |
||||
tmp |= SDRAM_CFG_2T_EN; |
||||
#endif |
||||
|
||||
ddr->sdram_cfg = tmp; |
||||
|
||||
asm("sync;isync"); |
||||
udelay(500); |
||||
|
||||
debug("DDR:sdram_cfg=0x%08x\n", ddr->sdram_cfg); |
||||
|
||||
return memsize;/*in MBytes*/ |
||||
} |
||||
|
||||
#endif /* CONFIG_SPD_EEPROM */ |
||||
|
||||
|
||||
#if defined(CONFIG_DDR_ECC) |
||||
/*
|
||||
* Initialize all of memory for ECC, then enable errors. |
||||
*/ |
||||
|
||||
void |
||||
ddr_enable_ecc(unsigned int dram_size) |
||||
{ |
||||
#ifndef FIXME |
||||
uint *p = 0; |
||||
uint i = 0; |
||||
volatile immap_t *immap = (immap_t *)CFG_IMMRBAR; |
||||
volatile ccsr_ddr_t *ddr= &immap->im_ddr; |
||||
|
||||
dma_init(); |
||||
|
||||
for (*p = 0; p < (uint *)(8 * 1024); p++) { |
||||
if (((unsigned int)p & 0x1f) == 0) { |
||||
ppcDcbz((unsigned long) p); |
||||
} |
||||
*p = (unsigned int)0xdeadbeef; |
||||
if (((unsigned int)p & 0x1c) == 0x1c) { |
||||
ppcDcbf((unsigned long) p); |
||||
} |
||||
} |
||||
|
||||
/* 8K */ |
||||
dma_xfer((uint *)0x2000, 0x2000, (uint *)0); |
||||
/* 16K */ |
||||
dma_xfer((uint *)0x4000, 0x4000, (uint *)0); |
||||
/* 32K */ |
||||
dma_xfer((uint *)0x8000, 0x8000, (uint *)0); |
||||
/* 64K */ |
||||
dma_xfer((uint *)0x10000, 0x10000, (uint *)0); |
||||
/* 128k */ |
||||
dma_xfer((uint *)0x20000, 0x20000, (uint *)0); |
||||
/* 256k */ |
||||
dma_xfer((uint *)0x40000, 0x40000, (uint *)0); |
||||
/* 512k */ |
||||
dma_xfer((uint *)0x80000, 0x80000, (uint *)0); |
||||
/* 1M */ |
||||
dma_xfer((uint *)0x100000, 0x100000, (uint *)0); |
||||
/* 2M */ |
||||
dma_xfer((uint *)0x200000, 0x200000, (uint *)0); |
||||
/* 4M */ |
||||
dma_xfer((uint *)0x400000, 0x400000, (uint *)0); |
||||
|
||||
for (i = 1; i < dram_size / 0x800000; i++) { |
||||
dma_xfer((uint *)(0x800000*i), 0x800000, (uint *)0); |
||||
} |
||||
|
||||
/*
|
||||
* Enable errors for ECC. |
||||
*/ |
||||
ddr->err_disable = 0x00000000; |
||||
asm("sync;isync"); |
||||
#endif |
||||
} |
||||
|
||||
#endif /* CONFIG_DDR_ECC */ |
||||
@ -0,0 +1,424 @@ |
||||
/*
|
||||
* (C) Copyright 2000-2002 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* Copyright 2004 Freescale Semiconductor, Inc. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
* |
||||
* Change log: |
||||
* |
||||
* 20050101: Eran Liberty (liberty@freescale.com) |
||||
* Initial file creating (porting from 85XX & 8260) |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <mpc83xx.h> |
||||
#include <asm/processor.h> |
||||
|
||||
/* ----------------------------------------------------------------- */ |
||||
|
||||
typedef enum { |
||||
_unk, |
||||
_off, |
||||
_byp, |
||||
_x8, |
||||
_x4, |
||||
_x2, |
||||
_x1, |
||||
_1x, |
||||
_1_5x, |
||||
_2x, |
||||
_2_5x, |
||||
_3x |
||||
} mult_t; |
||||
|
||||
typedef struct { |
||||
mult_t core_csb_ratio; |
||||
mult_t vco_divider; |
||||
} corecnf_t; |
||||
|
||||
corecnf_t corecnf_tab[] = { |
||||
{ _byp, _byp}, /* 0x00 */ |
||||
{ _byp, _byp}, /* 0x01 */ |
||||
{ _byp, _byp}, /* 0x02 */ |
||||
{ _byp, _byp}, /* 0x03 */ |
||||
{ _byp, _byp}, /* 0x04 */ |
||||
{ _byp, _byp}, /* 0x05 */ |
||||
{ _byp, _byp}, /* 0x06 */ |
||||
{ _byp, _byp}, /* 0x07 */ |
||||
{ _1x, _x2}, /* 0x08 */ |
||||
{ _1x, _x4}, /* 0x09 */ |
||||
{ _1x, _x8}, /* 0x0A */ |
||||
{ _1x, _x8}, /* 0x0B */ |
||||
{_1_5x, _x2}, /* 0x0C */ |
||||
{_1_5x, _x4}, /* 0x0D */ |
||||
{_1_5x, _x8}, /* 0x0E */ |
||||
{_1_5x, _x8}, /* 0x0F */ |
||||
{ _2x, _x2}, /* 0x10 */ |
||||
{ _2x, _x4}, /* 0x11 */ |
||||
{ _2x, _x8}, /* 0x12 */ |
||||
{ _2x, _x8}, /* 0x13 */ |
||||
{_2_5x, _x2}, /* 0x14 */ |
||||
{_2_5x, _x4}, /* 0x15 */ |
||||
{_2_5x, _x8}, /* 0x16 */ |
||||
{_2_5x, _x8}, /* 0x17 */ |
||||
{ _3x, _x2}, /* 0x18 */ |
||||
{ _3x, _x4}, /* 0x19 */ |
||||
{ _3x, _x8}, /* 0x1A */ |
||||
{ _3x, _x8}, /* 0x1B */ |
||||
}; |
||||
|
||||
/* ----------------------------------------------------------------- */ |
||||
|
||||
/*
|
||||
* |
||||
*/ |
||||
int get_clocks (void) |
||||
{ |
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
volatile immap_t *im = (immap_t *)CFG_IMMRBAR; |
||||
u32 pci_sync_in; |
||||
u8 spmf; |
||||
u8 clkin_div; |
||||
u32 sccr; |
||||
u32 corecnf_tab_index; |
||||
u8 corepll; |
||||
u32 lcrr; |
||||
|
||||
u32 csb_clk; |
||||
u32 tsec1_clk; |
||||
u32 tsec2_clk; |
||||
u32 core_clk; |
||||
u32 usbmph_clk; |
||||
u32 usbdr_clk; |
||||
u32 i2c_clk; |
||||
u32 enc_clk; |
||||
u32 lbiu_clk; |
||||
u32 lclk_clk; |
||||
u32 ddr_clk; |
||||
|
||||
if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) |
||||
return -1; |
||||
|
||||
#ifndef CFG_HRCW_HIGH |
||||
# error "CFG_HRCW_HIGH must be defined in include/configs/MCP83XXADS.h" |
||||
#endif /* CFG_HCWD_HIGH */ |
||||
|
||||
#if (CFG_HRCW_HIGH & HRCWH_PCI_HOST) |
||||
# ifndef CONFIG_83XX_CLKIN |
||||
# error "In PCI Host Mode, CONFIG_83XX_CLKIN must be defined in include/configs/MCP83XXADS.h" |
||||
# endif /* CONFIG_83XX_CLKIN */ |
||||
# ifdef CONFIG_83XX_PCICLK |
||||
# warning "In PCI Host Mode, CONFIG_83XX_PCICLK in include/configs/MCP83XXADS.h is igonred." |
||||
# endif /* CONFIG_83XX_PCICLK */ |
||||
/* PCI Host Mode */ |
||||
if (!(im->reset.rcwh & RCWH_PCIHOST)) { |
||||
/* though RCWH_PCIHOST is defined in CFG_HRCW_HIGH the im->reset.rcwhr PCI Host Mode is disabled */ |
||||
/* FIXME: findout if there is a way to issue some warning */ |
||||
return -2; |
||||
|
||||
} |
||||
if (im->clk.spmr & SPMR_CKID) { |
||||
pci_sync_in = CONFIG_83XX_CLKIN / 2; /* PCI Clock is half CONFIG_83XX_CLKIN */ |
||||
} |
||||
else { |
||||
pci_sync_in = CONFIG_83XX_CLKIN; |
||||
} |
||||
#else |
||||
# ifdef CONFIG_83XX_CLKIN |
||||
# warning "In PCI Agent Mode, CONFIG_83XX_CLKIN in include/configs/MCP83XXADS.h is igonred." |
||||
# endif /* CONFIG_83XX_CLKIN */ |
||||
# ifndef CONFIG_83XX_PCICLK |
||||
# error "In PCI Agent Mode, CONFIG_83XX_PCICLK must be defined in include/configs/MCP83XXADS.h" |
||||
# endif /* CONFIG_83XX_PCICLK */ |
||||
/* PCI Agent Mode */ |
||||
if (im->reset.rcwh & RCWH_PCIHOST) { |
||||
/* though RCWH_PCIHOST is not defined in CFG_HRCW_HIGH the im->reset.rcwhr PCI Host Mode is enabled */ |
||||
return -3; |
||||
} |
||||
pci_sync_in = CONFIG_83XX_PCICLK; |
||||
#endif /* (CFG_HRCW_HIGH | RCWH_PCIHOST) */ |
||||
|
||||
/* we have up to date pci_sync_in */ |
||||
|
||||
spmf = ((im->reset.rcwl & RCWL_SPMF) >> RCWL_SPMF_SHIFT); |
||||
clkin_div = ((im->clk.spmr & SPMR_CKID) >> SPMR_CKID_SHIFT); |
||||
|
||||
if ((im->reset.rcwl & RCWL_LBIUCM) || (im->reset.rcwl & RCWL_DDRCM)) { |
||||
csb_clk = (pci_sync_in * spmf * (1 + clkin_div)) / 2; |
||||
} |
||||
else { |
||||
csb_clk = pci_sync_in * spmf * (1 + clkin_div); |
||||
} |
||||
|
||||
sccr = im->clk.sccr; |
||||
switch ((sccr & SCCR_TSEC1CM) >> SCCR_TSEC1CM_SHIFT) { |
||||
case 0: |
||||
tsec1_clk = 0; |
||||
break; |
||||
case 1: |
||||
tsec1_clk = csb_clk; |
||||
break; |
||||
case 2: |
||||
tsec1_clk = csb_clk / 2; |
||||
break; |
||||
case 3: |
||||
tsec1_clk = csb_clk / 3; |
||||
break; |
||||
default: |
||||
/* unkown SCCR_TSEC1CM value */ |
||||
return -4; |
||||
} |
||||
|
||||
switch ((sccr & SCCR_TSEC2CM) >> SCCR_TSEC2CM_SHIFT) { |
||||
case 0: |
||||
tsec2_clk = 0; |
||||
break; |
||||
case 1: |
||||
tsec2_clk = csb_clk; |
||||
break; |
||||
case 2: |
||||
tsec2_clk = csb_clk / 2; |
||||
break; |
||||
case 3: |
||||
tsec2_clk = csb_clk / 3; |
||||
break; |
||||
default: |
||||
/* unkown SCCR_TSEC2CM value */ |
||||
return -5; |
||||
} |
||||
i2c_clk = tsec2_clk; |
||||
|
||||
switch ((sccr & SCCR_ENCCM) >> SCCR_ENCCM_SHIFT) { |
||||
case 0: |
||||
enc_clk = 0; |
||||
break; |
||||
case 1: |
||||
enc_clk = csb_clk; |
||||
break; |
||||
case 2: |
||||
enc_clk = csb_clk / 2; |
||||
break; |
||||
case 3: |
||||
enc_clk = csb_clk / 3; |
||||
break; |
||||
default: |
||||
/* unkown SCCR_ENCCM value */ |
||||
return -6; |
||||
} |
||||
|
||||
switch ((sccr & SCCR_USBMPHCM) >> SCCR_USBMPHCM_SHIFT) { |
||||
case 0: |
||||
usbmph_clk = 0; |
||||
break; |
||||
case 1: |
||||
usbmph_clk = csb_clk; |
||||
break; |
||||
case 2: |
||||
usbmph_clk = csb_clk / 2; |
||||
break; |
||||
case 3: |
||||
usbmph_clk = csb_clk / 3; |
||||
break; |
||||
default: |
||||
/* unkown SCCR_USBMPHCM value */ |
||||
return -7; |
||||
} |
||||
|
||||
switch ((sccr & SCCR_USBDRCM) >> SCCR_USBDRCM_SHIFT) { |
||||
case 0: |
||||
usbdr_clk = 0; |
||||
break; |
||||
case 1: |
||||
usbdr_clk = csb_clk; |
||||
break; |
||||
case 2: |
||||
usbdr_clk = csb_clk / 2; |
||||
break; |
||||
case 3: |
||||
usbdr_clk = csb_clk / 3; |
||||
break; |
||||
default: |
||||
/* unkown SCCR_USBDRCM value */ |
||||
return -8; |
||||
} |
||||
|
||||
if (usbmph_clk != 0 |
||||
&& usbdr_clk != 0 |
||||
&& usbmph_clk != usbdr_clk ) { |
||||
/* if USB MPH clock is not disabled and USB DR clock is not disabled than USB MPH & USB DR must have the same rate */ |
||||
return -9; |
||||
} |
||||
|
||||
lbiu_clk = csb_clk * (1 + ((im->reset.rcwl & RCWL_LBIUCM) >> RCWL_LBIUCM_SHIFT)); |
||||
lcrr = (im->lbus.lcrr & LCRR_CLKDIV) >> LCRR_CLKDIV_SHIFT; |
||||
switch (lcrr) { |
||||
case 2: |
||||
case 4: |
||||
case 8: |
||||
lclk_clk = lbiu_clk / lcrr; |
||||
break; |
||||
default: |
||||
/* unknown lcrr */ |
||||
return -10; |
||||
} |
||||
|
||||
ddr_clk = csb_clk * (1 + ((im->reset.rcwl & RCWL_DDRCM) >> RCWL_DDRCM_SHIFT)); |
||||
|
||||
corepll = (im->reset.rcwl & RCWL_COREPLL) >> RCWL_COREPLL_SHIFT; |
||||
corecnf_tab_index = ((corepll & 0x1F) << 2) | ((corepll & 0x60) >> 5); |
||||
if (corecnf_tab_index > (sizeof(corecnf_tab)/sizeof(corecnf_t)) ) { |
||||
/* corecnf_tab_index is too high, possibly worng value */ |
||||
return -11; |
||||
} |
||||
switch (corecnf_tab[corecnf_tab_index].core_csb_ratio) { |
||||
case _byp: |
||||
case _x1: |
||||
case _1x: |
||||
core_clk = csb_clk; |
||||
break; |
||||
case _1_5x: |
||||
core_clk = (3 * csb_clk) / 2; |
||||
break; |
||||
case _2x: |
||||
core_clk = 2 * csb_clk; |
||||
break; |
||||
case _2_5x: |
||||
core_clk = ( 5 * csb_clk) / 2; |
||||
break; |
||||
case _3x: |
||||
core_clk = 3 * csb_clk; |
||||
break; |
||||
default: |
||||
/* unkown core to csb ratio */ |
||||
return -12; |
||||
} |
||||
|
||||
gd->csb_clk = csb_clk ; |
||||
gd->tsec1_clk = tsec1_clk ; |
||||
gd->tsec2_clk = tsec2_clk ; |
||||
gd->core_clk = core_clk ; |
||||
gd->usbmph_clk = usbmph_clk; |
||||
gd->usbdr_clk = usbdr_clk ; |
||||
gd->i2c_clk = i2c_clk ; |
||||
gd->enc_clk = enc_clk ;
|
||||
gd->lbiu_clk = lbiu_clk ; |
||||
gd->lclk_clk = lclk_clk ; |
||||
gd->ddr_clk = ddr_clk ; |
||||
|
||||
gd->cpu_clk = gd->core_clk; |
||||
gd->bus_clk = gd->lbiu_clk; |
||||
return 0; |
||||
} |
||||
|
||||
/********************************************
|
||||
* get_bus_freq |
||||
* return system bus freq in Hz |
||||
*********************************************/ |
||||
ulong get_bus_freq (ulong dummy) |
||||
{ |
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
return gd->csb_clk; |
||||
} |
||||
|
||||
int print_clock_conf (void) |
||||
{ |
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
printf("Clock configuration:\n"); |
||||
printf(" Coherent System Bus: %4d MHz\n",gd->csb_clk/1000000); |
||||
printf(" Core: %4d MHz\n",gd->core_clk/1000000); |
||||
printf(" Local Bus Controller:%4d MHz\n",gd->lbiu_clk/1000000); |
||||
printf(" Local Bus: %4d MHz\n",gd->lclk_clk/1000000); |
||||
printf(" DDR: %4d MHz\n",gd->ddr_clk/1000000); |
||||
printf(" I2C: %4d MHz\n",gd->i2c_clk/1000000); |
||||
printf(" TSEC1: %4d MHz\n",gd->tsec1_clk/1000000); |
||||
printf(" TSEC2: %4d MHz\n",gd->tsec2_clk/1000000); |
||||
printf(" USB MPH: %4d MHz\n",gd->usbmph_clk/1000000); |
||||
printf(" USB DR: %4d MHz\n",gd->usbdr_clk/1000000); |
||||
|
||||
#if 0 |
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
volatile immap_t *immap = (immap_t *) CFG_IMMR; |
||||
ulong sccr, dfbrg; |
||||
ulong scmr, corecnf, busdf, cpmdf, plldf, pllmf; |
||||
corecnf_t *cp; |
||||
|
||||
sccr = immap->im_clkrst.car_sccr; |
||||
dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT; |
||||
|
||||
scmr = immap->im_clkrst.car_scmr; |
||||
corecnf = (scmr & SCMR_CORECNF_MSK) >> SCMR_CORECNF_SHIFT; |
||||
busdf = (scmr & SCMR_BUSDF_MSK) >> SCMR_BUSDF_SHIFT; |
||||
cpmdf = (scmr & SCMR_CPMDF_MSK) >> SCMR_CPMDF_SHIFT; |
||||
plldf = (scmr & SCMR_PLLDF) ? 1 : 0; |
||||
pllmf = (scmr & SCMR_PLLMF_MSK) >> SCMR_PLLMF_SHIFT; |
||||
|
||||
cp = &corecnf_tab[corecnf]; |
||||
|
||||
puts (CPU_ID_STR " Clock Configuration\n - Bus-to-Core Mult "); |
||||
|
||||
switch (cp->b2c_mult) { |
||||
case _byp: |
||||
puts ("BYPASS"); |
||||
break; |
||||
|
||||
case _off: |
||||
puts ("OFF"); |
||||
break; |
||||
|
||||
case _unk: |
||||
puts ("UNKNOWN"); |
||||
break; |
||||
|
||||
default: |
||||
printf ("%d%sx", |
||||
cp->b2c_mult / 2, |
||||
(cp->b2c_mult % 2) ? ".5" : ""); |
||||
break; |
||||
} |
||||
|
||||
printf (", VCO Div %d, 60x Bus Freq %s, Core Freq %s\n", |
||||
cp->vco_div, cp->freq_60x, cp->freq_core); |
||||
|
||||
printf (" - dfbrg %ld, corecnf 0x%02lx, busdf %ld, cpmdf %ld, " |
||||
"plldf %ld, pllmf %ld\n", dfbrg, corecnf, busdf, cpmdf, plldf, |
||||
pllmf); |
||||
|
||||
printf (" - vco_out %10ld, scc_clk %10ld, brg_clk %10ld\n", |
||||
gd->vco_out, gd->scc_clk, gd->brg_clk); |
||||
|
||||
printf (" - cpu_clk %10ld, cpm_clk %10ld, bus_clk %10ld\n", |
||||
gd->cpu_clk, gd->cpm_clk, gd->bus_clk); |
||||
|
||||
if (sccr & SCCR_PCI_MODE) { |
||||
uint pci_div; |
||||
|
||||
pci_div = ( (sccr & SCCR_PCI_MODCK) ? 2 : 1) * |
||||
( ( (sccr & SCCR_PCIDF_MSK) >> SCCR_PCIDF_SHIFT) + 1); |
||||
|
||||
printf (" - pci_clk %10ld\n", (gd->cpm_clk * 2) / pci_div); |
||||
} |
||||
putc ('\n'); |
||||
#endif |
||||
return (0); |
||||
} |
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,274 @@ |
||||
/*
|
||||
* linux/arch/ppc/kernel/traps.c |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
* |
||||
* Change log: |
||||
* |
||||
* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) |
||||
* |
||||
* Modified by Cort Dougan (cort@cs.nmt.edu) |
||||
* and Paul Mackerras (paulus@cs.anu.edu.au) |
||||
* |
||||
* (C) Copyright 2000 |
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
||||
* |
||||
* 20050101: Eran Liberty (liberty@freescale.com) |
||||
* Initial file creating (porting from 85XX & 8260) |
||||
*/ |
||||
|
||||
/*
|
||||
* This file handles the architecture-dependent parts of hardware |
||||
* exceptions |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <command.h> |
||||
#include <asm/processor.h> |
||||
#include <asm/mpc8349_pci.h> |
||||
|
||||
/* Returns 0 if exception not found and fixup otherwise. */ |
||||
extern unsigned long search_exception_table(unsigned long); |
||||
|
||||
#define END_OF_MEM (gd->bd->bi_memstart + gd->bd->bi_memsize) |
||||
|
||||
/*
|
||||
* Trap & Exception support |
||||
*/ |
||||
|
||||
void |
||||
print_backtrace(unsigned long *sp) |
||||
{ |
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
int cnt = 0; |
||||
unsigned long i; |
||||
|
||||
puts ("Call backtrace: "); |
||||
while (sp) { |
||||
if ((uint)sp > END_OF_MEM) |
||||
break; |
||||
|
||||
i = sp[1]; |
||||
if (cnt++ % 7 == 0) |
||||
putc ('\n'); |
||||
printf("%08lX ", i); |
||||
if (cnt > 32) break; |
||||
sp = (unsigned long *)*sp; |
||||
} |
||||
putc ('\n'); |
||||
} |
||||
|
||||
void show_regs(struct pt_regs * regs) |
||||
{ |
||||
int i; |
||||
|
||||
printf("NIP: %08lX XER: %08lX LR: %08lX REGS: %p TRAP: %04lx DAR: %08lX\n", |
||||
regs->nip, regs->xer, regs->link, regs, regs->trap, regs->dar); |
||||
printf("MSR: %08lx EE: %01x PR: %01x FP: %01x ME: %01x IR/DR: %01x%01x\n", |
||||
regs->msr, regs->msr&MSR_EE ? 1 : 0, regs->msr&MSR_PR ? 1 : 0, |
||||
regs->msr & MSR_FP ? 1 : 0,regs->msr&MSR_ME ? 1 : 0, |
||||
regs->msr&MSR_IR ? 1 : 0, |
||||
regs->msr&MSR_DR ? 1 : 0); |
||||
|
||||
putc ('\n'); |
||||
for (i = 0; i < 32; i++) { |
||||
if ((i % 8) == 0) { |
||||
printf("GPR%02d: ", i); |
||||
} |
||||
|
||||
printf("%08lX ", regs->gpr[i]); |
||||
if ((i % 8) == 7) { |
||||
putc ('\n'); |
||||
} |
||||
} |
||||
} |
||||
|
||||
|
||||
void |
||||
_exception(int signr, struct pt_regs *regs) |
||||
{ |
||||
show_regs(regs); |
||||
print_backtrace((unsigned long *)regs->gpr[1]); |
||||
panic("Exception in kernel pc %lx signal %d",regs->nip,signr); |
||||
} |
||||
|
||||
#ifdef CONFIG_PCI |
||||
void dump_pci (void) |
||||
{ |
||||
/*
|
||||
volatile immap_t *immap = (immap_t *) CFG_IMMR; |
||||
printf ("PCI: err status %x err mask %x err ctrl %x\n", |
||||
le32_to_cpu (immap->im_pci.pci_esr), |
||||
le32_to_cpu (immap->im_pci.pci_emr), |
||||
le32_to_cpu (immap->im_pci.pci_ecr)); |
||||
printf (" error address %x error data %x ctrl %x\n", |
||||
le32_to_cpu (immap->im_pci.pci_eacr), |
||||
le32_to_cpu (immap->im_pci.pci_edcr), |
||||
le32_to_cpu (immap->im_pci.pci_eccr)); |
||||
*/ |
||||
} |
||||
#endif |
||||
|
||||
void |
||||
MachineCheckException(struct pt_regs *regs) |
||||
{ |
||||
unsigned long fixup; |
||||
|
||||
/* Probing PCI using config cycles cause this exception
|
||||
* when a device is not present. Catch it and return to |
||||
* the PCI exception handler. |
||||
*/ |
||||
#ifdef CONFIG_PCI |
||||
#if 0 |
||||
volatile immap_t *immap = (immap_t *)CFG_IMMR; |
||||
#ifdef DEBUG |
||||
dump_pci(); |
||||
#endif |
||||
/* clear the error in the error status register */ |
||||
if(immap->im_pci.pci_esr & cpu_to_le32(PCI_ERROR_PCI_NO_RSP)) { |
||||
immap->im_pci.pci_esr = cpu_to_le32(PCI_ERROR_PCI_NO_RSP); |
||||
return; |
||||
} |
||||
#endif |
||||
#endif /* CONFIG_PCI */ |
||||
if ((fixup = search_exception_table(regs->nip)) != 0) { |
||||
regs->nip = fixup; |
||||
return; |
||||
} |
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
if (debugger_exception_handler && (*debugger_exception_handler)(regs)) |
||||
return; |
||||
#endif |
||||
|
||||
puts ("Machine check in kernel mode.\n" |
||||
"Caused by (from msr): "); |
||||
printf("regs %p ",regs); |
||||
switch( regs->msr & 0x000F0000) { |
||||
case (0x80000000>>12): |
||||
puts ("Machine check signal - probably due to mm fault\n" |
||||
"with mmu off\n"); |
||||
break; |
||||
case (0x80000000>>13): |
||||
puts ("Transfer error ack signal\n"); |
||||
break; |
||||
case (0x80000000>>14): |
||||
puts ("Data parity signal\n"); |
||||
break; |
||||
case (0x80000000>>15): |
||||
puts ("Address parity signal\n"); |
||||
break; |
||||
default: |
||||
puts ("Unknown values in msr\n"); |
||||
} |
||||
show_regs(regs); |
||||
print_backtrace((unsigned long *)regs->gpr[1]); |
||||
#ifdef CONFIG_PCI |
||||
dump_pci(); |
||||
#endif |
||||
panic("machine check"); |
||||
} |
||||
|
||||
void |
||||
AlignmentException(struct pt_regs *regs) |
||||
{ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
if (debugger_exception_handler && (*debugger_exception_handler)(regs)) |
||||
return; |
||||
#endif |
||||
show_regs(regs); |
||||
print_backtrace((unsigned long *)regs->gpr[1]); |
||||
panic("Alignment Exception"); |
||||
} |
||||
|
||||
void |
||||
ProgramCheckException(struct pt_regs *regs) |
||||
{ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
if (debugger_exception_handler && (*debugger_exception_handler)(regs)) |
||||
return; |
||||
#endif |
||||
show_regs(regs); |
||||
print_backtrace((unsigned long *)regs->gpr[1]); |
||||
panic("Program Check Exception"); |
||||
} |
||||
|
||||
void |
||||
SoftEmuException(struct pt_regs *regs) |
||||
{ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
if (debugger_exception_handler && (*debugger_exception_handler)(regs)) |
||||
return; |
||||
#endif |
||||
show_regs(regs); |
||||
print_backtrace((unsigned long *)regs->gpr[1]); |
||||
panic("Software Emulation Exception"); |
||||
} |
||||
|
||||
|
||||
void |
||||
UnknownException(struct pt_regs *regs) |
||||
{ |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
if (debugger_exception_handler && (*debugger_exception_handler)(regs)) |
||||
return; |
||||
#endif |
||||
printf("Bad trap at PC: %lx, SR: %lx, vector=%lx\n", |
||||
regs->nip, regs->msr, regs->trap); |
||||
_exception(0, regs); |
||||
} |
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) |
||||
extern void do_bedbug_breakpoint(struct pt_regs *); |
||||
#endif |
||||
|
||||
void |
||||
DebugException(struct pt_regs *regs) |
||||
{ |
||||
printf("Debugger trap at @ %lx\n", regs->nip ); |
||||
show_regs(regs); |
||||
#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) |
||||
do_bedbug_breakpoint( regs ); |
||||
#endif |
||||
} |
||||
|
||||
/* Probe an address by reading. If not present, return -1, otherwise
|
||||
* return 0. |
||||
*/ |
||||
int |
||||
addr_probe(uint *addr) |
||||
{ |
||||
#if 0 |
||||
int retval; |
||||
|
||||
__asm__ __volatile__( \
|
||||
"1: lwz %0,0(%1)\n" \
|
||||
" eieio\n" \
|
||||
" li %0,0\n" \
|
||||
"2:\n" \
|
||||
".section .fixup,\"ax\"\n" \
|
||||
"3: li %0,-1\n" \
|
||||
" b 2b\n" \
|
||||
".section __ex_table,\"a\"\n" \
|
||||
" .align 2\n" \
|
||||
" .long 1b,3b\n" \
|
||||
".text" \
|
||||
: "=r" (retval) : "r"(addr)); |
||||
|
||||
return (retval); |
||||
#endif |
||||
return 0; |
||||
} |
||||
@ -0,0 +1,96 @@ |
||||
Freescale MPC83xx ADS Boards |
||||
----------------------------------------- |
||||
|
||||
0. Toolchain / Building |
||||
|
||||
% setenv CROSS_COMPILE /usr/powerpc/bin/powerpc-linux- |
||||
|
||||
% /usr/powerpc/bin/powerpc-linux-gcc -v |
||||
Reading specs from /usr/powerpc/lib/gcc/powerpc-linux/3.4.3/specs |
||||
Configured with: ../configure --prefix=/usr/powerpc |
||||
--exec-prefix=/usr/powerpc --target=powerpc-linux --enable-shared |
||||
--disable-nls --disable-multilib --enable-languages=c,c++,ada,f77,objc |
||||
Thread model: posix |
||||
gcc version 3.4.3 (Debian) |
||||
|
||||
% /usr/powerpc/bin/powerpc-linux-as -v |
||||
GNU assembler version 2.15 (powerpc-linux) using BFD version 2.15 |
||||
|
||||
|
||||
% make MPC8349ADS_config |
||||
Configuring for MPC8349ADS board... |
||||
|
||||
% make |
||||
|
||||
|
||||
1. Board Switches and Jumpers |
||||
|
||||
|
||||
2. Memory Map |
||||
|
||||
2.1. The memory map should look pretty much like this: |
||||
|
||||
0x0000_0000 0x7fff_ffff DDR 2G |
||||
0x8000_0000 0x9fff_ffff PCI MEM 512M |
||||
0xc000_0000 0xdfff_ffff Rapid IO 512M |
||||
0xe000_0000 0xe00f_ffff CCSR 1M |
||||
0xe200_0000 0xe2ff_ffff PCI IO 16M |
||||
0xf000_0000 0xf7ff_ffff SDRAM 128M |
||||
0xf800_0000 0xf80f_ffff BCSR 1M |
||||
0xfe00_0000 0xffff_ffff FLASH (boot bank) 16M |
||||
|
||||
|
||||
3. Definitions |
||||
|
||||
3.1 Explanation of NEW definitions in: |
||||
|
||||
include/configs/MPC8349ADS.h |
||||
|
||||
CONFIG_MPC83xx MPC83xx family |
||||
CONFIG_MPC8349 MPC8349 specific |
||||
CONFIG_MPC8349ADS MPC8349ADS board specific |
||||
CONFIG_TSEC_ENET Use on-chip 10/100/1000 ethernet |
||||
|
||||
|
||||
4. Compilation |
||||
|
||||
Assuming you're using BASH shell: |
||||
|
||||
export CROSS_COMPILE=your-cross-compile-prefix |
||||
cd u-boot |
||||
make distclean |
||||
make MPC8349ADS_config |
||||
make |
||||
|
||||
5. Downloading and Flashing Images |
||||
|
||||
5.0 Download over serial line using Kermit: |
||||
|
||||
loadb |
||||
[Drop to kermit: |
||||
^\c |
||||
send <u-boot-bin-image> |
||||
c |
||||
] |
||||
|
||||
|
||||
Or via tftp: |
||||
|
||||
tftp 10000 u-boot.bin |
||||
|
||||
5.1 Reflash U-boot Image using U-boot |
||||
|
||||
tftp 10000 u-boot.bin |
||||
protect off fe000000 fe09ffff |
||||
erase fe000000 fe09ffff |
||||
|
||||
cp.b 10000 fe000000 xxxx |
||||
or |
||||
cp.b 10000 fe000000 a0000 |
||||
|
||||
You might have to supply the correct byte count for 'xxxx' from |
||||
the TFTP. Maybe a0000 will work too, that corresponds to the |
||||
erased sectors. |
||||
|
||||
|
||||
6. Notes |
||||
@ -0,0 +1,128 @@ |
||||
/*
|
||||
* Copyright 2004 Freescale Semiconductor, Inc. |
||||
* Liberty Eran (liberty@freescale.com) |
||||
*/ |
||||
|
||||
#ifndef __E300_H__ |
||||
#define __E300_H__ |
||||
|
||||
/*
|
||||
* e300 Processor Version & Revision Numbers
|
||||
*/ |
||||
#define PVR_83xx 0x80830000 |
||||
#define PVR_8349_REV10 (PVR_83xx | 0x0010) |
||||
#define PVR_8349_REV11 (PVR_83xx | 0x0011) |
||||
|
||||
/*
|
||||
* Hardware Implementation-Dependent Register 0 (HID0) |
||||
*/ |
||||
|
||||
/* #define HID0 1008 already defined in processor.h */ |
||||
#define HID0_MASK_MACHINE_CHECK 0x00000000 |
||||
#define HID0_ENABLE_MACHINE_CHECK 0x80000000 |
||||
|
||||
#define HID0_DISABLE_CACHE_PARITY 0x00000000 |
||||
#define HID0_ENABLE_CACHE_PARITY 0x40000000 |
||||
|
||||
#define HID0_DISABLE_ADDRESS_PARITY 0x00000000 /* on mpc8349ads must be disabled */ |
||||
#define HID0_ENABLE_ADDRESS_PARITY 0x20000000 |
||||
|
||||
#define HID0_DISABLE_DATA_PARITY 0x00000000 /* on mpc8349ads must be disabled */ |
||||
#define HID0_ENABLE_DATE_PARITY 0x10000000 |
||||
|
||||
#define HID0_CORE_CLK_OUT 0x00000000 |
||||
#define HID0_CORE_CLK_OUT_DIV_2 0x08000000 |
||||
|
||||
#define HID0_ENABLE_ARTRY_OUT_PRECHARGE 0x00000000 /* on mpc8349ads must be enabled */ |
||||
#define HID0_DISABLE_ARTRY_OUT_PRECHARGE 0x01000000 |
||||
|
||||
#define HID0_DISABLE_DOSE_MODE 0x00000000 |
||||
#define HID0_ENABLE_DOSE_MODE 0x00800000 |
||||
|
||||
#define HID0_DISABLE_NAP_MODE 0x00000000 |
||||
#define HID0_ENABLE_NAP_MODE 0x00400000 |
||||
|
||||
#define HID0_DISABLE_SLEEP_MODE 0x00000000 |
||||
#define HID0_ENABLE_SLEEP_MODE 0x00200000 |
||||
|
||||
#define HID0_DISABLE_DYNAMIC_POWER_MANAGMENT 0x00000000 |
||||
#define HID0_ENABLE_DYNAMIC_POWER_MANAGMENT 0x00100000 |
||||
|
||||
#define HID0_SOFT_RESET 0x00010000 |
||||
|
||||
#define HID0_DISABLE_INSTRUCTION_CACHE 0x00000000 |
||||
#define HID0_ENABLE_INSTRUCTION_CACHE 0x00008000 |
||||
|
||||
#define HID0_DISABLE_DATA_CACHE 0x00000000 |
||||
#define HID0_ENABLE_DATA_CACHE 0x00004000 |
||||
|
||||
#define HID0_LOCK_INSTRUCTION_CACHE 0x00002000 |
||||
|
||||
#define HID0_LOCK_DATA_CACHE 0x00001000 |
||||
|
||||
#define HID0_INVALIDATE_INSTRUCTION_CACHE 0x00000800 |
||||
|
||||
#define HID0_INVALIDATE_DATA_CACHE 0x00000400 |
||||
|
||||
#define HID0_DISABLE_M_BIT 0x00000000 |
||||
#define HID0_ENABLE_M_BIT 0x00000080 |
||||
|
||||
#define HID0_FBIOB 0x00000010 |
||||
|
||||
#define HID0_DISABLE_ADDRESS_BROADCAST 0x00000000 |
||||
#define HID0_ENABLE_ADDRESS_BROADCAST 0x00000008 |
||||
|
||||
#define HID0_ENABLE_NOOP_DCACHE_INSTRUCTION 0x00000000 |
||||
#define HID0_DISABLE_NOOP_DCACHE_INSTRUCTION 0x00000001 |
||||
|
||||
/*
|
||||
* Hardware Implementation-Dependent Register 2 (HID2) |
||||
*/ |
||||
#define HID2 1011 |
||||
|
||||
#define HID2_LET 0x08000000 |
||||
#define HID2_HBE 0x00040000 |
||||
#define HID2_IWLCK_000 0x00000000 /* no ways locked */ |
||||
#define HID2_IWLCK_001 0x00002000 /* way 0 locked */ |
||||
#define HID2_IWLCK_010 0x00004000 /* way 0 through way 1 locked */ |
||||
#define HID2_IWLCK_011 0x00006000 /* way 0 through way 2 locked */ |
||||
#define HID2_IWLCK_100 0x00008000 /* way 0 through way 3 locked */ |
||||
#define HID2_IWLCK_101 0x0000A000 /* way 0 through way 4 locked */ |
||||
#define HID2_IWLCK_110 0x0000C000 /* way 0 through way 5 locked */ |
||||
|
||||
|
||||
/* BAT (block address translation */ |
||||
#define BATU_BEPI_MSK 0xfffe0000 |
||||
#define BATU_BL_MSK 0x00001ffc |
||||
|
||||
#define BATU_BL_128K 0x00000000 |
||||
#define BATU_BL_256K 0x00000004 |
||||
#define BATU_BL_512K 0x0000000c |
||||
#define BATU_BL_1M 0x0000001c |
||||
#define BATU_BL_2M 0x0000003c |
||||
#define BATU_BL_4M 0x0000007c |
||||
#define BATU_BL_8M 0x000000fc |
||||
#define BATU_BL_16M 0x000001fc |
||||
#define BATU_BL_32M 0x000003fc |
||||
#define BATU_BL_64M 0x000007fc |
||||
#define BATU_BL_128M 0x00000ffc |
||||
#define BATU_BL_256M 0x00001ffc |
||||
|
||||
#define BATU_VS 0x00000002 |
||||
#define BATU_VP 0x00000001 |
||||
|
||||
#define BATL_BRPN_MSK 0xfffe0000 |
||||
#define BATL_WIMG_MSK 0x00000078 |
||||
|
||||
#define BATL_WRITETHROUGH 0x00000040 |
||||
#define BATL_CACHEINHIBIT 0x00000020 |
||||
#define BATL_MEMCOHERENCE 0x00000010 |
||||
#define BATL_GUARDEDSTORAGE 0x00000008 |
||||
|
||||
#define BATL_PP_MSK 0x00000003 |
||||
#define BATL_PP_00 0x00000000 /* No access */ |
||||
#define BATL_PP_01 0x00000001 /* Read-only */ |
||||
#define BATL_PP_10 0x00000002 /* Read-write */ |
||||
#define BATL_PP_11 0x00000003 |
||||
|
||||
#endif /* __E300_H__ */ |
||||
@ -0,0 +1,104 @@ |
||||
/*
|
||||
* Freescale I2C Controller |
||||
* |
||||
* This software may be used and distributed according to the |
||||
* terms of the GNU Public License, Version 2, incorporated |
||||
* herein by reference. |
||||
* |
||||
* Copyright 2004 Freescale Semiconductor. |
||||
* (C) Copyright 2003, Motorola, Inc. |
||||
* author: Eran Liberty (liberty@freescale.com) |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
#ifndef _ASM_I2C_H_ |
||||
#define _ASM_I2C_H_ |
||||
|
||||
#include <asm/types.h> |
||||
|
||||
typedef struct i2c |
||||
{ |
||||
u8 adr; /**< I2C slave address */ |
||||
#define I2C_ADR 0xFE |
||||
#define I2C_ADR_SHIFT 1 |
||||
#define I2C_ADR_RES ~(I2C_ADR) |
||||
u8 res0[3];
|
||||
u8 fdr; /**< I2C frequency divider register */ |
||||
|
||||
#define IC2_FDR 0x3F |
||||
#define IC2_FDR_SHIFT 0 |
||||
#define IC2_FDR_RES ~(IC2_FDR) |
||||
u8 res1[3];
|
||||
u8 cr; /**< I2C control redister */ |
||||
#define I2C_CR_MEN 0x80 |
||||
#define I2C_CR_MIEN 0x40 |
||||
#define I2C_CR_MSTA 0x20 |
||||
#define I2C_CR_MTX 0x10 |
||||
#define I2C_CR_TXAK 0x08 |
||||
#define I2C_CR_RSTA 0x04 |
||||
#define I2C_CR_BCST 0x01 |
||||
u8 res2[3];
|
||||
u8 sr; /**< I2C status register */ |
||||
#define I2C_SR_MCF 0x80 |
||||
#define I2C_SR_MAAS 0x40 |
||||
#define I2C_SR_MBB 0x20 |
||||
#define I2C_SR_MAL 0x10 |
||||
#define I2C_SR_BCSTM 0x08 |
||||
#define I2C_SR_SRW 0x04 |
||||
#define I2C_SR_MIF 0x02 |
||||
#define I2C_SR_RXAK 0x01 |
||||
u8 res3[3];
|
||||
u8 dr; /**< I2C data register */ |
||||
#define I2C_DR 0xFF |
||||
#define I2C_DR_SHIFT 0 |
||||
#define I2C_DR_RES ~(I2C_DR) |
||||
u8 res4[3];
|
||||
u8 dfsrr; /**< I2C digital filter sampling rate register */ |
||||
#define I2C_DFSRR 0x3F |
||||
#define I2C_DFSRR_SHIFT 0 |
||||
#define I2C_DFSRR_RES ~(I2C_DR) |
||||
u8 res5[3]; |
||||
u8 res6[0xE8];
|
||||
} i2c_t; |
||||
|
||||
#ifndef CFG_HZ |
||||
#error CFG_HZ is not defined in /include/configs/${BOARD}.h |
||||
#endif |
||||
#define I2C_TIMEOUT (CFG_HZ/4) |
||||
|
||||
#ifndef CFG_IMMRBAR |
||||
#error CFG_IMMRBAR is not defined in /include/configs/${BOARD}.h |
||||
#endif |
||||
|
||||
#ifndef CFG_I2C_OFFSET |
||||
#error CFG_I2C_OFFSET is not defined in /include/configs/${BOARD}.h |
||||
#endif |
||||
|
||||
#ifdef CONFIG_MPC8349ADS |
||||
/*
|
||||
* MPC8349 have two i2c bus
|
||||
*/ |
||||
extern i2c_t * mpc8349_i2c; |
||||
#define I2C mpc8349_i2c |
||||
#else |
||||
#define I2C ((i2c_t*)(CFG_IMMRBAR + CFG_I2C_OFFSET)) |
||||
#endif |
||||
|
||||
#define I2C_READ 1 |
||||
#define I2C_WRITE 0 |
||||
|
||||
#endif /* _ASM_I2C_H_ */ |
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,167 @@ |
||||
#ifndef _PPC_KERNEL_MPC8349_PCI_H |
||||
#define _PPC_KERNEL_MPC8349_PCI_H |
||||
|
||||
|
||||
#define M8265_PCIBR0 0x101ac |
||||
#define M8265_PCIBR1 0x101b0 |
||||
#define M8265_PCIMSK0 0x101c4 |
||||
#define M8265_PCIMSK1 0x101c8 |
||||
|
||||
/* Bit definitions for PCIBR registers */ |
||||
|
||||
#define PCIBR_ENABLE 0x00000001 |
||||
|
||||
/* Bit definitions for PCIMSK registers */ |
||||
|
||||
#define PCIMSK_32KB 0xFFFF8000 /* Size of window, smallest */ |
||||
#define PCIMSK_64KB 0xFFFF0000 |
||||
#define PCIMSK_128KB 0xFFFE0000 |
||||
#define PCIMSK_256KB 0xFFFC0000 |
||||
#define PCIMSK_512KB 0xFFF80000 |
||||
#define PCIMSK_1MB 0xFFF00000 |
||||
#define PCIMSK_2MB 0xFFE00000 |
||||
#define PCIMSK_4MB 0xFFC00000 |
||||
#define PCIMSK_8MB 0xFF800000 |
||||
#define PCIMSK_16MB 0xFF000000 |
||||
#define PCIMSK_32MB 0xFE000000 |
||||
#define PCIMSK_64MB 0xFC000000 |
||||
#define PCIMSK_128MB 0xF8000000 |
||||
#define PCIMSK_256MB 0xF0000000 |
||||
#define PCIMSK_512MB 0xE0000000 |
||||
#define PCIMSK_1GB 0xC0000000 /* Size of window, largest */ |
||||
|
||||
|
||||
#define M826X_SCCR_PCI_MODE_EN 0x100 |
||||
|
||||
|
||||
/*
|
||||
* Outbound ATU registers (3 sets). These registers control how 60x bus |
||||
* (local) addresses are translated to PCI addresses when the MPC826x is |
||||
* a PCI bus master (initiator). |
||||
*/ |
||||
|
||||
#define POTAR_REG0 0x10800 /* PCI Outbound Translation Addr registers */ |
||||
#define POTAR_REG1 0x10818 |
||||
#define POTAR_REG2 0x10830 |
||||
|
||||
#define POBAR_REG0 0x10808 /* PCI Outbound Base Addr registers */ |
||||
#define POBAR_REG1 0x10820 |
||||
#define POBAR_REG2 0x10838 |
||||
|
||||
#define POCMR_REG0 0x10810 /* PCI Outbound Comparison Mask registers */ |
||||
#define POCMR_REG1 0x10828 |
||||
#define POCMR_REG2 0x10840 |
||||
|
||||
/* Bit definitions for POMCR registers */ |
||||
|
||||
#define POCMR_MASK_4KB 0x000FFFFF |
||||
#define POCMR_MASK_8KB 0x000FFFFE |
||||
#define POCMR_MASK_16KB 0x000FFFFC |
||||
#define POCMR_MASK_32KB 0x000FFFF8 |
||||
#define POCMR_MASK_64KB 0x000FFFF0 |
||||
#define POCMR_MASK_128KB 0x000FFFE0 |
||||
#define POCMR_MASK_256KB 0x000FFFC0 |
||||
#define POCMR_MASK_512KB 0x000FFF80 |
||||
#define POCMR_MASK_1MB 0x000FFF00 |
||||
#define POCMR_MASK_2MB 0x000FFE00 |
||||
#define POCMR_MASK_4MB 0x000FFC00 |
||||
#define POCMR_MASK_8MB 0x000FF800 |
||||
#define POCMR_MASK_16MB 0x000FF000 |
||||
#define POCMR_MASK_32MB 0x000FE000 |
||||
#define POCMR_MASK_64MB 0x000FC000 |
||||
#define POCMR_MASK_128MB 0x000F8000 |
||||
#define POCMR_MASK_256MB 0x000F0000 |
||||
#define POCMR_MASK_512MB 0x000E0000 |
||||
#define POCMR_MASK_1GB 0x000C0000 |
||||
|
||||
#define POCMR_ENABLE 0x80000000 |
||||
#define POCMR_PCI_IO 0x40000000 |
||||
#define POCMR_PREFETCH_EN 0x20000000 |
||||
|
||||
/* Soft PCI reset */ |
||||
|
||||
#define PCI_GCR_REG 0x10880 |
||||
|
||||
/* Bit definitions for PCI_GCR registers */ |
||||
|
||||
#define PCIGCR_PCI_BUS_EN 0x1 |
||||
|
||||
/*
|
||||
* Inbound ATU registers (2 sets). These registers control how PCI |
||||
* addresses are translated to 60x bus (local) addresses when the |
||||
* MPC826x is a PCI bus target. |
||||
*/ |
||||
|
||||
#define PITAR_REG1 0x108D0 |
||||
#define PIBAR_REG1 0x108D8 |
||||
#define PICMR_REG1 0x108E0 |
||||
#define PITAR_REG0 0x108E8 |
||||
#define PIBAR_REG0 0x108F0 |
||||
#define PICMR_REG0 0x108F8 |
||||
|
||||
/* Bit definitions for PCI Inbound Comparison Mask registers */ |
||||
|
||||
#define PICMR_MASK_4KB 0x000FFFFF |
||||
#define PICMR_MASK_8KB 0x000FFFFE |
||||
#define PICMR_MASK_16KB 0x000FFFFC |
||||
#define PICMR_MASK_32KB 0x000FFFF8 |
||||
#define PICMR_MASK_64KB 0x000FFFF0 |
||||
#define PICMR_MASK_128KB 0x000FFFE0 |
||||
#define PICMR_MASK_256KB 0x000FFFC0 |
||||
#define PICMR_MASK_512KB 0x000FFF80 |
||||
#define PICMR_MASK_1MB 0x000FFF00 |
||||
#define PICMR_MASK_2MB 0x000FFE00 |
||||
#define PICMR_MASK_4MB 0x000FFC00 |
||||
#define PICMR_MASK_8MB 0x000FF800 |
||||
#define PICMR_MASK_16MB 0x000FF000 |
||||
#define PICMR_MASK_32MB 0x000FE000 |
||||
#define PICMR_MASK_64MB 0x000FC000 |
||||
#define PICMR_MASK_128MB 0x000F8000 |
||||
#define PICMR_MASK_256MB 0x000F0000 |
||||
#define PICMR_MASK_512MB 0x000E0000 |
||||
#define PICMR_MASK_1GB 0x000C0000 |
||||
|
||||
#define PICMR_ENABLE 0x80000000 |
||||
#define PICMR_NO_SNOOP_EN 0x40000000 |
||||
#define PICMR_PREFETCH_EN 0x20000000 |
||||
|
||||
/* PCI error Registers */ |
||||
|
||||
#define PCI_ERROR_STATUS_REG 0x10884 |
||||
#define PCI_ERROR_MASK_REG 0x10888 |
||||
#define PCI_ERROR_CONTROL_REG 0x1088C |
||||
#define PCI_ERROR_ADRS_CAPTURE_REG 0x10890 |
||||
#define PCI_ERROR_DATA_CAPTURE_REG 0x10898 |
||||
#define PCI_ERROR_CTRL_CAPTURE_REG 0x108A0 |
||||
|
||||
/* PCI error Register bit defines */ |
||||
|
||||
#define PCI_ERROR_PCI_ADDR_PAR 0x00000001 |
||||
#define PCI_ERROR_PCI_DATA_PAR_WR 0x00000002 |
||||
#define PCI_ERROR_PCI_DATA_PAR_RD 0x00000004 |
||||
#define PCI_ERROR_PCI_NO_RSP 0x00000008 |
||||
#define PCI_ERROR_PCI_TAR_ABT 0x00000010 |
||||
#define PCI_ERROR_PCI_SERR 0x00000020 |
||||
#define PCI_ERROR_PCI_PERR_RD 0x00000040 |
||||
#define PCI_ERROR_PCI_PERR_WR 0x00000080 |
||||
#define PCI_ERROR_I2O_OFQO 0x00000100 |
||||
#define PCI_ERROR_I2O_IPQO 0x00000200 |
||||
#define PCI_ERROR_IRA 0x00000400 |
||||
#define PCI_ERROR_NMI 0x00000800 |
||||
#define PCI_ERROR_I2O_DBMC 0x00001000 |
||||
|
||||
/*
|
||||
* Register pair used to generate configuration cycles on the PCI bus |
||||
* and access the MPC826x's own PCI configuration registers. |
||||
*/ |
||||
|
||||
#define PCI_CFG_ADDR_REG 0x10900 |
||||
#define PCI_CFG_DATA_REG 0x10904 |
||||
|
||||
/* Bus parking decides where the bus control sits when idle */ |
||||
/* If modifying memory controllers for PCI park on the core */ |
||||
|
||||
#define PPC_ACR_BUS_PARK_CORE 0x6 |
||||
#define PPC_ACR_BUS_PARK_PCI 0x3 |
||||
|
||||
#endif /* _PPC_KERNEL_M8260_PCI_H */ |
||||
@ -0,0 +1,609 @@ |
||||
/*
|
||||
* Copyright 2004 Freescale Semiconductor. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
/*
|
||||
* mpc8349ads board configuration file |
||||
* |
||||
* Please refer to doc/README.mpc83xxads for more info. |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_H |
||||
#define __CONFIG_H |
||||
|
||||
#undef DEBUG |
||||
|
||||
#define CONFIG_MII |
||||
|
||||
/*
|
||||
* High Level Configuration Options |
||||
*/ |
||||
#define CONFIG_E300 1 /* E300 Family */ |
||||
#define CONFIG_MPC83XX 1 /* MPC83XX family */ |
||||
#define CONFIG_MPC8349 1 /* MPC8349 specific */ |
||||
#define CONFIG_MPC8349ADS 1 /* MPC8349ADS board specific */ |
||||
|
||||
#define CONFIG_PCI |
||||
|
||||
#define CONFIG_TSEC_ENET /* tsec ethernet support */ |
||||
#define CONFIG_ENV_OVERWRITE |
||||
|
||||
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ |
||||
|
||||
#undef CONFIG_DDR_ECC /* only for ECC DDR module */ |
||||
|
||||
#define PCI_66M |
||||
#ifdef PCI_66M |
||||
#define CONFIG_83XX_CLKIN 66000000 /* in Hz */ |
||||
#else |
||||
#define CONFIG_83XX_CLKIN 33000000 /* in Hz */ |
||||
#endif |
||||
|
||||
#ifndef CONFIG_SYS_CLK_FREQ |
||||
#ifdef PCI_66M |
||||
#define CONFIG_SYS_CLK_FREQ 66000000 |
||||
#else |
||||
#define CONFIG_SYS_CLK_FREQ 33000000 |
||||
#endif |
||||
#endif |
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ |
||||
|
||||
#define CFG_IMMRBAR 0xE0000000 |
||||
|
||||
#undef CFG_DRAM_TEST /* memory test, takes time */ |
||||
#define CFG_MEMTEST_START 0x00000000 /* memtest region */ |
||||
#define CFG_MEMTEST_END 0x00100000 |
||||
|
||||
|
||||
|
||||
/*
|
||||
* DDR Setup |
||||
*/ |
||||
|
||||
#define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/ |
||||
#define CFG_SDRAM_BASE CFG_DDR_BASE |
||||
#undef CONFIG_DDR_2T_TIMING |
||||
#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE |
||||
|
||||
#if defined(CONFIG_SPD_EEPROM) |
||||
/*
|
||||
* Determine DDR configuration from I2C interface. |
||||
*/ |
||||
#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ |
||||
|
||||
#else |
||||
/*
|
||||
* Manually set up DDR parameters |
||||
*/ |
||||
#define CFG_DDR_SIZE 256 /* Mb */ |
||||
#define CFG_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_9) |
||||
#define CFG_DDR_TIMING_1 0x37344321 |
||||
#define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ |
||||
#define CFG_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ |
||||
#define CFG_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */ |
||||
#define CFG_DDR_INTERVAL 0x05200100 /* autocharge,no open page */ |
||||
#endif |
||||
|
||||
|
||||
/*
|
||||
* SDRAM on the Local Bus |
||||
*/ |
||||
#define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ |
||||
#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ |
||||
|
||||
/*
|
||||
* FLASH on the Local Bus |
||||
*/ |
||||
#define CFG_FLASH_CFI /* use the Common Flash Interface */ |
||||
#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ |
||||
#define CFG_FLASH_BASE 0xFE000000 /* start of FLASH */ |
||||
#define CFG_FLASH_SIZE 8 /* FLASH size in MB */ |
||||
/* #define CFG_FLASH_USE_BUFFER_WRITE */ |
||||
|
||||
#define CFG_BR0_PRELIM (CFG_FLASH_BASE | /* Flash Base address */ \ |
||||
(2 << BR_PS_SHIFT) | /* 32 bit port size */ \
|
||||
BR_V) /* valid */ |
||||
#define CFG_OR0_PRELIM 0xff806ff7 /* 16Mb Flash size*/ |
||||
#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */ |
||||
#define CFG_LBLAWAR0_PRELIM 0x80000016 /* 16Mb window size */ |
||||
|
||||
|
||||
#define CFG_MAX_FLASH_BANKS 1 /* number of banks */ |
||||
#define CFG_MAX_FLASH_SECT 64 /* sectors per device */ |
||||
|
||||
#undef CFG_FLASH_CHECKSUM |
||||
#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ |
||||
#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ |
||||
|
||||
#define CFG_MID_FLASH_JUMP 0x7F000000 |
||||
#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ |
||||
|
||||
|
||||
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) |
||||
#define CFG_RAMBOOT |
||||
#else |
||||
#undef CFG_RAMBOOT |
||||
#endif |
||||
|
||||
/*
|
||||
* BCSR register on local bus 32KB, 8-bit wide for ADS config reg |
||||
*/ |
||||
#define CFG_BCSR 0xF8000000 |
||||
#define CFG_LBLAWBAR1_PRELIM CFG_BCSR /* Access window base at BCSR base */ |
||||
#define CFG_LBLAWAR1_PRELIM 0x8000000E /* Access window size 32K */ |
||||
#define CFG_BR1_PRELIM (CFG_BCSR|0x00000801) /* Port-size=8bit, MSEL=GPCM */ |
||||
#define CFG_OR1_PRELIM 0xFFFFE8f0 /* length 32K */ |
||||
|
||||
|
||||
#define CONFIG_L1_INIT_RAM |
||||
#define CFG_INIT_RAM_LOCK 1 |
||||
#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ |
||||
#define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM*/ |
||||
|
||||
#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ |
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET |
||||
|
||||
#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ |
||||
#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ |
||||
|
||||
/*
|
||||
* Local Bus LCRR and LBCR regs |
||||
* LCRR: DLL bypass, Clock divider is 4 |
||||
* External Local Bus rate is |
||||
* CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV |
||||
*/ |
||||
#define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_4) |
||||
#define CFG_LBC_LBCR 0x00000000 |
||||
|
||||
#define CFG_LB_SDRAM /* if board has SRDAM on local bus */ |
||||
|
||||
#ifdef CFG_LB_SDRAM |
||||
/*local bus BR2, OR2 definition for SDRAM if soldered on the ADS board*/ |
||||
/*
|
||||
* Base Register 2 and Option Register 2 configure SDRAM. |
||||
* The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000. |
||||
* |
||||
* For BR2, need: |
||||
* Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 |
||||
* port-size = 32-bits = BR2[19:20] = 11 |
||||
* no parity checking = BR2[21:22] = 00 |
||||
* SDRAM for MSEL = BR2[24:26] = 011 |
||||
* Valid = BR[31] = 1 |
||||
* |
||||
* 0 4 8 12 16 20 24 28 |
||||
* 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 |
||||
* |
||||
* FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into |
||||
* FIXME: the top 17 bits of BR2. |
||||
*/ |
||||
|
||||
#define CFG_BR2_PRELIM 0xf0001861 /*Port-size=32bit, MSEL=SDRAM*/ |
||||
|
||||
#define CFG_LBLAWBAR2_PRELIM 0xF0000000 |
||||
|
||||
#define CFG_LBLAWAR2_PRELIM 0x80000019 /*64M*/ |
||||
|
||||
|
||||
/*
|
||||
* The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64. |
||||
* |
||||
* For OR2, need: |
||||
* 64MB mask for AM, OR2[0:7] = 1111 1100 |
||||
* XAM, OR2[17:18] = 11 |
||||
* 9 columns OR2[19-21] = 010 |
||||
* 13 rows OR2[23-25] = 100 |
||||
* EAD set for extra time OR[31] = 1 |
||||
* |
||||
* 0 4 8 12 16 20 24 28 |
||||
* 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 |
||||
*/ |
||||
|
||||
#define CFG_OR2_PRELIM 0xfc006901 |
||||
|
||||
#define CFG_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */ |
||||
#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32*/ |
||||
|
||||
/*
|
||||
* LSDMR masks |
||||
*/ |
||||
#define CFG_LBC_LSDMR_RFEN (1 << (31 - 1)) |
||||
#define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10)) |
||||
#define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10)) |
||||
#define CFG_LBC_LSDMR_RFCR5 (3 << (31 - 16)) |
||||
#define CFG_LBC_LSDMR_RFCR8 (5 << (31 - 16)) |
||||
#define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16)) |
||||
#define CFG_LBC_LSDMR_PRETOACT3 (3 << (31 - 19)) |
||||
#define CFG_LBC_LSDMR_PRETOACT6 (5 << (31 - 19)) |
||||
#define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19)) |
||||
#define CFG_LBC_LSDMR_ACTTORW3 (3 << (31 - 22)) |
||||
#define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22)) |
||||
#define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22)) |
||||
#define CFG_LBC_LSDMR_BL8 (1 << (31 - 23)) |
||||
#define CFG_LBC_LSDMR_WRC2 (2 << (31 - 27)) |
||||
#define CFG_LBC_LSDMR_WRC3 (3 << (31 - 27)) |
||||
#define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27)) |
||||
#define CFG_LBC_LSDMR_BUFCMD (1 << (31 - 29)) |
||||
#define CFG_LBC_LSDMR_CL3 (3 << (31 - 31)) |
||||
|
||||
#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) |
||||
#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) |
||||
#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) |
||||
#define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4)) |
||||
#define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) |
||||
#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) |
||||
#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) |
||||
#define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) |
||||
|
||||
#define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_RFEN \ |
||||
| CFG_LBC_LSDMR_BSMA1516 \
|
||||
| CFG_LBC_LSDMR_RFCR8 \
|
||||
| CFG_LBC_LSDMR_PRETOACT6 \
|
||||
| CFG_LBC_LSDMR_ACTTORW3 \
|
||||
| CFG_LBC_LSDMR_BL8 \
|
||||
| CFG_LBC_LSDMR_WRC3 \
|
||||
| CFG_LBC_LSDMR_CL3 \
|
||||
) |
||||
|
||||
|
||||
/*
|
||||
* SDRAM Controller configuration sequence. |
||||
*/ |
||||
#define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \ |
||||
| CFG_LBC_LSDMR_OP_PCHALL) |
||||
#define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \ |
||||
| CFG_LBC_LSDMR_OP_ARFRSH) |
||||
#define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \ |
||||
| CFG_LBC_LSDMR_OP_ARFRSH) |
||||
#define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \ |
||||
| CFG_LBC_LSDMR_OP_MRW) |
||||
#define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \ |
||||
| CFG_LBC_LSDMR_OP_NORMAL) |
||||
|
||||
#endif |
||||
|
||||
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* Serial Port |
||||
*/ |
||||
#define CONFIG_CONS_INDEX 1 |
||||
#undef CONFIG_SERIAL_SOFTWARE_FIFO |
||||
#define CFG_NS16550 |
||||
#define CFG_NS16550_SERIAL |
||||
#define CFG_NS16550_REG_SIZE 1 |
||||
#define CFG_NS16550_CLK get_bus_freq(0) |
||||
|
||||
#define CFG_BAUDRATE_TABLE \ |
||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} |
||||
|
||||
#define CFG_NS16550_COM1 (CFG_IMMRBAR+0x4500) |
||||
#define CFG_NS16550_COM2 (CFG_IMMRBAR+0x4600) |
||||
|
||||
/* Use the HUSH parser */ |
||||
#define CFG_HUSH_PARSER |
||||
#ifdef CFG_HUSH_PARSER |
||||
#define CFG_PROMPT_HUSH_PS2 "> " |
||||
#endif |
||||
|
||||
/* I2C */ |
||||
#define CONFIG_HARD_I2C /* I2C with hardware support*/ |
||||
#undef CONFIG_SOFT_I2C /* I2C bit-banged */ |
||||
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ |
||||
#define CFG_I2C_SLAVE 0x7F |
||||
#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ |
||||
#define CFG_I2C_OFFSET 0x3000 |
||||
#define CFG_I2C2_OFFSET 0x3100 |
||||
|
||||
/* TSEC */ |
||||
#define CFG_TSEC1_OFFSET 0x24000 |
||||
#define CFG_TSEC1 (CFG_IMMRBAR+CFG_TSEC1_OFFSET) |
||||
#define CFG_TSEC2_OFFSET 0x25000 |
||||
#define CFG_TSEC2 (CFG_IMMRBAR+CFG_TSEC2_OFFSET) |
||||
|
||||
|
||||
/* IO Configuration */ |
||||
#define CFG_IO_CONF (\ |
||||
IO_CONF_UART |\
|
||||
IO_CONF_TSEC1 |\
|
||||
IO_CONF_IRQ0 |\
|
||||
IO_CONF_IRQ1 |\
|
||||
IO_CONF_IRQ2 |\
|
||||
IO_CONF_IRQ3 |\
|
||||
IO_CONF_IRQ4 |\
|
||||
IO_CONF_IRQ5 |\
|
||||
IO_CONF_IRQ6 |\
|
||||
IO_CONF_IRQ7 ) |
||||
|
||||
/*
|
||||
* General PCI |
||||
* Addresses are mapped 1-1. |
||||
*/ |
||||
#define CFG_PCI1_MEM_BASE 0x80000000 |
||||
#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE |
||||
#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ |
||||
#define CFG_PCI1_IO_BASE 0x00000000 |
||||
#define CFG_PCI1_IO_PHYS 0xe2000000 |
||||
#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ |
||||
|
||||
|
||||
#define CFG_PCI2_MEM_BASE 0xA0000000 |
||||
#define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE |
||||
#define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */ |
||||
#define CFG_PCI2_IO_BASE 0x00000000 |
||||
#define CFG_PCI2_IO_PHYS 0xe3000000 |
||||
#define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */ |
||||
#if defined(CONFIG_PCI) |
||||
|
||||
//#define PCI_64BIT
|
||||
#define PCI_ALL_PCI1 |
||||
//#define PCI_ONE_PCI1
|
||||
//#define PCI_TWO_PCI1
|
||||
#if defined(PCI_64BIT) |
||||
#undef PCI_ALL_PCI1 |
||||
#undef PCI_TWO_PCI1 |
||||
#undef PCI_ONE_PCI1 |
||||
#endif |
||||
|
||||
#define CONFIG_NET_MULTI |
||||
#define CONFIG_PCI_PNP /* do pci plug-and-play */ |
||||
|
||||
#undef CONFIG_EEPRO100 |
||||
#undef CONFIG_TULIP |
||||
|
||||
#if !defined(CONFIG_PCI_PNP) |
||||
#define PCI_ENET0_IOADDR 0xFIXME |
||||
#define PCI_ENET0_MEMADDR 0xFIXME |
||||
#define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ |
||||
#endif |
||||
|
||||
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
||||
#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ |
||||
|
||||
#endif /* CONFIG_PCI */ |
||||
|
||||
|
||||
#if defined(CONFIG_TSEC_ENET) |
||||
|
||||
#ifndef CONFIG_NET_MULTI |
||||
#define CONFIG_NET_MULTI 1 |
||||
#endif |
||||
|
||||
#define CONFIG_GMII 1 /* MII PHY management */ |
||||
#define CONFIG_MPC83XX_TSEC1 1 |
||||
#define CONFIG_MPC83XX_TSEC1_NAME "TSEC0" |
||||
#define CONFIG_MPC83XX_TSEC2 1 |
||||
#define CONFIG_MPC83XX_TSEC2_NAME "TSEC1" |
||||
#define TSEC1_PHY_ADDR 0 |
||||
#define TSEC2_PHY_ADDR 1 |
||||
#define TSEC1_PHYIDX 0 |
||||
#define TSEC2_PHYIDX 0 |
||||
|
||||
/* Options are: TSEC[0-1] */ |
||||
#define CONFIG_ETHPRIME "TSEC0" |
||||
|
||||
#endif /* CONFIG_TSEC_ENET */ |
||||
|
||||
|
||||
/*
|
||||
* Environment |
||||
*/ |
||||
#ifndef CFG_RAMBOOT |
||||
#define CFG_ENV_IS_IN_FLASH 1 |
||||
#define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) |
||||
#define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ |
||||
#define CFG_ENV_SIZE 0x2000 |
||||
#else |
||||
#define CFG_NO_FLASH 1 /* Flash is not usable now */ |
||||
#define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ |
||||
#define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) |
||||
#define CFG_ENV_SIZE 0x2000 |
||||
#endif |
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
||||
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
||||
|
||||
#if defined(CFG_RAMBOOT) |
||||
#if defined(CONFIG_PCI) |
||||
#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ |
||||
| CFG_CMD_PING \
|
||||
| CFG_CMD_PCI \
|
||||
| CFG_CMD_I2C) \
|
||||
& \
|
||||
~(CFG_CMD_ENV \
|
||||
| CFG_CMD_LOADS)) |
||||
#else |
||||
#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ |
||||
| CFG_CMD_PING \
|
||||
| CFG_CMD_I2C) \
|
||||
& \
|
||||
~(CFG_CMD_ENV \
|
||||
| CFG_CMD_LOADS)) |
||||
#endif |
||||
#else |
||||
#if defined(CONFIG_PCI) |
||||
#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ |
||||
| CFG_CMD_PCI \
|
||||
| CFG_CMD_PING \
|
||||
| CFG_CMD_I2C) |
||||
#else |
||||
#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ |
||||
| CFG_CMD_PING \
|
||||
| CFG_CMD_I2C \
|
||||
| CFG_CMD_MII \
|
||||
) |
||||
#endif |
||||
#endif |
||||
|
||||
#include <cmd_confdefs.h> |
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */ |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CFG_LONGHELP /* undef to save memory */ |
||||
#define CFG_LOAD_ADDR 0x2000000 /* default load address */ |
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */ |
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#else |
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#endif |
||||
|
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
||||
#define CFG_MAXARGS 16 /* max number of command args */ |
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
||||
#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 8 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization. |
||||
*/ |
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ |
||||
|
||||
/* Cache Configuration */ |
||||
#define CFG_DCACHE_SIZE 32768 |
||||
#define CFG_CACHELINE_SIZE 32 |
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ |
||||
#endif |
||||
|
||||
#define CFG_RCWH_PCIHOST 0x80000000 /* PCIHOST */ |
||||
|
||||
#define CFG_HRCW_LOW (\ |
||||
HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
|
||||
HRCWL_DDR_TO_SCB_CLK_1X1 |\
|
||||
HRCWL_CSB_TO_CLKIN_4X1 |\
|
||||
HRCWL_VCO_1X2 |\
|
||||
HRCWL_CORE_TO_CSB_2X1) |
||||
|
||||
#if defined(PCI_64BIT) |
||||
#define CFG_HRCW_HIGH (\ |
||||
HRCWH_PCI_HOST |\
|
||||
HRCWH_64_BIT_PCI |\
|
||||
HRCWH_PCI1_ARBITER_ENABLE |\
|
||||
HRCWH_PCI2_ARBITER_DISABLE |\
|
||||
HRCWH_CORE_ENABLE |\
|
||||
HRCWH_FROM_0X00000100 |\
|
||||
HRCWH_BOOTSEQ_DISABLE |\
|
||||
HRCWH_SW_WATCHDOG_DISABLE |\
|
||||
HRCWH_ROM_LOC_LOCAL_16BIT |\
|
||||
HRCWH_TSEC1M_IN_GMII |\
|
||||
HRCWH_TSEC2M_IN_GMII ) |
||||
#else |
||||
#define CFG_HRCW_HIGH (\ |
||||
HRCWH_PCI_HOST |\
|
||||
HRCWH_32_BIT_PCI |\
|
||||
HRCWH_PCI1_ARBITER_ENABLE |\
|
||||
HRCWH_PCI2_ARBITER_ENABLE |\
|
||||
HRCWH_CORE_ENABLE |\
|
||||
HRCWH_FROM_0X00000100 |\
|
||||
HRCWH_BOOTSEQ_DISABLE |\
|
||||
HRCWH_SW_WATCHDOG_DISABLE |\
|
||||
HRCWH_ROM_LOC_LOCAL_16BIT |\
|
||||
HRCWH_TSEC1M_IN_GMII |\
|
||||
HRCWH_TSEC2M_IN_GMII ) |
||||
#endif |
||||
|
||||
|
||||
#define CFG_HID0_INIT 0x000000000 |
||||
|
||||
#define CFG_HID0_FINAL CFG_HID0_INIT |
||||
|
||||
/* #define CFG_HID0_FINAL (\
|
||||
HID0_ENABLE_INSTRUCTION_CACHE |\
|
||||
HID0_ENABLE_M_BIT |\
|
||||
HID0_ENABLE_ADDRESS_BROADCAST ) */ |
||||
|
||||
#define CFG_HID2 0x000000000 |
||||
|
||||
/*
|
||||
* Internal Definitions |
||||
* |
||||
* Boot Flags |
||||
*/ |
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */ |
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
||||
#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ |
||||
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ |
||||
#endif |
||||
|
||||
|
||||
/*
|
||||
* Environment Configuration |
||||
*/ |
||||
|
||||
#if defined(CONFIG_TSEC_ENET) |
||||
#define CONFIG_ETHADDR 00:04:9f:11:22:33 |
||||
#define CONFIG_HAS_ETH1 |
||||
#define CONFIG_ETH1ADDR 00:E0:0C:00:7D:01 |
||||
#endif |
||||
|
||||
#define CONFIG_IPADDR 10.193.20.150 |
||||
|
||||
#define CONFIG_HOSTNAME unknown |
||||
#define CONFIG_ROOTPATH /tftpboot/10.193.20.150 |
||||
#define CONFIG_BOOTFILE /tftpboot/vmlinux.150 |
||||
|
||||
#define CONFIG_SERVERIP 10.193.20.58 |
||||
#define CONFIG_GATEWAYIP 192.168.1.1 |
||||
#define CONFIG_NETMASK 255.255.255.0 |
||||
|
||||
#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ |
||||
|
||||
#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ |
||||
#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ |
||||
|
||||
#define CONFIG_BAUDRATE 115200 |
||||
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"netdev=eth0\0" \
|
||||
"consoledev=ttyS0\0" \
|
||||
"ramdiskaddr=400000\0" \
|
||||
"ramdiskfile=ramfs.83xx\0" \
|
||||
|
||||
#define CONFIG_NFSBOOTCOMMAND \ |
||||
"setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=$serverip:$rootpath " \
|
||||
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
|
||||
"console=$consoledev,$baudrate $othbootargs;" \
|
||||
"tftp $loadaddr $bootfile;" \
|
||||
"bootm $loadaddr" |
||||
|
||||
#define CONFIG_RAMBOOTCOMMAND \ |
||||
"setenv bootargs root=/dev/ram rw " \
|
||||
"console=$consoledev,$baudrate $othbootargs;" \
|
||||
"tftp $ramdiskaddr $ramdiskfile;" \
|
||||
"tftp $loadaddr $bootfile;" \
|
||||
"bootm $loadaddr $ramdiskaddr" |
||||
|
||||
#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND |
||||
|
||||
#endif /* __CONFIG_H */ |
||||
@ -0,0 +1,289 @@ |
||||
/*
|
||||
* Copyright 2004 Freescale Semiconductor, Inc. |
||||
* |
||||
* See file CREDITS for list of people who contributed to this |
||||
* project. |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
*/ |
||||
|
||||
/*
|
||||
* mpc83xx.h |
||||
* |
||||
* MPC83xx specific definitions |
||||
*/ |
||||
|
||||
#ifndef __MPC83XX_H__ |
||||
#define __MPC83XX_H__ |
||||
|
||||
#if defined(CONFIG_E300) |
||||
#include <asm/e300.h> |
||||
#endif |
||||
|
||||
/*
|
||||
* MPC83xx cpu provide RCR register to do reset thing specially. easier |
||||
* to implement |
||||
*/ |
||||
|
||||
#define MPC83xx_RESET |
||||
|
||||
/*
|
||||
* System reset offset (PowerPC standard) |
||||
*/ |
||||
#define EXC_OFF_SYS_RESET 0x0100 |
||||
|
||||
/*
|
||||
* Default Internal Memory Register Space (Freescale recomandation) |
||||
*/ |
||||
#define CONFIG_DEFAULT_IMMR 0xFF400000 |
||||
|
||||
/*
|
||||
* Watchdog |
||||
*/ |
||||
#define SWCRR 0x0204 |
||||
#define SWCRR_SWTC 0xFFFF0000 /* Software Watchdog Time Count. */ |
||||
#define SWCRR_SWEN 0x00000004 /* Watchdog Enable bit. */ |
||||
#define SWCRR_SWRI 0x00000002 /* Software Watchdog Reset/Interrupt Select bit. */ |
||||
#define SWCRR_SWPR 0x00000001 /* Software Watchdog Counter Prescale bit. */ |
||||
#define SWCRR_RES ~(SWCRR_SWTC | SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR) |
||||
|
||||
#define SWCNR 0x0208 |
||||
#define SWCNR_SWCN 0x0000FFFF Software Watchdog Count Field. |
||||
#define SWCNR_RES ~(SWCNR_SWCN) |
||||
|
||||
#define SWSRR 0x020E |
||||
|
||||
/*
|
||||
* Default Internal Memory Register Space (Freescale recomandation) |
||||
*/ |
||||
#define IMMRBAR 0x0000 |
||||
#define IMMRBAR_BASE_ADDR 0xFFF00000 /* Identifies the 12 most-significant address bits of the base of the 1 MByte internal memory window. */ |
||||
#define IMMRBAR_RES ~(IMMRBAR_BASE_ADDR) |
||||
|
||||
/*
|
||||
* Default Internal Memory Register Space (Freescale recomandation) |
||||
*/ |
||||
#define LBLAWBAR0 0x0020 |
||||
#define LBLAWAR0 0x0024 |
||||
#define LBLAWBAR1 0x0028 |
||||
#define LBLAWAR1 0x002C |
||||
#define LBLAWBAR2 0x0030 |
||||
#define LBLAWAR2 0x0034 |
||||
#define LBLAWBAR3 0x0038 |
||||
#define LBLAWAR3 0x003C |
||||
|
||||
|
||||
/*
|
||||
* Base Registers & Option Registers |
||||
*/ |
||||
#define BR0 0x5000 |
||||
#define BR1 0x5008 |
||||
#define BR2 0x5010 |
||||
#define BR3 0x5018 |
||||
#define BR4 0x5020 |
||||
#define BR5 0x5028 |
||||
#define BR6 0x5030 |
||||
#define BR7 0x5038 |
||||
|
||||
#define BR_BA 0xFFFF8000 |
||||
#define BR_BA_SHIFT 15 |
||||
#define BR_PS 0x00001800 |
||||
#define BR_PS_SHIFT 11 |
||||
#define BR_DECC 0x00000600 |
||||
#define BR_DECC_SHIFT 9 |
||||
#define BR_WP 0x00000100 |
||||
#define BR_WP_SHIFT 8 |
||||
#define BR_MSEL 0x000000E0 |
||||
#define BR_MSEL_SHIFT 5 |
||||
#define BR_V 0x00000001 |
||||
#define BR_V_SHIFT 0 |
||||
#define BR_RES ~(BR_BA|BR_PS|BR_DECC|BR_WP|BR_MSEL|BR_V) |
||||
|
||||
#define OR0 0x5004 |
||||
#define OR1 0x500C |
||||
#define OR2 0x5014 |
||||
#define OR3 0x501C |
||||
#define OR4 0x5024 |
||||
#define OR5 0x502C |
||||
#define OR6 0x5034 |
||||
#define OR7 0x503C |
||||
|
||||
#define OR_GPCM_AM 0xFFFF8000 |
||||
#define OR_GPCM_AM_SHIFT 15 |
||||
#define OR_GPCM_BCTLD 0x00001000 |
||||
#define OR_GPCM_BCTLD_SHIFT 12 |
||||
#define OR_GPCM_CSNT 0x00000800 |
||||
#define OR_GPCM_CSNT_SHIFT 11 |
||||
#define OR_GPCM_ACS 0x00000600 |
||||
#define OR_GPCM_ACS_SHIFT 9 |
||||
#define OR_GPCM_XACS 0x00000100 |
||||
#define OR_GPCM_XACS_SHIFT 8 |
||||
#define OR_GPCM_SCY 0x000000F0 |
||||
#define OR_GPCM_SCY_SHIFT 4 |
||||
#define OR_GPCM_SETA 0x00000008 |
||||
#define OR_GPCM_SETA_SHIFT 3 |
||||
#define OR_GPCM_TRLX 0x00000004 |
||||
#define OR_GPCM_TRLX_SHIFT 2 |
||||
#define OR_GPCM_EHTR 0x00000002 |
||||
#define OR_GPCM_EHTR_SHIFT 1 |
||||
#define OR_GPCM_EAD 0x00000001 |
||||
#define OR_GPCM_EAD_SHIFT 0 |
||||
|
||||
#define OR_UPM_AM 0xFFFF8000 |
||||
#define OR_UPM_AM_SHIFT 15 |
||||
#define OR_UPM_XAM 0x00006000 |
||||
#define OR_UPM_XAM_SHIFT 13 |
||||
#define OR_UPM_BCTLD 0x00001000 |
||||
#define OR_UPM_BCTLD_SHIFT 12 |
||||
#define OR_UPM_BI 0x00000100 |
||||
#define OR_UPM_BI_SHIFT 8 |
||||
#define OR_UPM_TRLX 0x00000004 |
||||
#define OR_UPM_TRLX_SHIFT 2 |
||||
#define OR_UPM_EHTR 0x00000002 |
||||
#define OR_UPM_EHTR_SHIFT 1 |
||||
#define OR_UPM_EAD 0x00000001 |
||||
#define OR_UPM_EAD_SHIFT 0 |
||||
|
||||
#define OR_SDRAM_AM 0xFFFF8000 |
||||
#define OR_SDRAM_AM_SHIFT 15 |
||||
#define OR_SDRAM_XAM 0x00006000 |
||||
#define OR_SDRAM_XAM_SHIFT 13 |
||||
#define OR_SDRAM_COLS 0x00001C00 |
||||
#define OR_SDRAM_COLS_SHIFT 10 |
||||
#define OR_SDRAM_ROWS 0x000001C0 |
||||
#define OR_SDRAM_ROWS_SHIFT 6 |
||||
#define OR_SDRAM_PMSEL 0x00000020 |
||||
#define OR_SDRAM_PMSEL_SHIFT 5 |
||||
#define OR_SDRAM_EAD 0x00000001 |
||||
#define OR_SDRAM_EAD_SHIFT 0 |
||||
|
||||
/*
|
||||
* Hard Reset Configration Word - High |
||||
*/
|
||||
#define HRCWH_PCI_AGENT 0x00000000 |
||||
#define HRCWH_PCI_HOST 0x80000000 |
||||
|
||||
#define HRCWH_32_BIT_PCI 0x00000000 |
||||
#define HRCWH_64_BIT_PCI 0x40000000 |
||||
|
||||
#define HRCWH_PCI1_ARBITER_DISABLE 0x00000000 |
||||
#define HRCWH_PCI1_ARBITER_ENABLE 0x20000000 |
||||
|
||||
#define HRCWH_PCI2_ARBITER_DISABLE 0x00000000 |
||||
#define HRCWH_PCI2_ARBITER_ENABLE 0x10000000 |
||||
|
||||
#define HRCWH_CORE_DISABLE 0x08000000 |
||||
#define HRCWH_CORE_ENABLE 0x00000000 |
||||
|
||||
#define HRCWH_FROM_0X00000100 0x00000000 |
||||
#define HRCWH_FROM_0XFFF00100 0x04000000 |
||||
|
||||
#define HRCWH_BOOTSEQ_DISABLE 0x00000000 |
||||
#define HRCWH_BOOTSEQ_NORMAL 0x01000000 |
||||
#define HRCWH_BOOTSEQ_EXTENDED 0x02000000 |
||||
|
||||
#define HRCWH_SW_WATCHDOG_DISABLE 0x00000000 |
||||
#define HRCWH_SW_WATCHDOG_ENABLE 0x00800000 |
||||
|
||||
#define HRCWH_ROM_LOC_DDR_SDRAM 0x00000000 |
||||
#define HRCWH_ROM_LOC_PCI1 0x00100000 |
||||
#define HRCWH_ROM_LOC_PCI2 0x00200000 |
||||
#define HRCWH_ROM_LOC_LOCAL_8BIT 0x00500000 |
||||
#define HRCWH_ROM_LOC_LOCAL_16BIT 0x00600000 |
||||
#define HRCWH_ROM_LOC_LOCAL_32BIT 0x00700000 |
||||
|
||||
#define HRCWH_TSEC1M_IN_RGMII 0x00000000 |
||||
#define HRCWH_TSEC1M_IN_RTBI 0x00004000 |
||||
#define HRCWH_TSEC1M_IN_GMII 0x00008000 |
||||
#define HRCWH_TSEC1M_IN_TBI 0x0000C000 |
||||
|
||||
#define HRCWH_TSEC2M_IN_RGMII 0x00000000 |
||||
#define HRCWH_TSEC2M_IN_RTBI 0x00001000 |
||||
#define HRCWH_TSEC2M_IN_GMII 0x00002000 |
||||
#define HRCWH_TSEC2M_IN_TBI 0x00003000 |
||||
|
||||
#define HRCWH_BIG_ENDIAN 0x00000000 |
||||
#define HRCWH_LITTLE_ENDIAN 0x00000008 |
||||
|
||||
/*
|
||||
* Hard Reset Configration Word - Low |
||||
*/ |
||||
#define HRCWL_LCL_BUS_TO_SCB_CLK_1X1 0x00000000 |
||||
#define HRCWL_LCL_BUS_TO_SCB_CLK_2X1 0x80000000 |
||||
|
||||
#define HRCWL_DDR_TO_SCB_CLK_1X1 0x00000000 |
||||
#define HRCWL_DDR_TO_SCB_CLK_2X1 0x40000000 |
||||
|
||||
#define HRCWL_CSB_TO_CLKIN_16X1 0x00000000 |
||||
#define HRCWL_CSB_TO_CLKIN_1X1 0x01000000 |
||||
#define HRCWL_CSB_TO_CLKIN_2X1 0x02000000 |
||||
#define HRCWL_CSB_TO_CLKIN_3X1 0x03000000 |
||||
#define HRCWL_CSB_TO_CLKIN_4X1 0x04000000 |
||||
#define HRCWL_CSB_TO_CLKIN_5X1 0x05000000 |
||||
#define HRCWL_CSB_TO_CLKIN_6X1 0x06000000 |
||||
#define HRCWL_CSB_TO_CLKIN_7X1 0x07000000 |
||||
#define HRCWL_CSB_TO_CLKIN_8X1 0x08000000 |
||||
#define HRCWL_CSB_TO_CLKIN_9X1 0x09000000 |
||||
#define HRCWL_CSB_TO_CLKIN_10X1 0x0A000000 |
||||
#define HRCWL_CSB_TO_CLKIN_11X1 0x0B000000 |
||||
#define HRCWL_CSB_TO_CLKIN_12X1 0x0C000000 |
||||
#define HRCWL_CSB_TO_CLKIN_13X1 0x0D000000 |
||||
#define HRCWL_CSB_TO_CLKIN_14X1 0x0E000000 |
||||
#define HRCWL_CSB_TO_CLKIN_15X1 0x0F000000 |
||||
|
||||
#define HRCWL_VCO_BYPASS 0x00000000 |
||||
#define HRCWL_VCO_1X2 0x00000000 |
||||
#define HRCWL_VCO_1X4 0x00200000 |
||||
#define HRCWL_VCO_1X8 0x00400000 |
||||
|
||||
#define HRCWL_CORE_TO_CSB_BYPASS 0x00000000 |
||||
#define HRCWL_CORE_TO_CSB_1X1 0x00020000 |
||||
#define HRCWL_CORE_TO_CSB_1_5X1 0x00030000 |
||||
#define HRCWL_CORE_TO_CSB_2X1 0x00040000 |
||||
#define HRCWL_CORE_TO_CSB_2_5X1 0x00050000 |
||||
#define HRCWL_CORE_TO_CSB_3X1 0x00060000 |
||||
|
||||
/*
|
||||
* LCRR - Clock Ratio Register (10.3.1.16)
|
||||
*/ |
||||
#define LCRR_DBYP 0x80000000 |
||||
#define LCRR_DBYP_SHIFT 31 |
||||
#define LCRR_BUFCMDC 0x30000000 |
||||
#define LCRR_BUFCMDC_1 0x10000000 |
||||
#define LCRR_BUFCMDC_2 0x20000000 |
||||
#define LCRR_BUFCMDC_3 0x30000000 |
||||
#define LCRR_BUFCMDC_4 0x00000000 |
||||
#define LCRR_BUFCMDC_SHIFT 28 |
||||
#define LCRR_ECL 0x03000000 |
||||
#define LCRR_ECL_4 0x00000000 |
||||
#define LCRR_ECL_5 0x01000000 |
||||
#define LCRR_ECL_6 0x02000000 |
||||
#define LCRR_ECL_7 0x03000000 |
||||
#define LCRR_ECL_SHIFT 24 |
||||
#define LCRR_EADC 0x00030000 |
||||
#define LCRR_EADC_1 0x00010000 |
||||
#define LCRR_EADC_2 0x00020000 |
||||
#define LCRR_EADC_3 0x00030000 |
||||
#define LCRR_EADC_4 0x00000000 |
||||
#define LCRR_EADC_SHIFT 16 |
||||
#define LCRR_CLKDIV 0x0000000F |
||||
#define LCRR_CLKDIV_2 0x00000002 |
||||
#define LCRR_CLKDIV_4 0x00000004 |
||||
#define LCRR_CLKDIV_8 0x00000008 |
||||
#define LCRR_CLKDIV_SHIFT 0 |
||||
|
||||
|
||||
#endif /* __MPC83XX_H__ */ |
||||
Loading…
Reference in new issue